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Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +00005 */
6
7/*
8 * BSC9131 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
harninder rai604b3ca2014-12-02 15:55:47 +053014#define CONFIG_DISPLAY_BOARDINFO
15
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000016#ifdef CONFIG_BSC9131RDB
17#define CONFIG_BSC9131
18#define CONFIG_NAND_FSL_IFC
19#endif
20
21#ifdef CONFIG_SPIFLASH
22#define CONFIG_RAMBOOT_SPIFLASH
23#define CONFIG_SYS_RAMBOOT
24#define CONFIG_SYS_EXTRA_ENV_RELOC
25#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053026#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000027#endif
28
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053029#ifdef CONFIG_NAND
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053030#define CONFIG_SPL_INIT_MINIMAL
31#define CONFIG_SPL_SERIAL_SUPPORT
32#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahaafffcb02013-12-11 12:42:11 +053033#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053034#define CONFIG_SPL_FLUSH_IMAGE
35#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
36
37#define CONFIG_SYS_TEXT_BASE 0x00201000
38#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
39#define CONFIG_SPL_MAX_SIZE 8192
40#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
41#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053042#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053043#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
44#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
45#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
46#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000047#endif
48
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +053049#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
51#else
52#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
53#endif
54
55
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000056/* High Level Configuration Options */
57#define CONFIG_BOOKE /* BOOKE */
58#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000059#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta12af67f2014-10-15 11:35:31 +053060#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000061
62#define CONFIG_FSL_LAW /* Use common FSL init code */
63#define CONFIG_TSEC_ENET
64#define CONFIG_ENV_OVERWRITE
65
66#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
Priyanka Jainf9146bd2013-04-01 12:12:45 +053067#if defined(CONFIG_SYS_CLK_100)
68#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
69#else
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000070#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
Priyanka Jainf9146bd2013-04-01 12:12:45 +053071#endif
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000072
73#define CONFIG_HWCONFIG
74/*
75 * These can be toggled for performance analysis, otherwise use default.
76 */
77#define CONFIG_L2_CACHE /* toggle L2 cache */
78#define CONFIG_BTB /* enable branch predition */
79
80#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
81#define CONFIG_SYS_MEMTEST_END 0x01ffffff
82
83/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070084#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +000085#undef CONFIG_SYS_DDR_RAW_TIMING
86#undef CONFIG_DDR_SPD
87#define CONFIG_SYS_SPD_BUS_NUM 0
88#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
89
90#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
91
92#ifndef __ASSEMBLY__
93extern unsigned long get_sdram_size(void);
94#endif
95#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
96#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98
99#define CONFIG_NUM_DDR_CONTROLLERS 1
100#define CONFIG_DIMM_SLOTS_PER_CTLR 1
101#define CONFIG_CHIP_SELECTS_PER_CTRL 1
102
103#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
104#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
105#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
106
107#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
108#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
109#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
110#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
111
112#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
113#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
114#define CONFIG_SYS_DDR_RCW_1 0x00000000
115#define CONFIG_SYS_DDR_RCW_2 0x00000000
116#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
117#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
118#define CONFIG_SYS_DDR_TIMING_4 0x00000001
119#define CONFIG_SYS_DDR_TIMING_5 0x02401400
120
121#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
122#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
123#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
124#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
125#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
126#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
127#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
128#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
129#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
130
131/*
132 * Base addresses -- Note these are effective addresses where the
133 * actual resources get mapped (not physical addresses)
134 */
135/* relocated CCSRBAR */
136#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
137#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
138
139#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
140 /* CONFIG_SYS_IMMR */
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530141/* DSP CCSRBAR */
142#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
143#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000144
145/*
146 * Memory map
147 *
148 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
149 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530150 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000151 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
152 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
153 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
154 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
Priyanka Jainf81e8b22013-04-04 09:31:54 +0530155 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000156 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
157 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
158 *
159 */
160
161/*
162 * IFC Definitions
163 */
164#define CONFIG_SYS_NO_FLASH
165
166/* NAND Flash on IFC */
167#define CONFIG_SYS_NAND_BASE 0xff800000
168#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
169
170#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
171 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
172 | CSPR_MSEL_NAND /* MSEL = NAND */ \
173 | CSPR_V)
174#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
175
176#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
177 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
178 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
179 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
180 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
181 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
182 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
183
184/* NAND Flash Timing Params */
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530185#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
186 | FTIM0_NAND_TWP(0x05) \
187 | FTIM0_NAND_TWCHT(0x02) \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000188 | FTIM0_NAND_TWH(0x04))
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530189#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
190 | FTIM1_NAND_TWBE(0x1E) \
191 | FTIM1_NAND_TRR(0x07) \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000192 | FTIM1_NAND_TRP(0x05))
193#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
194 | FTIM2_NAND_TREH(0x04) \
Prabhakar Kushwaha1cf874a2013-09-10 17:33:12 +0530195 | FTIM2_NAND_TWHRE(0x11))
196#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000197
198#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
199#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000200#define CONFIG_CMD_NAND
201#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
202
203#define CONFIG_SYS_NAND_DDR_LAW 11
204
205/* Set up IFC registers for boot location NAND */
206#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
207#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
208#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
209#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
210#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
211#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
212#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
213
214#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
215
216#define CONFIG_SYS_INIT_RAM_LOCK
217#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sun515fbb42016-04-06 13:22:10 -0700218#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000219
York Sun515fbb42016-04-06 13:22:10 -0700220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000221 - GENERATED_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
223
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530224#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000225#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
226
227/* Serial Port */
228#define CONFIG_CONS_INDEX 1
229#undef CONFIG_SERIAL_SOFTWARE_FIFO
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000230#define CONFIG_SYS_NS16550_SERIAL
231#define CONFIG_SYS_NS16550_REG_SIZE 1
232#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530233#ifdef CONFIG_SPL_BUILD
234#define CONFIG_NS16550_MIN_FUNCTIONS
235#endif
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000236
237#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
238
239#define CONFIG_SYS_BAUDRATE_TABLE \
240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
241
242#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
243
244/* Use the HUSH parser */
245#define CONFIG_SYS_HUSH_PARSER
246#ifdef CONFIG_SYS_HUSH_PARSER
247#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
248#endif
249
Heiko Schocherf2850742012-10-24 13:48:22 +0200250#define CONFIG_SYS_I2C
251#define CONFIG_SYS_I2C_FSL
252#define CONFIG_SYS_FSL_I2C_SPEED 400000
253#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
254#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000255
256/* I2C EEPROM */
257#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000258#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
259#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
260#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
261
262#define CONFIG_CMD_I2C
263
264
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000265/* eSPI - Enhanced SPI */
266#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000267#define CONFIG_CMD_SF
268#define CONFIG_SF_DEFAULT_SPEED 10000000
269#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
270#endif
271
272#if defined(CONFIG_TSEC_ENET)
273
274#define CONFIG_MII /* MII PHY management */
275#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
276#define CONFIG_TSEC1 1
277#define CONFIG_TSEC1_NAME "eTSEC1"
278#define CONFIG_TSEC2 1
279#define CONFIG_TSEC2_NAME "eTSEC2"
280
281#define TSEC1_PHY_ADDR 0
282#define TSEC2_PHY_ADDR 3
283
284#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
285#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
286
287#define TSEC1_PHYIDX 0
288
289#define TSEC2_PHYIDX 0
290
291#define CONFIG_ETHPRIME "eTSEC1"
292
293#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
294
295#endif /* CONFIG_TSEC_ENET */
296
297/*
298 * Environment
299 */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000300#if defined(CONFIG_RAMBOOT_SPIFLASH)
301#define CONFIG_ENV_IS_IN_SPI_FLASH
302#define CONFIG_ENV_SPI_BUS 0
303#define CONFIG_ENV_SPI_CS 0
304#define CONFIG_ENV_SPI_MAX_HZ 10000000
305#define CONFIG_ENV_SPI_MODE 0
306#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
307#define CONFIG_ENV_SECT_SIZE 0x10000
308#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530309#elif defined(CONFIG_NAND)
310#define CONFIG_ENV_IS_IN_NAND
311#define CONFIG_SYS_EXTRA_ENV_RELOC
312#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +0530313#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530314#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
315#elif defined(CONFIG_SYS_RAMBOOT)
316#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000317#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Prabhakar Kushwahabc84b5e2013-04-16 13:28:25 +0530318#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000319#endif
320
321#define CONFIG_LOADS_ECHO /* echo on for serial download */
322#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
323
324/*
325 * Command line configuration.
326 */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000327#define CONFIG_CMD_DHCP
328#define CONFIG_CMD_ERRATA
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000329#define CONFIG_CMD_EXT2
330#define CONFIG_CMD_FAT
331#define CONFIG_CMD_IRQ
332#define CONFIG_CMD_MII
333#define CONFIG_DOS_PARTITION
334#define CONFIG_CMD_PING
335#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000336
337/*
338 * Miscellaneous configurable options
339 */
340#define CONFIG_SYS_LONGHELP /* undef to save memory */
341#define CONFIG_CMDLINE_EDITING /* Command-line editing */
342#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
343#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000344
345#if defined(CONFIG_CMD_KGDB)
346#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
347#else
348#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
349#endif
350#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
351 /* Print Buffer Size */
352#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
353#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000354
355/*
356 * For booting Linux, the board info and command line data
357 * have to be in the first 64 MB of memory, since this is
358 * the maximum mapped by the Linux kernel during initialization.
359 */
360#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
361#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
362
363#if defined(CONFIG_CMD_KGDB)
364#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000365#endif
366
Ruchika Gupta12af67f2014-10-15 11:35:31 +0530367/* Hash command with SHA acceleration supported in hardware */
368#ifdef CONFIG_FSL_CAAM
369#define CONFIG_CMD_HASH
370#define CONFIG_SHA_HW_ACCEL
371#endif
372
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000373#define CONFIG_USB_EHCI
374
375#ifdef CONFIG_USB_EHCI
376#define CONFIG_CMD_USB
377#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
378#define CONFIG_USB_EHCI_FSL
379#define CONFIG_USB_STORAGE
380#define CONFIG_HAS_FSL_DR_USB
381#endif
382
383/*
Ashish Kumarc4570202014-10-07 18:02:23 +0530384 * Dynamic MTD Partition support with mtdparts
385 */
386#define CONFIG_MTD_DEVICE
387#define CONFIG_MTD_PARTITIONS
388#define CONFIG_CMD_MTDPARTS
389#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
390#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
391 "8m(kernel),512k(dtb),-(fs)"
392/*
393 * Override partitions in device tree using info
394 * in "mtdparts" environment variable
395 */
396#ifdef CONFIG_CMD_MTDPARTS
397#define CONFIG_FDT_FIXUP_PARTITIONS
398#endif
399
400/*
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000401 * Environment Configuration
402 */
403
404#if defined(CONFIG_TSEC_ENET)
405#define CONFIG_HAS_ETH0
406#endif
407
408#define CONFIG_HOSTNAME BSC9131rdb
409#define CONFIG_ROOTPATH "/opt/nfsroot"
410#define CONFIG_BOOTFILE "uImage"
411#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
412
413#define CONFIG_BAUDRATE 115200
harninder rai9da3adc2014-12-15 12:58:45 +0530414#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000415
416#define CONFIG_EXTRA_ENV_SETTINGS \
417 "netdev=eth0\0" \
418 "uboot=" CONFIG_UBOOTPATH "\0" \
419 "loadaddr=1000000\0" \
420 "bootfile=uImage\0" \
421 "consoledev=ttyS0\0" \
422 "ramdiskaddr=2000000\0" \
423 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
424 "fdtaddr=c00000\0" \
425 "fdtfile=bsc9131rdb.dtb\0" \
426 "bdev=sda1\0" \
427 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
Priyanka Jain20732df2013-04-04 14:40:32 +0530428 "bootm_size=0x37000000\0" \
429 "othbootargs=ramdisk_size=600000 " \
430 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
Prabhakar Kushwaha63956d52012-04-24 20:17:15 +0000431 "usbext2boot=setenv bootargs root=/dev/ram rw " \
432 "console=$consoledev,$baudrate $othbootargs; " \
433 "usb start;" \
434 "ext2load usb 0:4 $loadaddr $bootfile;" \
435 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
436 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
437 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
438
439#define CONFIG_RAMBOOTCOMMAND \
440 "setenv bootargs root=/dev/ram rw " \
441 "console=$consoledev,$baudrate $othbootargs; " \
442 "tftp $ramdiskaddr $ramdiskfile;" \
443 "tftp $loadaddr $bootfile;" \
444 "tftp $fdtaddr $fdtfile;" \
445 "bootm $loadaddr $ramdiskaddr $fdtaddr"
446
447#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
448
449#endif /* __CONFIG_H */