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git01.mediatek.com / filogic / uboot / f1264ba094e0f91f65f08624f892383fe7e8bc61 / . / arch / arm / dts / imx8mp-verdin-wifi-dev-u-boot.dtsi
blob: 0162f9b2da375203a94ce71f40f2bd1ebbac8844 [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
15
16 wdt-reboot {
17 compatible = "wdt-reboot";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]19 wdt = <&wdog1>;
20 };
21};
22
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]23&{/aliases} {
24 eeprom0 = &eeprom_module;
25 eeprom1 = &eeprom_carrier_board;
26 eeprom2 = &eeprom_display_adapter;
27};
28
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]29&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-all;
31 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]32 /delete-property/ assigned-clocks;
33 /delete-property/ assigned-clock-parents;
34 /delete-property/ assigned-clock-rates;
35
36};
37
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]38&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]40};
41
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]42&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]44};
45
46&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]48
49 regulator-ethphy {
50 gpio-hog;
51 gpios = <20 GPIO_ACTIVE_HIGH>;
52 line-name = "reg_ethphy";
53 output-high;
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_reg_eth>;
56 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]57};
58
59&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]61};
62
63&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Andrejs Cainikovsdd1587c2023-07-11 11:09:18 +0200[diff] [blame]65
66 ctrl-sleep-moci-hog {
67 bootph-pre-ram;
68 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]69};
70
71&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]73};
74
75&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]77
78 eeprom_module: eeprom@50 {
79 compatible = "i2c-eeprom";
80 pagesize = <16>;
81 reg = <0x50>;
82 };
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]83};
84
85&i2c2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]87};
88
89&i2c3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]91};
92
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]93&i2c4 {
94 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
95 eeprom_display_adapter: eeprom@50 {
96 compatible = "i2c-eeprom";
97 pagesize = <16>;
98 reg = <0x50>;
99 };
100
101 /* EEPROM on carrier board */
102 eeprom_carrier_board: eeprom@57 {
103 compatible = "i2c-eeprom";
104 pagesize = <16>;
105 reg = <0x57>;
106 };
107};
108
109&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]111};
112
Andrejs Cainikovsdd1587c2023-07-11 11:09:18 +0200[diff] [blame]113&pinctrl_ctrl_sleep_moci {
114 bootph-pre-ram;
115};
116
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]117&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]119};
120
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]121&pinctrl_usdhc2_pwr_en {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]123 u-boot,off-on-delay-us = <20000>;
124};
125
126&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]128};
129
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]130&pinctrl_usdhc2_cd {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]131 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]132};
133
134&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]136};
137
138&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]140};
141
142&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]144};
145
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]146&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]148};
149
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]150&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]151 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]152};
153
154&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]155 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]156};
157
158&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]159 bootph-pre-ram;
Andrejs Cainikovs654d41c2022-10-04 13:06:30 +0200[diff] [blame]160};
161
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]162&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]163 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]164};
165
Marcel Ziswilerf8621462022-07-21 15:46:44 +0200[diff] [blame]166&usdhc1 {
167 status = "disabled";
168};
169
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]170&usdhc2 {
171 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
172 assigned-clock-rates = <400000000>;
173 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
174 sd-uhs-ddr50;
175 sd-uhs-sdr104;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]176 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]177};
178
179&usdhc3 {
180 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
181 assigned-clock-rates = <400000000>;
182 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
183 mmc-hs400-1_8v;
184 mmc-hs400-enhanced-strobe;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]185 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]186};
187
188&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]189 bootph-pre-ram;
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]190};