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git01.mediatek.com / filogic / uboot / f1264ba094e0f91f65f08624f892383fe7e8bc61 / . / arch / arm / dts / imx8mm-phg-u-boot.dtsi
blob: 3ced97cfaafa5681f5606262d326056fba0c0387 [file] [log] [blame]
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]13 };
14
15 firmware {
16 optee {
17 compatible = "linaro,optee-tz";
18 method = "smc";
19 };
20 };
21};
22
23&aips4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]25};
26
27&reg_usdhc2_vmmc {
28 u-boot,off-on-delay-us = <20000>;
29};
30
31&pinctrl_reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]33};
34
35&pinctrl_uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]37};
38
39&pinctrl_usdhc2_gpio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]41};
42
43&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]45};
46
47&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]48 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]49};
50
51&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]53};
54
55&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]57};
58
59&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]61};
62
63&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]65};
66
67&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]69};
70
71&uart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]73};
74
75&usbmisc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]77};
78
79&usbphynop1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]81};
82
83&usbotg1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]85};
86
87&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]89};
90
91&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]93 sd-uhs-sdr104;
94 sd-uhs-ddr50;
95 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
96 assigned-clock-rates = <400000000>;
97 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
98};
99
100&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]102 mmc-hs400-1_8v;
103 mmc-hs400-enhanced-strobe;
104 /*
105 * prevents voltage switch warn: driver will switch even at
106 * fixed voltage
107 */
108 /delete-property/ vmmc-supply;
109 /delete-property/ vqmmc-supply;
110 assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
111 assigned-clock-rates = <400000000>;
112 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
113};
114
115&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]117};
118
119&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]121};
122
123&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]125};
126
127&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]129};
130
131&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]133};
134
135&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Fabio Estevam2ef69ef2023-01-10 17:18:08 -0300[diff] [blame]137};