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git01.mediatek.com / filogic / uboot / f1264ba094e0f91f65f08624f892383fe7e8bc61 / . / arch / arm / dts / dra72-evm-revc-u-boot.dtsi
blob: 8e7dc719bf8578ce6624da1f57461f1cbd78ef2a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]2/*
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
Lokesh Vutlae6734ae2017-08-21 12:51:00 +0530[diff] [blame]4 */
5
6#include "omap5-u-boot.dtsi"
7
8&pcf_gpio_21{
9 u-boot,i2c-offset-len = <0>;
10};
11
12&pcf_hdmi{
13 u-boot,i2c-offset-len = <0>;
14};
15
16&cpsw_emac0 {
17 phy-handle = <&dp83867_0>;
18};
19
20&cpsw_emac1 {
21 phy-handle = <&dp83867_1>;
22};
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]23
24&mmc2_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]26};
27
28&mmc2_pins_hs {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]30};
31
32&mmc2_pins_ddr_rev20 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]34};
35
36&mmc2_iodelay_ddr_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]38};
39
40&mmc2_pins_hs200 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]42};
43
44&mmc2_iodelay_hs200_rev20_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Jean-Jacques Hiblota45f72d2018-02-27 17:05:50 +0100[diff] [blame]46};
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]47
48&omap_dwc3_1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]50};
51
52&usb1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]54 dr_mode = "peripheral";
55};
56
57&usb2_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]59};
60
61&usb3_phy1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Faiz Abbase220a462019-10-09 12:35:18 +0200[diff] [blame]63};