blob: 0fd6fb04f86903cd3034e3626b7982b35f32328e [file] [log] [blame]
Macpaul Lin01cfa112010-10-19 17:05:51 +08001/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin01cfa112010-10-19 17:05:51 +08007 */
8
9#include <common.h>
rickf1113c92017-05-18 14:37:53 +080010#if defined(CONFIG_FTMAC100)
Macpaul Lin01cfa112010-10-19 17:05:51 +080011#include <netdev.h>
rickf1113c92017-05-18 14:37:53 +080012#endif
13#include <linux/io.h>
Macpaul Lin01cfa112010-10-19 17:05:51 +080014
15#include <faraday/ftsdc010.h>
16#include <faraday/ftsmc020.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20/*
21 * Miscellaneous platform dependent initializations
22 */
23
24int board_init(void)
25{
26 /*
27 * refer to BOOT_PARAMETER_PA_BASE within
28 * "linux/arch/nds32/include/asm/misc_spec.h"
29 */
rickf1113c92017-05-18 14:37:53 +080030 printf("Board: %s\n" , CONFIG_SYS_BOARD);
Macpaul Lin01cfa112010-10-19 17:05:51 +080031 gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
32 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
33
Macpaul Lin01cfa112010-10-19 17:05:51 +080034 return 0;
35}
36
37int dram_init(void)
38{
39 unsigned long sdram_base = PHYS_SDRAM_0;
ken kuo7abab272013-06-08 11:14:09 +080040 unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
Macpaul Lin01cfa112010-10-19 17:05:51 +080041 unsigned long actual_size;
42
43 actual_size = get_ram_size((void *)sdram_base, expected_size);
44
45 gd->ram_size = actual_size;
46
47 if (expected_size != actual_size) {
48 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
49 actual_size >> 20, expected_size >> 20);
50 }
51
52 return 0;
53}
54
Simon Glass2f949c32017-03-31 08:40:32 -060055int dram_init_banksize(void)
ken kuo7abab272013-06-08 11:14:09 +080056{
57 gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
58 gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
59 gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
60 gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
Simon Glass2f949c32017-03-31 08:40:32 -060061
62 return 0;
ken kuo7abab272013-06-08 11:14:09 +080063}
64
rickf1113c92017-05-18 14:37:53 +080065#if defined(CONFIG_FTMAC100)
Macpaul Lin01cfa112010-10-19 17:05:51 +080066int board_eth_init(bd_t *bd)
67{
68 return ftmac100_initialize(bd);
69}
rickf1113c92017-05-18 14:37:53 +080070#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +080071
72ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
73{
74 if (banknum == 0) { /* non-CFI boot flash */
75 info->portwidth = FLASH_CFI_8BIT;
76 info->chipwidth = FLASH_CFI_BY8;
77 info->interface = FLASH_CFI_X8;
78 return 1;
79 } else {
80 return 0;
81 }
82}
83
84int board_mmc_init(bd_t *bis)
85{
rickf1113c92017-05-18 14:37:53 +080086#ifdef CONFIG_FTSDC010
Macpaul Lin01cfa112010-10-19 17:05:51 +080087 ftsdc010_mmc_init(0);
rickf1113c92017-05-18 14:37:53 +080088#endif
Macpaul Lin01cfa112010-10-19 17:05:51 +080089 return 0;
90}