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Marcel Ziswiler99d768b2019-05-31 18:56:39 +03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2019 Toradex
4 */
5
6#ifndef __COLIBRI_IMX8X_H
7#define __COLIBRI_IMX8X_H
8
9#include <asm/arch/imx-regs.h>
10#include <linux/sizes.h>
Simon Glassfb64e362020-05-10 11:40:09 -060011#include <linux/stringify.h>
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030012
Tom Rini376b88a2022-10-28 20:27:13 -040013#define CFG_SYS_FSL_ESDHC_ADDR 0
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030014#define USDHC1_BASE_ADDR 0x5b010000
15#define USDHC2_BASE_ADDR 0x5b020000
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030016
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030017#define MEM_LAYOUT_ENV_SETTINGS \
18 "fdt_addr_r=0x83000000\0" \
19 "kernel_addr_r=0x81000000\0" \
20 "ramdisk_addr_r=0x83800000\0" \
21 "scriptaddr=0x80800000\0"
22
23#ifdef CONFIG_AHAB_BOOT
24#define AHAB_ENV "sec_boot=yes\0"
25#else
26#define AHAB_ENV "sec_boot=no\0"
27#endif
28
29/* Boot M4 */
30#define M4_BOOT_ENV \
31 "m4_0_image=m4_0.bin\0" \
32 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
33 "${m4_0_image}\0" \
34 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
35
36#define MFG_NAND_PARTITION ""
37
38#define BOOT_TARGET_DEVICES(func) \
39 func(MMC, mmc, 1) \
40 func(MMC, mmc, 0) \
41 func(DHCP, dhcp, na)
42#include <config_distro_bootcmd.h>
43#undef BOOTENV_RUN_NET_USB_START
44#define BOOTENV_RUN_NET_USB_START ""
45
Tom Rini0c6ed312022-12-04 10:04:52 -050046#define CFG_MFG_ENV_SETTINGS \
Oleksandr Suvorov408b8d92020-06-16 22:20:01 +030047 "mfgtool_args=setenv bootargs ${consoleargs} " \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030048 "rdinit=/linuxrc g_mass_storage.stall=0 " \
49 "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
50 "g_mass_storage.idProduct=0x37FF " \
51 "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
52 "${vidargs} clk_ignore_unused\0" \
53 "initrd_addr=0x83800000\0" \
54 "initrd_high=0xffffffff\0" \
55 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
56 "${fdt_addr};\0" \
57
58/* Initial environment variables */
Tom Rinic9edebe2022-12-04 10:03:50 -050059#define CFG_EXTRA_ENV_SETTINGS \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030060 AHAB_ENV \
61 BOOTENV \
Tom Rini0c6ed312022-12-04 10:04:52 -050062 CFG_MFG_ENV_SETTINGS \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030063 M4_BOOT_ENV \
64 MEM_LAYOUT_ENV_SETTINGS \
Igor Opaniuk8ff1c242019-08-23 20:00:48 +030065 "boot_file=Image\0" \
Igor Opaniuk84c1a2d2022-04-13 11:33:27 +020066 "boot_script_dhcp=boot.scr\0" \
Oleksandr Suvorov408b8d92020-06-16 22:20:01 +030067 "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030068 "fdt_addr=0x83000000\0" \
69 "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
70 "fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
71 "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
72 "image=Image\0" \
73 "initrd_addr=0x83800000\0" \
74 "initrd_high=0xffffffffffffffff\0" \
Oleksandr Suvorov408b8d92020-06-16 22:20:01 +030075 "mmcargs=setenv bootargs ${consoleargs} " \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030076 "root=PARTUUID=${uuid} rootwait " \
77 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050078 "mmcpart=1\0" \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030079 "panel=NULL\0" \
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030080 "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
81 "if test \"$confirm\" = \"y\"; then " \
82 "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
83 "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
84 "${blkcnt}; fi\0" \
85 "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
86
87/* Link Definitions */
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030088
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030089/* Environment in eMMC, before config block at the end of 1st "boot sector" */
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030090
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030091/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
Tom Rini376b88a2022-10-28 20:27:13 -040092#define CFG_SYS_FSL_USDHC_NUM 2
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030093
Tom Rinibb4dd962022-11-16 13:10:37 -050094#define CFG_SYS_SDRAM_BASE 0x80000000
Marcel Ziswiler99d768b2019-05-31 18:56:39 +030095#define PHYS_SDRAM_1 0x80000000
96#define PHYS_SDRAM_2 0x880000000
97#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
98#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
99
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300100/* Generic Timer Definitions */
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300101
102#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
103#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
104
105#endif /* __COLIBRI_IMX8X_H */