| Simon Glass | fcfd26e | 2019-12-08 17:40:14 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ARCH_CPU_H |
| 7 | #define _ASM_ARCH_CPU_H |
| 8 | |
| 9 | /* Common Timer Copy (CTC) frequency - 19.2MHz */ |
| 10 | #define CTC_FREQ 19200000 |
| 11 | |
| 12 | #define MAX_PCIE_PORTS 6 |
| 13 | #define CLKREQ_DISABLED 0xf |
| 14 | |
| 15 | #ifndef __ASSEMBLY__ |
| 16 | /* Flush L1D to L2 */ |
| 17 | void cpu_flush_l1d_to_l2(void); |
| Simon Glass | f07f4b9 | 2020-11-04 09:57:15 -0700 | [diff] [blame^] | 18 | |
| 19 | /** |
| 20 | * Enable emulation of the PM timer |
| 21 | * |
| 22 | * Some legacy OSes cannot tolerate the ACPI timer stoping during idle states, |
| 23 | * and this results in higher power consumption. ACPI timer emulation allows |
| 24 | * disabling of the ACPI Timer (PM1_TMR) to have no impact on the system, with |
| 25 | * the exception that TMR_STS will not be set on an overflow condition. All |
| 26 | * aligned 32-bit reads from the ACPI Timer port are valid and will behave as if |
| 27 | * the ACPI timer remains enabled. |
| 28 | * |
| 29 | * @pmc: PMC device |
| 30 | */ |
| 31 | void enable_pm_timer_emulation(const struct udevice *pmc); |
| Simon Glass | fcfd26e | 2019-12-08 17:40:14 -0700 | [diff] [blame] | 32 | #endif |
| 33 | |
| 34 | #endif /* _ASM_ARCH_CPU_H */ |