Jim Liu | 2568856 | 2022-04-19 13:32:20 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | |
| 3 | #ifndef _CLK_NPCM_H_ |
| 4 | #define _CLK_NPCM_H_ |
| 5 | |
| 6 | #include <clk-uclass.h> |
| 7 | |
| 8 | /* Register offsets */ |
| 9 | #define CLKSEL 0x04 /* clock source selection */ |
| 10 | #define CLKDIV1 0x08 /* clock divider 1 */ |
| 11 | #define CLKDIV2 0x2C /* clock divider 2 */ |
| 12 | #define CLKDIV3 0x58 /* clock divider 3 */ |
| 13 | #define PLLCON0 0x0C /* pll0 control */ |
| 14 | #define PLLCON1 0x10 /* pll1 control */ |
| 15 | #define PLLCON2 0x54 /* pll2 control */ |
| 16 | |
| 17 | /* CLKSEL bit filed */ |
| 18 | #define NPCM7XX_CPUCKSEL GENMASK(1, 0) |
| 19 | #define NPCM8XX_CPUCKSEL GENMASK(2, 0) |
| 20 | #define SDCKSEL GENMASK(7, 6) |
| 21 | #define UARTCKSEL GENMASK(9, 8) |
| 22 | #define TIMCKSEL GENMASK(15, 14) |
| 23 | |
| 24 | /* CLKDIV1 bit filed */ |
| 25 | #define SPI3CKDIV GENMASK(10, 6) |
| 26 | #define MMCCKDIV GENMASK(15, 11) |
| 27 | #define UARTDIV1 GENMASK(20, 16) |
| 28 | #define TIMCKDIV GENMASK(25, 21) |
| 29 | #define CLK4DIV GENMASK(27, 26) |
| 30 | |
| 31 | /* CLKDIV2 bit filed */ |
| 32 | #define APB5CKDIV GENMASK(23, 22) |
| 33 | #define APB2CKDIV GENMASK(27, 26) |
| 34 | |
| 35 | /* CLKDIV3 bit filed */ |
| 36 | #define SPIXCKDIV GENMASK(5, 1) |
| 37 | #define SPI0CKDIV GENMASK(10, 6) |
| 38 | #define UARTDIV2 GENMASK(15, 11) |
| 39 | #define SPI1CKDIV GENMASK(23, 16) |
| 40 | |
| 41 | /* PLLCON bit filed */ |
| 42 | #define PLLCON_INDV GENMASK(5, 0) |
| 43 | #define PLLCON_OTDV1 GENMASK(10, 8) |
| 44 | #define PLLCON_OTDV2 GENMASK(15, 13) |
| 45 | #define PLLCON_FBDV GENMASK(27, 16) |
| 46 | |
| 47 | /* Flags */ |
| 48 | #define DIV_TYPE1 BIT(0) /* div = clkdiv + 1 */ |
| 49 | #define DIV_TYPE2 BIT(1) /* div = 1 << clkdiv */ |
| 50 | #define PRE_DIV2 BIT(2) /* Pre divisor = 2 */ |
| 51 | #define POST_DIV2 BIT(3) /* Post divisor = 2 */ |
| 52 | #define FIXED_PARENT BIT(4) /* clock source is fixed */ |
Jim Liu | f071d55 | 2023-11-14 17:00:04 +0800 | [diff] [blame^] | 53 | #define DIV_RO BIT(5) /* divider is read-only */ |
Jim Liu | 2568856 | 2022-04-19 13:32:20 +0800 | [diff] [blame] | 54 | |
| 55 | /* Parameters of PLL configuration */ |
| 56 | struct npcm_clk_pll { |
| 57 | const int id; |
| 58 | const int parent_id; |
| 59 | u32 reg; |
| 60 | u32 flags; |
| 61 | }; |
| 62 | |
| 63 | /* Parent clock id to clksel mapping */ |
| 64 | struct parent_data { |
| 65 | int id; |
| 66 | int clksel; |
| 67 | }; |
| 68 | |
| 69 | /* Parameters of parent selection */ |
| 70 | struct npcm_clk_select { |
| 71 | const int id; |
| 72 | const struct parent_data *parents; |
| 73 | u32 reg; |
| 74 | u32 mask; |
| 75 | u8 num_parents; |
| 76 | u32 flags; |
| 77 | }; |
| 78 | |
| 79 | /* Parameters of clock divider */ |
| 80 | struct npcm_clk_div { |
| 81 | const int id; |
| 82 | u32 reg; |
| 83 | u32 mask; |
| 84 | u32 flags; |
| 85 | }; |
| 86 | |
| 87 | struct npcm_clk_data { |
| 88 | struct npcm_clk_pll *clk_plls; |
| 89 | int num_plls; |
| 90 | struct npcm_clk_select *clk_selectors; |
| 91 | int num_selectors; |
| 92 | struct npcm_clk_div *clk_dividers; |
| 93 | int num_dividers; |
| 94 | int refclk_id; |
| 95 | int pll0_id; |
| 96 | }; |
| 97 | |
| 98 | struct npcm_clk_priv { |
| 99 | void __iomem *base; |
| 100 | struct npcm_clk_data *clk_data; |
| 101 | int num_clks; |
| 102 | }; |
| 103 | |
| 104 | extern const struct clk_ops npcm_clk_ops; |
| 105 | |
| 106 | #endif |