| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017, Intel Corporation |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __CONFIG_TERASIC_DE10_H__ |
| 6 | #define __CONFIG_TERASIC_DE10_H__ |
| 7 | |
| 8 | #include <asm/arch/base_addr_ac5.h> |
| 9 | |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 10 | /* Memory configurations */ |
| 11 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ |
| 12 | |
| Dalon Westergreen | 7a0fe0d | 2017-04-18 08:11:16 -0700 | [diff] [blame] | 13 | /* The rest of the configuration is shared */ |
| 14 | #include <configs/socfpga_common.h> |
| 15 | |
| 16 | #endif /* __CONFIG_TERASIC_DE10_H__ */ |