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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenke65527f2004-02-12 00:47:09 +00002/*
3 * Configuation settings for the Motorola MC5272C3 board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenke65527f2004-02-12 00:47:09 +00006 */
wdenkabf7a7c2003-12-08 01:34:36 +00007
wdenke65527f2004-02-12 00:47:09 +00008/*
9 * board/config.h - configuration options, board specific
10 */
wdenkabf7a7c2003-12-08 01:34:36 +000011
wdenke65527f2004-02-12 00:47:09 +000012#ifndef _M5272C3_H
13#define _M5272C3_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
wdenkabf7a7c2003-12-08 01:34:36 +000019
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020020#define CONFIG_SYS_UART_PORT (0)
wdenke65527f2004-02-12 00:47:09 +000021
wdenke65527f2004-02-12 00:47:09 +000022#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
23
TsiChungLiew1692b482007-08-15 20:32:06 -050024#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenke65527f2004-02-12 00:47:09 +000025
26/* Configuration for environment
27 * Environment is embedded in u-boot in the second sector of the flash
28 */
wdenke65527f2004-02-12 00:47:09 +000029
angelo@sysam.it6312a952015-03-29 22:54:16 +020030#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060031 . = DEFINED(env_offset) ? env_offset : .; \
32 env/embedded.o(.text);
angelo@sysam.it6312a952015-03-29 22:54:16 +020033
TsiChungLiew1692b482007-08-15 20:32:06 -050034#ifdef CONFIG_MCFFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035# define CONFIG_SYS_DISCOVER_PHY
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
37# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew1692b482007-08-15 20:32:06 -050038# define FECDUPLEX FULL
39# define FECSPEED _100BASET
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew1692b482007-08-15 20:32:06 -050041#endif
42
43#ifdef CONFIG_MCFFEC
TsiChungLiew1692b482007-08-15 20:32:06 -050044# define CONFIG_IPADDR 192.162.1.2
45# define CONFIG_NETMASK 255.255.255.0
46# define CONFIG_SERVERIP 192.162.1.1
47# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew1692b482007-08-15 20:32:06 -050048#endif /* CONFIG_MCFFEC */
49
Mario Six790d8442018-03-28 14:38:20 +020050#define CONFIG_HOSTNAME "M5272C3"
TsiChungLiew1692b482007-08-15 20:32:06 -050051#define CONFIG_EXTRA_ENV_SETTINGS \
52 "netdev=eth0\0" \
53 "loadaddr=10000\0" \
54 "u-boot=u-boot.bin\0" \
55 "load=tftp ${loadaddr) ${u-boot}\0" \
56 "upd=run load; run prog\0" \
57 "prog=prot off ffe00000 ffe3ffff;" \
58 "era ffe00000 ffe3ffff;" \
59 "cp.b ${loadaddr} ffe00000 ${filesize};"\
60 "save\0" \
61 ""
wdenke65527f2004-02-12 00:47:09 +000062
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#define CONFIG_SYS_CLK 66000000
wdenke65527f2004-02-12 00:47:09 +000064
65/*
66 * Low Level Configuration Settings
67 * (address mappings, register initial values, etc.)
68 * You should know what you are doing if you make changes here.
69 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
71#define CONFIG_SYS_SCR 0x0003
72#define CONFIG_SYS_SPR 0xffff
wdenke65527f2004-02-12 00:47:09 +000073
wdenke65527f2004-02-12 00:47:09 +000074/*-----------------------------------------------------------------------
75 * Definitions for initial stack pointer and data area (in DPRAM)
76 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020078#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +020079#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke65527f2004-02-12 00:47:09 +000081
82/*-----------------------------------------------------------------------
83 * Start addresses for the final memory configuration
84 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke65527f2004-02-12 00:47:09 +000086 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_SDRAM_BASE 0x00000000
88#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
89#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenke65527f2004-02-12 00:47:09 +000090
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_MONITOR_LEN 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenke65527f2004-02-12 00:47:09 +000093
94/*
95 * For booting Linux, the board info and command line data
96 * have to be in the first 8 MB of memory, since this is
97 * the maximum mapped by the Linux kernel during initialization ??
98 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenke65527f2004-02-12 00:47:09 +0000100
TsiChung Liew12b340a2008-10-21 14:19:26 +0000101/*
wdenke65527f2004-02-12 00:47:09 +0000102 * FLASH organization
103 */
TsiChung Liew12b340a2008-10-21 14:19:26 +0000104#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew12b340a2008-10-21 14:19:26 +0000105# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
106# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChung Liew12b340a2008-10-21 14:19:26 +0000107# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
TsiChung Liew12b340a2008-10-21 14:19:26 +0000108#endif
wdenke65527f2004-02-12 00:47:09 +0000109
110/*-----------------------------------------------------------------------
111 * Cache Configuration
112 */
wdenke65527f2004-02-12 00:47:09 +0000113
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600114#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200115 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600116#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200117 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600118#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
119#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
120 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
121 CF_ACR_EN | CF_ACR_SM_ALL)
122#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
123 CF_CACR_DISD | CF_CACR_INVI | \
124 CF_CACR_CEIB | CF_CACR_DCM | \
125 CF_CACR_EUSP)
126
wdenke65527f2004-02-12 00:47:09 +0000127/*-----------------------------------------------------------------------
wdenke65527f2004-02-12 00:47:09 +0000128 * Port configuration
129 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_PACNT 0x00000000
131#define CONFIG_SYS_PADDR 0x0000
132#define CONFIG_SYS_PADAT 0x0000
133#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
134#define CONFIG_SYS_PBDDR 0x0000
135#define CONFIG_SYS_PBDAT 0x0000
136#define CONFIG_SYS_PDCNT 0x00000000
TsiChungLiew1692b482007-08-15 20:32:06 -0500137#endif /* _M5272C3_H */