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git01.mediatek.com / filogic / uboot / f04969b3b336af3eece0dd175f90abc364fbcf24 / . / arch / mips / mach-octeon / include / mach / cvmx-smix-defs.h
blob: c51d71b38fee854c0e9fe6286310ebe943c59725 [file] [log] [blame]
Aaron Williams78f51882020-12-11 17:05:51 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon smix.
7 */
8
9#ifndef __CVMX_SMIX_DEFS_H__
10#define __CVMX_SMIX_DEFS_H__
11
12static inline u64 CVMX_SMIX_CLK(unsigned long offset)
13{
14 switch (cvmx_get_octeon_family()) {
15 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
16 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
17 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
18 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
19 return 0x0001180000001818ull + (offset) * 256;
20 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
21 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
22 return 0x0001180000003818ull + (offset) * 128;
23 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
24 return 0x0001180000003818ull + (offset) * 128;
25 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
26 return 0x0001180000003818ull + (offset) * 128;
27 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
28 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
29 return 0x0001180000003818ull + (offset) * 128;
30 }
31 return 0x0001180000003818ull + (offset) * 128;
32}
33
34static inline u64 CVMX_SMIX_CMD(unsigned long offset)
35{
36 switch (cvmx_get_octeon_family()) {
37 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
38 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
39 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
40 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
42 return 0x0001180000001800ull + (offset) * 256;
43 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
44 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
45 return 0x0001180000003800ull + (offset) * 128;
46 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
47 return 0x0001180000003800ull + (offset) * 128;
48 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
49 return 0x0001180000003800ull + (offset) * 128;
50 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
51 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
52 return 0x0001180000003800ull + (offset) * 128;
53 }
54 return 0x0001180000003800ull + (offset) * 128;
55}
56
57static inline u64 CVMX_SMIX_EN(unsigned long offset)
58{
59 switch (cvmx_get_octeon_family()) {
60 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
61 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
62 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
63 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
65 return 0x0001180000001820ull + (offset) * 256;
66 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
67 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
68 return 0x0001180000003820ull + (offset) * 128;
69 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
70 return 0x0001180000003820ull + (offset) * 128;
71 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
72 return 0x0001180000003820ull + (offset) * 128;
73 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
74 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
75 return 0x0001180000003820ull + (offset) * 128;
76 }
77 return 0x0001180000003820ull + (offset) * 128;
78}
79
80static inline u64 CVMX_SMIX_RD_DAT(unsigned long offset)
81{
82 switch (cvmx_get_octeon_family()) {
83 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
84 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
85 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
86 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
88 return 0x0001180000001810ull + (offset) * 256;
89 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
90 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
91 return 0x0001180000003810ull + (offset) * 128;
92 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
93 return 0x0001180000003810ull + (offset) * 128;
94 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
95 return 0x0001180000003810ull + (offset) * 128;
96 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
97 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
98 return 0x0001180000003810ull + (offset) * 128;
99 }
100 return 0x0001180000003810ull + (offset) * 128;
101}
102
103static inline u64 CVMX_SMIX_WR_DAT(unsigned long offset)
104{
105 switch (cvmx_get_octeon_family()) {
106 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
107 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
108 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
109 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
110 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
111 return 0x0001180000001808ull + (offset) * 256;
112 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
113 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
114 return 0x0001180000003808ull + (offset) * 128;
115 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
116 return 0x0001180000003808ull + (offset) * 128;
117 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
118 return 0x0001180000003808ull + (offset) * 128;
119 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
120 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
121 return 0x0001180000003808ull + (offset) * 128;
122 }
123 return 0x0001180000003808ull + (offset) * 128;
124}
125
126/**
127 * cvmx_smi#_clk
128 *
129 * This register determines the SMI timing characteristics.
130 * If software wants to change SMI CLK timing parameters ([SAMPLE]/[SAMPLE_HI]), software
131 * must delay the SMI_()_CLK CSR write by at least 512 coprocessor-clock cycles after the
132 * previous SMI operation is finished.
133 */
134union cvmx_smix_clk {
135 u64 u64;
136 struct cvmx_smix_clk_s {
137 u64 reserved_25_63 : 39;
138 u64 mode : 1;
139 u64 reserved_21_23 : 3;
140 u64 sample_hi : 5;
141 u64 sample_mode : 1;
142 u64 reserved_14_14 : 1;
143 u64 clk_idle : 1;
144 u64 preamble : 1;
145 u64 sample : 4;
146 u64 phase : 8;
147 } s;
148 struct cvmx_smix_clk_cn30xx {
149 u64 reserved_21_63 : 43;
150 u64 sample_hi : 5;
151 u64 sample_mode : 1;
152 u64 reserved_14_14 : 1;
153 u64 clk_idle : 1;
154 u64 preamble : 1;
155 u64 sample : 4;
156 u64 phase : 8;
157 } cn30xx;
158 struct cvmx_smix_clk_cn30xx cn31xx;
159 struct cvmx_smix_clk_cn30xx cn38xx;
160 struct cvmx_smix_clk_cn30xx cn38xxp2;
161 struct cvmx_smix_clk_s cn50xx;
162 struct cvmx_smix_clk_s cn52xx;
163 struct cvmx_smix_clk_s cn52xxp1;
164 struct cvmx_smix_clk_s cn56xx;
165 struct cvmx_smix_clk_s cn56xxp1;
166 struct cvmx_smix_clk_cn30xx cn58xx;
167 struct cvmx_smix_clk_cn30xx cn58xxp1;
168 struct cvmx_smix_clk_s cn61xx;
169 struct cvmx_smix_clk_s cn63xx;
170 struct cvmx_smix_clk_s cn63xxp1;
171 struct cvmx_smix_clk_s cn66xx;
172 struct cvmx_smix_clk_s cn68xx;
173 struct cvmx_smix_clk_s cn68xxp1;
174 struct cvmx_smix_clk_s cn70xx;
175 struct cvmx_smix_clk_s cn70xxp1;
176 struct cvmx_smix_clk_s cn73xx;
177 struct cvmx_smix_clk_s cn78xx;
178 struct cvmx_smix_clk_s cn78xxp1;
179 struct cvmx_smix_clk_s cnf71xx;
180 struct cvmx_smix_clk_s cnf75xx;
181};
182
183typedef union cvmx_smix_clk cvmx_smix_clk_t;
184
185/**
186 * cvmx_smi#_cmd
187 *
188 * This register forces a read or write command to the PHY. Write operations to this register
189 * create SMI transactions. Software will poll (depending on the transaction type).
190 */
191union cvmx_smix_cmd {
192 u64 u64;
193 struct cvmx_smix_cmd_s {
194 u64 reserved_18_63 : 46;
195 u64 phy_op : 2;
196 u64 reserved_13_15 : 3;
197 u64 phy_adr : 5;
198 u64 reserved_5_7 : 3;
199 u64 reg_adr : 5;
200 } s;
201 struct cvmx_smix_cmd_cn30xx {
202 u64 reserved_17_63 : 47;
203 u64 phy_op : 1;
204 u64 reserved_13_15 : 3;
205 u64 phy_adr : 5;
206 u64 reserved_5_7 : 3;
207 u64 reg_adr : 5;
208 } cn30xx;
209 struct cvmx_smix_cmd_cn30xx cn31xx;
210 struct cvmx_smix_cmd_cn30xx cn38xx;
211 struct cvmx_smix_cmd_cn30xx cn38xxp2;
212 struct cvmx_smix_cmd_s cn50xx;
213 struct cvmx_smix_cmd_s cn52xx;
214 struct cvmx_smix_cmd_s cn52xxp1;
215 struct cvmx_smix_cmd_s cn56xx;
216 struct cvmx_smix_cmd_s cn56xxp1;
217 struct cvmx_smix_cmd_cn30xx cn58xx;
218 struct cvmx_smix_cmd_cn30xx cn58xxp1;
219 struct cvmx_smix_cmd_s cn61xx;
220 struct cvmx_smix_cmd_s cn63xx;
221 struct cvmx_smix_cmd_s cn63xxp1;
222 struct cvmx_smix_cmd_s cn66xx;
223 struct cvmx_smix_cmd_s cn68xx;
224 struct cvmx_smix_cmd_s cn68xxp1;
225 struct cvmx_smix_cmd_s cn70xx;
226 struct cvmx_smix_cmd_s cn70xxp1;
227 struct cvmx_smix_cmd_s cn73xx;
228 struct cvmx_smix_cmd_s cn78xx;
229 struct cvmx_smix_cmd_s cn78xxp1;
230 struct cvmx_smix_cmd_s cnf71xx;
231 struct cvmx_smix_cmd_s cnf75xx;
232};
233
234typedef union cvmx_smix_cmd cvmx_smix_cmd_t;
235
236/**
237 * cvmx_smi#_en
238 *
239 * Enables the SMI interface.
240 *
241 */
242union cvmx_smix_en {
243 u64 u64;
244 struct cvmx_smix_en_s {
245 u64 reserved_1_63 : 63;
246 u64 en : 1;
247 } s;
248 struct cvmx_smix_en_s cn30xx;
249 struct cvmx_smix_en_s cn31xx;
250 struct cvmx_smix_en_s cn38xx;
251 struct cvmx_smix_en_s cn38xxp2;
252 struct cvmx_smix_en_s cn50xx;
253 struct cvmx_smix_en_s cn52xx;
254 struct cvmx_smix_en_s cn52xxp1;
255 struct cvmx_smix_en_s cn56xx;
256 struct cvmx_smix_en_s cn56xxp1;
257 struct cvmx_smix_en_s cn58xx;
258 struct cvmx_smix_en_s cn58xxp1;
259 struct cvmx_smix_en_s cn61xx;
260 struct cvmx_smix_en_s cn63xx;
261 struct cvmx_smix_en_s cn63xxp1;
262 struct cvmx_smix_en_s cn66xx;
263 struct cvmx_smix_en_s cn68xx;
264 struct cvmx_smix_en_s cn68xxp1;
265 struct cvmx_smix_en_s cn70xx;
266 struct cvmx_smix_en_s cn70xxp1;
267 struct cvmx_smix_en_s cn73xx;
268 struct cvmx_smix_en_s cn78xx;
269 struct cvmx_smix_en_s cn78xxp1;
270 struct cvmx_smix_en_s cnf71xx;
271 struct cvmx_smix_en_s cnf75xx;
272};
273
274typedef union cvmx_smix_en cvmx_smix_en_t;
275
276/**
277 * cvmx_smi#_rd_dat
278 *
279 * This register contains the data in a read operation.
280 *
281 */
282union cvmx_smix_rd_dat {
283 u64 u64;
284 struct cvmx_smix_rd_dat_s {
285 u64 reserved_18_63 : 46;
286 u64 pending : 1;
287 u64 val : 1;
288 u64 dat : 16;
289 } s;
290 struct cvmx_smix_rd_dat_s cn30xx;
291 struct cvmx_smix_rd_dat_s cn31xx;
292 struct cvmx_smix_rd_dat_s cn38xx;
293 struct cvmx_smix_rd_dat_s cn38xxp2;
294 struct cvmx_smix_rd_dat_s cn50xx;
295 struct cvmx_smix_rd_dat_s cn52xx;
296 struct cvmx_smix_rd_dat_s cn52xxp1;
297 struct cvmx_smix_rd_dat_s cn56xx;
298 struct cvmx_smix_rd_dat_s cn56xxp1;
299 struct cvmx_smix_rd_dat_s cn58xx;
300 struct cvmx_smix_rd_dat_s cn58xxp1;
301 struct cvmx_smix_rd_dat_s cn61xx;
302 struct cvmx_smix_rd_dat_s cn63xx;
303 struct cvmx_smix_rd_dat_s cn63xxp1;
304 struct cvmx_smix_rd_dat_s cn66xx;
305 struct cvmx_smix_rd_dat_s cn68xx;
306 struct cvmx_smix_rd_dat_s cn68xxp1;
307 struct cvmx_smix_rd_dat_s cn70xx;
308 struct cvmx_smix_rd_dat_s cn70xxp1;
309 struct cvmx_smix_rd_dat_s cn73xx;
310 struct cvmx_smix_rd_dat_s cn78xx;
311 struct cvmx_smix_rd_dat_s cn78xxp1;
312 struct cvmx_smix_rd_dat_s cnf71xx;
313 struct cvmx_smix_rd_dat_s cnf75xx;
314};
315
316typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;
317
318/**
319 * cvmx_smi#_wr_dat
320 *
321 * This register provides the data for a write operation.
322 *
323 */
324union cvmx_smix_wr_dat {
325 u64 u64;
326 struct cvmx_smix_wr_dat_s {
327 u64 reserved_18_63 : 46;
328 u64 pending : 1;
329 u64 val : 1;
330 u64 dat : 16;
331 } s;
332 struct cvmx_smix_wr_dat_s cn30xx;
333 struct cvmx_smix_wr_dat_s cn31xx;
334 struct cvmx_smix_wr_dat_s cn38xx;
335 struct cvmx_smix_wr_dat_s cn38xxp2;
336 struct cvmx_smix_wr_dat_s cn50xx;
337 struct cvmx_smix_wr_dat_s cn52xx;
338 struct cvmx_smix_wr_dat_s cn52xxp1;
339 struct cvmx_smix_wr_dat_s cn56xx;
340 struct cvmx_smix_wr_dat_s cn56xxp1;
341 struct cvmx_smix_wr_dat_s cn58xx;
342 struct cvmx_smix_wr_dat_s cn58xxp1;
343 struct cvmx_smix_wr_dat_s cn61xx;
344 struct cvmx_smix_wr_dat_s cn63xx;
345 struct cvmx_smix_wr_dat_s cn63xxp1;
346 struct cvmx_smix_wr_dat_s cn66xx;
347 struct cvmx_smix_wr_dat_s cn68xx;
348 struct cvmx_smix_wr_dat_s cn68xxp1;
349 struct cvmx_smix_wr_dat_s cn70xx;
350 struct cvmx_smix_wr_dat_s cn70xxp1;
351 struct cvmx_smix_wr_dat_s cn73xx;
352 struct cvmx_smix_wr_dat_s cn78xx;
353 struct cvmx_smix_wr_dat_s cn78xxp1;
354 struct cvmx_smix_wr_dat_s cnf71xx;
355 struct cvmx_smix_wr_dat_s cnf75xx;
356};
357
358typedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t;
359
360#endif