Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / f04969b3b336af3eece0dd175f90abc364fbcf24 / . / arch / mips / mach-octeon / include / mach / cvmx-dtx-defs.h
blob: afb581a5ea155ace6adc8607d78ea22dd7f92631 [file] [log] [blame]
Aaron Williamsb93d51b2020-12-11 17:05:31 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon dtx.
7 */
8
9#ifndef __CVMX_DTX_DEFS_H__
10#define __CVMX_DTX_DEFS_H__
11
12#define CVMX_DTX_AGL_BCST_RSP (0x00011800FE700080ull)
13#define CVMX_DTX_AGL_CTL (0x00011800FE700060ull)
14#define CVMX_DTX_AGL_DATX(offset) (0x00011800FE700040ull + ((offset) & 1) * 8)
15#define CVMX_DTX_AGL_ENAX(offset) (0x00011800FE700020ull + ((offset) & 1) * 8)
16#define CVMX_DTX_AGL_SELX(offset) (0x00011800FE700000ull + ((offset) & 1) * 8)
17#define CVMX_DTX_ASE_BCST_RSP (0x00011800FE6E8080ull)
18#define CVMX_DTX_ASE_CTL (0x00011800FE6E8060ull)
19#define CVMX_DTX_ASE_DATX(offset) (0x00011800FE6E8040ull + ((offset) & 1) * 8)
20#define CVMX_DTX_ASE_ENAX(offset) (0x00011800FE6E8020ull + ((offset) & 1) * 8)
21#define CVMX_DTX_ASE_SELX(offset) (0x00011800FE6E8000ull + ((offset) & 1) * 8)
22#define CVMX_DTX_BBX1I_BCST_RSP (0x00011800FED78080ull)
23#define CVMX_DTX_BBX1I_CTL (0x00011800FED78060ull)
24#define CVMX_DTX_BBX1I_DATX(offset) (0x00011800FED78040ull + ((offset) & 1) * 8)
25#define CVMX_DTX_BBX1I_ENAX(offset) (0x00011800FED78020ull + ((offset) & 1) * 8)
26#define CVMX_DTX_BBX1I_SELX(offset) (0x00011800FED78000ull + ((offset) & 1) * 8)
27#define CVMX_DTX_BBX2I_BCST_RSP (0x00011800FED80080ull)
28#define CVMX_DTX_BBX2I_CTL (0x00011800FED80060ull)
29#define CVMX_DTX_BBX2I_DATX(offset) (0x00011800FED80040ull + ((offset) & 1) * 8)
30#define CVMX_DTX_BBX2I_ENAX(offset) (0x00011800FED80020ull + ((offset) & 1) * 8)
31#define CVMX_DTX_BBX2I_SELX(offset) (0x00011800FED80000ull + ((offset) & 1) * 8)
32#define CVMX_DTX_BBX3I_BCST_RSP (0x00011800FED88080ull)
33#define CVMX_DTX_BBX3I_CTL (0x00011800FED88060ull)
34#define CVMX_DTX_BBX3I_DATX(offset) (0x00011800FED88040ull + ((offset) & 1) * 8)
35#define CVMX_DTX_BBX3I_ENAX(offset) (0x00011800FED88020ull + ((offset) & 1) * 8)
36#define CVMX_DTX_BBX3I_SELX(offset) (0x00011800FED88000ull + ((offset) & 1) * 8)
37#define CVMX_DTX_BCH_BCST_RSP (0x00011800FE388080ull)
38#define CVMX_DTX_BCH_CTL (0x00011800FE388060ull)
39#define CVMX_DTX_BCH_DATX(offset) (0x00011800FE388040ull + ((offset) & 1) * 8)
40#define CVMX_DTX_BCH_ENAX(offset) (0x00011800FE388020ull + ((offset) & 1) * 8)
41#define CVMX_DTX_BCH_SELX(offset) (0x00011800FE388000ull + ((offset) & 1) * 8)
42#define CVMX_DTX_BGXX_BCST_RSP(offset) (0x00011800FE700080ull + ((offset) & 7) * 32768)
43#define CVMX_DTX_BGXX_CTL(offset) (0x00011800FE700060ull + ((offset) & 7) * 32768)
44#define CVMX_DTX_BGXX_DATX(offset, block_id) \
45 (0x00011800FE700040ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
46#define CVMX_DTX_BGXX_ENAX(offset, block_id) \
47 (0x00011800FE700020ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
48#define CVMX_DTX_BGXX_SELX(offset, block_id) \
49 (0x00011800FE700000ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
50#define CVMX_DTX_BROADCAST_CTL (0x00011800FE7F0060ull)
51#define CVMX_DTX_BROADCAST_ENAX(offset) (0x00011800FE7F0020ull + ((offset) & 1) * 8)
52#define CVMX_DTX_BROADCAST_SELX(offset) (0x00011800FE7F0000ull + ((offset) & 1) * 8)
53#define CVMX_DTX_BTS_BCST_RSP (0x00011800FE5B0080ull)
54#define CVMX_DTX_BTS_CTL (0x00011800FE5B0060ull)
55#define CVMX_DTX_BTS_DATX(offset) (0x00011800FE5B0040ull + ((offset) & 1) * 8)
56#define CVMX_DTX_BTS_ENAX(offset) (0x00011800FE5B0020ull + ((offset) & 1) * 8)
57#define CVMX_DTX_BTS_SELX(offset) (0x00011800FE5B0000ull + ((offset) & 1) * 8)
58#define CVMX_DTX_CIU_BCST_RSP (0x00011800FE808080ull)
59#define CVMX_DTX_CIU_CTL (0x00011800FE808060ull)
60#define CVMX_DTX_CIU_DATX(offset) (0x00011800FE808040ull + ((offset) & 1) * 8)
61#define CVMX_DTX_CIU_ENAX(offset) (0x00011800FE808020ull + ((offset) & 1) * 8)
62#define CVMX_DTX_CIU_SELX(offset) (0x00011800FE808000ull + ((offset) & 1) * 8)
63#define CVMX_DTX_DENC_BCST_RSP (0x00011800FED48080ull)
64#define CVMX_DTX_DENC_CTL (0x00011800FED48060ull)
65#define CVMX_DTX_DENC_DATX(offset) (0x00011800FED48040ull + ((offset) & 1) * 8)
66#define CVMX_DTX_DENC_ENAX(offset) (0x00011800FED48020ull + ((offset) & 1) * 8)
67#define CVMX_DTX_DENC_SELX(offset) (0x00011800FED48000ull + ((offset) & 1) * 8)
68#define CVMX_DTX_DFA_BCST_RSP (0x00011800FE1B8080ull)
69#define CVMX_DTX_DFA_CTL (0x00011800FE1B8060ull)
70#define CVMX_DTX_DFA_DATX(offset) (0x00011800FE1B8040ull + ((offset) & 1) * 8)
71#define CVMX_DTX_DFA_ENAX(offset) (0x00011800FE1B8020ull + ((offset) & 1) * 8)
72#define CVMX_DTX_DFA_SELX(offset) (0x00011800FE1B8000ull + ((offset) & 1) * 8)
73#define CVMX_DTX_DLFE_BCST_RSP (0x00011800FED18080ull)
74#define CVMX_DTX_DLFE_CTL (0x00011800FED18060ull)
75#define CVMX_DTX_DLFE_DATX(offset) (0x00011800FED18040ull + ((offset) & 1) * 8)
76#define CVMX_DTX_DLFE_ENAX(offset) (0x00011800FED18020ull + ((offset) & 1) * 8)
77#define CVMX_DTX_DLFE_SELX(offset) (0x00011800FED18000ull + ((offset) & 1) * 8)
78#define CVMX_DTX_DPI_BCST_RSP (0x00011800FEEF8080ull)
79#define CVMX_DTX_DPI_CTL (0x00011800FEEF8060ull)
80#define CVMX_DTX_DPI_DATX(offset) (0x00011800FEEF8040ull + ((offset) & 1) * 8)
81#define CVMX_DTX_DPI_ENAX(offset) (0x00011800FEEF8020ull + ((offset) & 1) * 8)
82#define CVMX_DTX_DPI_SELX(offset) (0x00011800FEEF8000ull + ((offset) & 1) * 8)
83#define CVMX_DTX_FDEQX_BCST_RSP(offset) (0x00011800FED30080ull + ((offset) & 1) * 0x20000ull)
84#define CVMX_DTX_FDEQX_CTL(offset) (0x00011800FED30060ull + ((offset) & 1) * 0x20000ull)
85#define CVMX_DTX_FDEQX_DATX(offset, block_id) \
86 (0x00011800FED30040ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)
87#define CVMX_DTX_FDEQX_ENAX(offset, block_id) \
88 (0x00011800FED30020ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)
89#define CVMX_DTX_FDEQX_SELX(offset, block_id) \
90 (0x00011800FED30000ull + (((offset) & 1) + ((block_id) & 1) * 0x4000ull) * 8)
91#define CVMX_DTX_FPA_BCST_RSP CVMX_DTX_FPA_BCST_RSP_FUNC()
92static inline u64 CVMX_DTX_FPA_BCST_RSP_FUNC(void)
93{
94 switch (cvmx_get_octeon_family()) {
95 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
96 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
97 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
98 return 0x00011800FE940080ull;
99 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
100 return 0x00011800FE940080ull;
101 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
102 return 0x00011800FE940080ull;
103 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
104 return 0x00011800FE140080ull;
105 }
106 return 0x00011800FE940080ull;
107}
108
109#define CVMX_DTX_FPA_CTL CVMX_DTX_FPA_CTL_FUNC()
110static inline u64 CVMX_DTX_FPA_CTL_FUNC(void)
111{
112 switch (cvmx_get_octeon_family()) {
113 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
114 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
115 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
116 return 0x00011800FE940060ull;
117 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
118 return 0x00011800FE940060ull;
119 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
120 return 0x00011800FE940060ull;
121 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
122 return 0x00011800FE140060ull;
123 }
124 return 0x00011800FE940060ull;
125}
126
127static inline u64 CVMX_DTX_FPA_DATX(unsigned long offset)
128{
129 switch (cvmx_get_octeon_family()) {
130 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
132 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
133 return 0x00011800FE940040ull + (offset) * 8;
134 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
135 return 0x00011800FE940040ull + (offset) * 8;
136 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
137 return 0x00011800FE940040ull + (offset) * 8;
138 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
139 return 0x00011800FE140040ull + (offset) * 8;
140 }
141 return 0x00011800FE940040ull + (offset) * 8;
142}
143
144static inline u64 CVMX_DTX_FPA_ENAX(unsigned long offset)
145{
146 switch (cvmx_get_octeon_family()) {
147 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
149 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
150 return 0x00011800FE940020ull + (offset) * 8;
151 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
152 return 0x00011800FE940020ull + (offset) * 8;
153 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
154 return 0x00011800FE940020ull + (offset) * 8;
155 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
156 return 0x00011800FE140020ull + (offset) * 8;
157 }
158 return 0x00011800FE940020ull + (offset) * 8;
159}
160
161static inline u64 CVMX_DTX_FPA_SELX(unsigned long offset)
162{
163 switch (cvmx_get_octeon_family()) {
164 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
165 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
166 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
167 return 0x00011800FE940000ull + (offset) * 8;
168 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
169 return 0x00011800FE940000ull + (offset) * 8;
170 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
171 return 0x00011800FE940000ull + (offset) * 8;
172 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
173 return 0x00011800FE140000ull + (offset) * 8;
174 }
175 return 0x00011800FE940000ull + (offset) * 8;
176}
177
178#define CVMX_DTX_GMXX_BCST_RSP(offset) (0x00011800FE040080ull + ((offset) & 1) * 0x40000ull)
179#define CVMX_DTX_GMXX_CTL(offset) (0x00011800FE040060ull + ((offset) & 1) * 0x40000ull)
180#define CVMX_DTX_GMXX_DATX(offset, block_id) \
181 (0x00011800FE040040ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
182#define CVMX_DTX_GMXX_ENAX(offset, block_id) \
183 (0x00011800FE040020ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
184#define CVMX_DTX_GMXX_SELX(offset, block_id) \
185 (0x00011800FE040000ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
186#define CVMX_DTX_GSERX_BCST_RSP(offset) (0x00011800FE480080ull + ((offset) & 15) * 32768)
187#define CVMX_DTX_GSERX_CTL(offset) (0x00011800FE480060ull + ((offset) & 15) * 32768)
188#define CVMX_DTX_GSERX_DATX(offset, block_id) \
189 (0x00011800FE480040ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)
190#define CVMX_DTX_GSERX_ENAX(offset, block_id) \
191 (0x00011800FE480020ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)
192#define CVMX_DTX_GSERX_SELX(offset, block_id) \
193 (0x00011800FE480000ull + (((offset) & 1) + ((block_id) & 15) * 0x1000ull) * 8)
194#define CVMX_DTX_HNA_BCST_RSP (0x00011800FE238080ull)
195#define CVMX_DTX_HNA_CTL (0x00011800FE238060ull)
196#define CVMX_DTX_HNA_DATX(offset) (0x00011800FE238040ull + ((offset) & 1) * 8)
197#define CVMX_DTX_HNA_ENAX(offset) (0x00011800FE238020ull + ((offset) & 1) * 8)
198#define CVMX_DTX_HNA_SELX(offset) (0x00011800FE238000ull + ((offset) & 1) * 8)
199#define CVMX_DTX_ILA_BCST_RSP (0x00011800FE0B8080ull)
200#define CVMX_DTX_ILA_CTL (0x00011800FE0B8060ull)
201#define CVMX_DTX_ILA_DATX(offset) (0x00011800FE0B8040ull + ((offset) & 1) * 8)
202#define CVMX_DTX_ILA_ENAX(offset) (0x00011800FE0B8020ull + ((offset) & 1) * 8)
203#define CVMX_DTX_ILA_SELX(offset) (0x00011800FE0B8000ull + ((offset) & 1) * 8)
204#define CVMX_DTX_ILK_BCST_RSP (0x00011800FE0A0080ull)
205#define CVMX_DTX_ILK_CTL (0x00011800FE0A0060ull)
206#define CVMX_DTX_ILK_DATX(offset) (0x00011800FE0A0040ull + ((offset) & 1) * 8)
207#define CVMX_DTX_ILK_ENAX(offset) (0x00011800FE0A0020ull + ((offset) & 1) * 8)
208#define CVMX_DTX_ILK_SELX(offset) (0x00011800FE0A0000ull + ((offset) & 1) * 8)
209#define CVMX_DTX_IOBN_BCST_RSP (0x00011800FE780080ull)
210#define CVMX_DTX_IOBN_CTL (0x00011800FE780060ull)
211#define CVMX_DTX_IOBN_DATX(offset) (0x00011800FE780040ull + ((offset) & 1) * 8)
212#define CVMX_DTX_IOBN_ENAX(offset) (0x00011800FE780020ull + ((offset) & 1) * 8)
213#define CVMX_DTX_IOBN_SELX(offset) (0x00011800FE780000ull + ((offset) & 1) * 8)
214#define CVMX_DTX_IOBP_BCST_RSP (0x00011800FE7A0080ull)
215#define CVMX_DTX_IOBP_CTL (0x00011800FE7A0060ull)
216#define CVMX_DTX_IOBP_DATX(offset) (0x00011800FE7A0040ull + ((offset) & 1) * 8)
217#define CVMX_DTX_IOBP_ENAX(offset) (0x00011800FE7A0020ull + ((offset) & 1) * 8)
218#define CVMX_DTX_IOBP_SELX(offset) (0x00011800FE7A0000ull + ((offset) & 1) * 8)
219#define CVMX_DTX_IOB_BCST_RSP (0x00011800FE780080ull)
220#define CVMX_DTX_IOB_CTL (0x00011800FE780060ull)
221#define CVMX_DTX_IOB_DATX(offset) (0x00011800FE780040ull + ((offset) & 1) * 8)
222#define CVMX_DTX_IOB_ENAX(offset) (0x00011800FE780020ull + ((offset) & 1) * 8)
223#define CVMX_DTX_IOB_SELX(offset) (0x00011800FE780000ull + ((offset) & 1) * 8)
224#define CVMX_DTX_IPD_BCST_RSP (0x00011800FE278080ull)
225#define CVMX_DTX_IPD_CTL (0x00011800FE278060ull)
226#define CVMX_DTX_IPD_DATX(offset) (0x00011800FE278040ull + ((offset) & 1) * 8)
227#define CVMX_DTX_IPD_ENAX(offset) (0x00011800FE278020ull + ((offset) & 1) * 8)
228#define CVMX_DTX_IPD_SELX(offset) (0x00011800FE278000ull + ((offset) & 1) * 8)
229#define CVMX_DTX_KEY_BCST_RSP (0x00011800FE100080ull)
230#define CVMX_DTX_KEY_CTL (0x00011800FE100060ull)
231#define CVMX_DTX_KEY_DATX(offset) (0x00011800FE100040ull + ((offset) & 1) * 8)
232#define CVMX_DTX_KEY_ENAX(offset) (0x00011800FE100020ull + ((offset) & 1) * 8)
233#define CVMX_DTX_KEY_SELX(offset) (0x00011800FE100000ull + ((offset) & 1) * 8)
234#define CVMX_DTX_L2C_CBCX_BCST_RSP(offset) (0x00011800FE420080ull + ((offset) & 3) * 32768)
235#define CVMX_DTX_L2C_CBCX_CTL(offset) (0x00011800FE420060ull + ((offset) & 3) * 32768)
236#define CVMX_DTX_L2C_CBCX_DATX(offset, block_id) \
237 (0x00011800FE420040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
238#define CVMX_DTX_L2C_CBCX_ENAX(offset, block_id) \
239 (0x00011800FE420020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
240#define CVMX_DTX_L2C_CBCX_SELX(offset, block_id) \
241 (0x00011800FE420000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
242#define CVMX_DTX_L2C_MCIX_BCST_RSP(offset) (0x00011800FE2E0080ull + ((offset) & 3) * 32768)
243#define CVMX_DTX_L2C_MCIX_CTL(offset) (0x00011800FE2E0060ull + ((offset) & 3) * 32768)
244#define CVMX_DTX_L2C_MCIX_DATX(offset, block_id) \
245 (0x00011800FE2E0040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
246#define CVMX_DTX_L2C_MCIX_ENAX(offset, block_id) \
247 (0x00011800FE2E0020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
248#define CVMX_DTX_L2C_MCIX_SELX(offset, block_id) \
249 (0x00011800FE2E0000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
250#define CVMX_DTX_L2C_TADX_BCST_RSP(offset) (0x00011800FE240080ull + ((offset) & 7) * 32768)
251#define CVMX_DTX_L2C_TADX_CTL(offset) (0x00011800FE240060ull + ((offset) & 7) * 32768)
252#define CVMX_DTX_L2C_TADX_DATX(offset, block_id) \
253 (0x00011800FE240040ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
254#define CVMX_DTX_L2C_TADX_ENAX(offset, block_id) \
255 (0x00011800FE240020ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
256#define CVMX_DTX_L2C_TADX_SELX(offset, block_id) \
257 (0x00011800FE240000ull + (((offset) & 1) + ((block_id) & 7) * 0x1000ull) * 8)
258#define CVMX_DTX_LAPX_BCST_RSP(offset) (0x00011800FE060080ull + ((offset) & 1) * 32768)
259#define CVMX_DTX_LAPX_CTL(offset) (0x00011800FE060060ull + ((offset) & 1) * 32768)
260#define CVMX_DTX_LAPX_DATX(offset, block_id) \
261 (0x00011800FE060040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
262#define CVMX_DTX_LAPX_ENAX(offset, block_id) \
263 (0x00011800FE060020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
264#define CVMX_DTX_LAPX_SELX(offset, block_id) \
265 (0x00011800FE060000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
266#define CVMX_DTX_LBK_BCST_RSP (0x00011800FE090080ull)
267#define CVMX_DTX_LBK_CTL (0x00011800FE090060ull)
268#define CVMX_DTX_LBK_DATX(offset) (0x00011800FE090040ull + ((offset) & 1) * 8)
269#define CVMX_DTX_LBK_ENAX(offset) (0x00011800FE090020ull + ((offset) & 1) * 8)
270#define CVMX_DTX_LBK_SELX(offset) (0x00011800FE090000ull + ((offset) & 1) * 8)
271#define CVMX_DTX_LMCX_BCST_RSP(offset) (0x00011800FE440080ull + ((offset) & 3) * 32768)
272#define CVMX_DTX_LMCX_CTL(offset) (0x00011800FE440060ull + ((offset) & 3) * 32768)
273#define CVMX_DTX_LMCX_DATX(offset, block_id) \
274 (0x00011800FE440040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
275#define CVMX_DTX_LMCX_ENAX(offset, block_id) \
276 (0x00011800FE440020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
277#define CVMX_DTX_LMCX_SELX(offset, block_id) \
278 (0x00011800FE440000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
279#define CVMX_DTX_MDBX_BCST_RSP(offset) (0x00011800FEC00080ull + ((offset) & 31) * 32768)
280#define CVMX_DTX_MDBX_CTL(offset) (0x00011800FEC00060ull + ((offset) & 31) * 32768)
281#define CVMX_DTX_MDBX_DATX(offset, block_id) \
282 (0x00011800FEC00040ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)
283#define CVMX_DTX_MDBX_ENAX(offset, block_id) \
284 (0x00011800FEC00020ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)
285#define CVMX_DTX_MDBX_SELX(offset, block_id) \
286 (0x00011800FEC00000ull + (((offset) & 1) + ((block_id) & 31) * 0x1000ull) * 8)
287#define CVMX_DTX_MHBW_BCST_RSP (0x00011800FE598080ull)
288#define CVMX_DTX_MHBW_CTL (0x00011800FE598060ull)
289#define CVMX_DTX_MHBW_DATX(offset) (0x00011800FE598040ull + ((offset) & 1) * 8)
290#define CVMX_DTX_MHBW_ENAX(offset) (0x00011800FE598020ull + ((offset) & 1) * 8)
291#define CVMX_DTX_MHBW_SELX(offset) (0x00011800FE598000ull + ((offset) & 1) * 8)
292#define CVMX_DTX_MIO_BCST_RSP (0x00011800FE000080ull)
293#define CVMX_DTX_MIO_CTL (0x00011800FE000060ull)
294#define CVMX_DTX_MIO_DATX(offset) (0x00011800FE000040ull + ((offset) & 1) * 8)
295#define CVMX_DTX_MIO_ENAX(offset) (0x00011800FE000020ull + ((offset) & 1) * 8)
296#define CVMX_DTX_MIO_SELX(offset) (0x00011800FE000000ull + ((offset) & 1) * 8)
297#define CVMX_DTX_OCX_BOT_BCST_RSP (0x00011800FE198080ull)
298#define CVMX_DTX_OCX_BOT_CTL (0x00011800FE198060ull)
299#define CVMX_DTX_OCX_BOT_DATX(offset) (0x00011800FE198040ull + ((offset) & 1) * 8)
300#define CVMX_DTX_OCX_BOT_ENAX(offset) (0x00011800FE198020ull + ((offset) & 1) * 8)
301#define CVMX_DTX_OCX_BOT_SELX(offset) (0x00011800FE198000ull + ((offset) & 1) * 8)
302#define CVMX_DTX_OCX_LNKX_BCST_RSP(offset) (0x00011800FE180080ull + ((offset) & 3) * 32768)
303#define CVMX_DTX_OCX_LNKX_CTL(offset) (0x00011800FE180060ull + ((offset) & 3) * 32768)
304#define CVMX_DTX_OCX_LNKX_DATX(offset, block_id) \
305 (0x00011800FE180040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
306#define CVMX_DTX_OCX_LNKX_ENAX(offset, block_id) \
307 (0x00011800FE180020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
308#define CVMX_DTX_OCX_LNKX_SELX(offset, block_id) \
309 (0x00011800FE180000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
310#define CVMX_DTX_OCX_OLEX_BCST_RSP(offset) (0x00011800FE1A0080ull + ((offset) & 3) * 32768)
311#define CVMX_DTX_OCX_OLEX_CTL(offset) (0x00011800FE1A0060ull + ((offset) & 3) * 32768)
312#define CVMX_DTX_OCX_OLEX_DATX(offset, block_id) \
313 (0x00011800FE1A0040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
314#define CVMX_DTX_OCX_OLEX_ENAX(offset, block_id) \
315 (0x00011800FE1A0020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
316#define CVMX_DTX_OCX_OLEX_SELX(offset, block_id) \
317 (0x00011800FE1A0000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
318#define CVMX_DTX_OCX_TOP_BCST_RSP (0x00011800FE088080ull)
319#define CVMX_DTX_OCX_TOP_CTL (0x00011800FE088060ull)
320#define CVMX_DTX_OCX_TOP_DATX(offset) (0x00011800FE088040ull + ((offset) & 1) * 8)
321#define CVMX_DTX_OCX_TOP_ENAX(offset) (0x00011800FE088020ull + ((offset) & 1) * 8)
322#define CVMX_DTX_OCX_TOP_SELX(offset) (0x00011800FE088000ull + ((offset) & 1) * 8)
323#define CVMX_DTX_OSM_BCST_RSP CVMX_DTX_OSM_BCST_RSP_FUNC()
324static inline u64 CVMX_DTX_OSM_BCST_RSP_FUNC(void)
325{
326 switch (cvmx_get_octeon_family()) {
327 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
328 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
329 return 0x00011800FE6E0080ull;
330 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
331 return 0x00011800FE6E0080ull;
332
333 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
334 return 0x00011800FEEE0080ull;
335 }
336 return 0x00011800FE6E0080ull;
337}
338
339#define CVMX_DTX_OSM_CTL CVMX_DTX_OSM_CTL_FUNC()
340static inline u64 CVMX_DTX_OSM_CTL_FUNC(void)
341{
342 switch (cvmx_get_octeon_family()) {
343 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
344 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
345 return 0x00011800FE6E0060ull;
346 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
347 return 0x00011800FE6E0060ull;
348
349 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
350 return 0x00011800FEEE0060ull;
351 }
352 return 0x00011800FE6E0060ull;
353}
354
355static inline u64 CVMX_DTX_OSM_DATX(unsigned long offset)
356{
357 switch (cvmx_get_octeon_family()) {
358 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
359 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
360 return 0x00011800FE6E0040ull + (offset) * 8;
361 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
362 return 0x00011800FE6E0040ull + (offset) * 8;
363
364 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
365 return 0x00011800FEEE0040ull + (offset) * 8;
366 }
367 return 0x00011800FE6E0040ull + (offset) * 8;
368}
369
370static inline u64 CVMX_DTX_OSM_ENAX(unsigned long offset)
371{
372 switch (cvmx_get_octeon_family()) {
373 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
374 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
375 return 0x00011800FE6E0020ull + (offset) * 8;
376 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
377 return 0x00011800FE6E0020ull + (offset) * 8;
378
379 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
380 return 0x00011800FEEE0020ull + (offset) * 8;
381 }
382 return 0x00011800FE6E0020ull + (offset) * 8;
383}
384
385static inline u64 CVMX_DTX_OSM_SELX(unsigned long offset)
386{
387 switch (cvmx_get_octeon_family()) {
388 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
389 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
390 return 0x00011800FE6E0000ull + (offset) * 8;
391 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
392 return 0x00011800FE6E0000ull + (offset) * 8;
393
394 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
395 return 0x00011800FEEE0000ull + (offset) * 8;
396 }
397 return 0x00011800FE6E0000ull + (offset) * 8;
398}
399
400#define CVMX_DTX_PCSX_BCST_RSP(offset) (0x00011800FE580080ull + ((offset) & 1) * 0x40000ull)
401#define CVMX_DTX_PCSX_CTL(offset) (0x00011800FE580060ull + ((offset) & 1) * 0x40000ull)
402#define CVMX_DTX_PCSX_DATX(offset, block_id) \
403 (0x00011800FE580040ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
404#define CVMX_DTX_PCSX_ENAX(offset, block_id) \
405 (0x00011800FE580020ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
406#define CVMX_DTX_PCSX_SELX(offset, block_id) \
407 (0x00011800FE580000ull + (((offset) & 1) + ((block_id) & 1) * 0x8000ull) * 8)
408#define CVMX_DTX_PEMX_BCST_RSP(offset) (0x00011800FE600080ull + ((offset) & 3) * 32768)
409#define CVMX_DTX_PEMX_CTL(offset) (0x00011800FE600060ull + ((offset) & 3) * 32768)
410#define CVMX_DTX_PEMX_DATX(offset, block_id) \
411 (0x00011800FE600040ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
412#define CVMX_DTX_PEMX_ENAX(offset, block_id) \
413 (0x00011800FE600020ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
414#define CVMX_DTX_PEMX_SELX(offset, block_id) \
415 (0x00011800FE600000ull + (((offset) & 1) + ((block_id) & 3) * 0x1000ull) * 8)
416#define CVMX_DTX_PIP_BCST_RSP (0x00011800FE500080ull)
417#define CVMX_DTX_PIP_CTL (0x00011800FE500060ull)
418#define CVMX_DTX_PIP_DATX(offset) (0x00011800FE500040ull + ((offset) & 1) * 8)
419#define CVMX_DTX_PIP_ENAX(offset) (0x00011800FE500020ull + ((offset) & 1) * 8)
420#define CVMX_DTX_PIP_SELX(offset) (0x00011800FE500000ull + ((offset) & 1) * 8)
421#define CVMX_DTX_PKI_PBE_BCST_RSP (0x00011800FE228080ull)
422#define CVMX_DTX_PKI_PBE_CTL (0x00011800FE228060ull)
423#define CVMX_DTX_PKI_PBE_DATX(offset) (0x00011800FE228040ull + ((offset) & 1) * 8)
424#define CVMX_DTX_PKI_PBE_ENAX(offset) (0x00011800FE228020ull + ((offset) & 1) * 8)
425#define CVMX_DTX_PKI_PBE_SELX(offset) (0x00011800FE228000ull + ((offset) & 1) * 8)
426#define CVMX_DTX_PKI_PFE_BCST_RSP (0x00011800FE220080ull)
427#define CVMX_DTX_PKI_PFE_CTL (0x00011800FE220060ull)
428#define CVMX_DTX_PKI_PFE_DATX(offset) (0x00011800FE220040ull + ((offset) & 1) * 8)
429#define CVMX_DTX_PKI_PFE_ENAX(offset) (0x00011800FE220020ull + ((offset) & 1) * 8)
430#define CVMX_DTX_PKI_PFE_SELX(offset) (0x00011800FE220000ull + ((offset) & 1) * 8)
431#define CVMX_DTX_PKI_PIX_BCST_RSP (0x00011800FE230080ull)
432#define CVMX_DTX_PKI_PIX_CTL (0x00011800FE230060ull)
433#define CVMX_DTX_PKI_PIX_DATX(offset) (0x00011800FE230040ull + ((offset) & 1) * 8)
434#define CVMX_DTX_PKI_PIX_ENAX(offset) (0x00011800FE230020ull + ((offset) & 1) * 8)
435#define CVMX_DTX_PKI_PIX_SELX(offset) (0x00011800FE230000ull + ((offset) & 1) * 8)
436#define CVMX_DTX_PKO_BCST_RSP CVMX_DTX_PKO_BCST_RSP_FUNC()
437static inline u64 CVMX_DTX_PKO_BCST_RSP_FUNC(void)
438{
439 switch (cvmx_get_octeon_family()) {
440 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
441 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
442 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
443 return 0x00011800FEAA0080ull;
444 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
445 return 0x00011800FEAA0080ull;
446 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
447 return 0x00011800FEAA0080ull;
448 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
449 return 0x00011800FE280080ull;
450 }
451 return 0x00011800FEAA0080ull;
452}
453
454#define CVMX_DTX_PKO_CTL CVMX_DTX_PKO_CTL_FUNC()
455static inline u64 CVMX_DTX_PKO_CTL_FUNC(void)
456{
457 switch (cvmx_get_octeon_family()) {
458 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
459 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
460 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
461 return 0x00011800FEAA0060ull;
462 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
463 return 0x00011800FEAA0060ull;
464 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
465 return 0x00011800FEAA0060ull;
466 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
467 return 0x00011800FE280060ull;
468 }
469 return 0x00011800FEAA0060ull;
470}
471
472static inline u64 CVMX_DTX_PKO_DATX(unsigned long offset)
473{
474 switch (cvmx_get_octeon_family()) {
475 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
476 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
477 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
478 return 0x00011800FEAA0040ull + (offset) * 8;
479 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
480 return 0x00011800FEAA0040ull + (offset) * 8;
481 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
482 return 0x00011800FEAA0040ull + (offset) * 8;
483 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
484 return 0x00011800FE280040ull + (offset) * 8;
485 }
486 return 0x00011800FEAA0040ull + (offset) * 8;
487}
488
489static inline u64 CVMX_DTX_PKO_ENAX(unsigned long offset)
490{
491 switch (cvmx_get_octeon_family()) {
492 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
493 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
494 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
495 return 0x00011800FEAA0020ull + (offset) * 8;
496 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
497 return 0x00011800FEAA0020ull + (offset) * 8;
498 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
499 return 0x00011800FEAA0020ull + (offset) * 8;
500 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
501 return 0x00011800FE280020ull + (offset) * 8;
502 }
503 return 0x00011800FEAA0020ull + (offset) * 8;
504}
505
506static inline u64 CVMX_DTX_PKO_SELX(unsigned long offset)
507{
508 switch (cvmx_get_octeon_family()) {
509 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
510 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
511 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
512 return 0x00011800FEAA0000ull + (offset) * 8;
513 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
514 return 0x00011800FEAA0000ull + (offset) * 8;
515 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
516 return 0x00011800FEAA0000ull + (offset) * 8;
517 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
518 return 0x00011800FE280000ull + (offset) * 8;
519 }
520 return 0x00011800FEAA0000ull + (offset) * 8;
521}
522
523#define CVMX_DTX_PNBDX_BCST_RSP(offset) (0x00011800FED90080ull + ((offset) & 1) * 32768)
524#define CVMX_DTX_PNBDX_CTL(offset) (0x00011800FED90060ull + ((offset) & 1) * 32768)
525#define CVMX_DTX_PNBDX_DATX(offset, block_id) \
526 (0x00011800FED90040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
527#define CVMX_DTX_PNBDX_ENAX(offset, block_id) \
528 (0x00011800FED90020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
529#define CVMX_DTX_PNBDX_SELX(offset, block_id) \
530 (0x00011800FED90000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
531#define CVMX_DTX_PNBX_BCST_RSP(offset) (0x00011800FE580080ull + ((offset) & 1) * 32768)
532#define CVMX_DTX_PNBX_CTL(offset) (0x00011800FE580060ull + ((offset) & 1) * 32768)
533#define CVMX_DTX_PNBX_DATX(offset, block_id) \
534 (0x00011800FE580040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
535#define CVMX_DTX_PNBX_ENAX(offset, block_id) \
536 (0x00011800FE580020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
537#define CVMX_DTX_PNBX_SELX(offset, block_id) \
538 (0x00011800FE580000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
539#define CVMX_DTX_POW_BCST_RSP (0x00011800FE338080ull)
540#define CVMX_DTX_POW_CTL (0x00011800FE338060ull)
541#define CVMX_DTX_POW_DATX(offset) (0x00011800FE338040ull + ((offset) & 1) * 8)
542#define CVMX_DTX_POW_ENAX(offset) (0x00011800FE338020ull + ((offset) & 1) * 8)
543#define CVMX_DTX_POW_SELX(offset) (0x00011800FE338000ull + ((offset) & 1) * 8)
544#define CVMX_DTX_PRCH_BCST_RSP (0x00011800FED00080ull)
545#define CVMX_DTX_PRCH_CTL (0x00011800FED00060ull)
546#define CVMX_DTX_PRCH_DATX(offset) (0x00011800FED00040ull + ((offset) & 1) * 8)
547#define CVMX_DTX_PRCH_ENAX(offset) (0x00011800FED00020ull + ((offset) & 1) * 8)
548#define CVMX_DTX_PRCH_SELX(offset) (0x00011800FED00000ull + ((offset) & 1) * 8)
549#define CVMX_DTX_PSM_BCST_RSP (0x00011800FEEA0080ull)
550#define CVMX_DTX_PSM_CTL (0x00011800FEEA0060ull)
551#define CVMX_DTX_PSM_DATX(offset) (0x00011800FEEA0040ull + ((offset) & 1) * 8)
552#define CVMX_DTX_PSM_ENAX(offset) (0x00011800FEEA0020ull + ((offset) & 1) * 8)
553#define CVMX_DTX_PSM_SELX(offset) (0x00011800FEEA0000ull + ((offset) & 1) * 8)
554#define CVMX_DTX_RAD_BCST_RSP (0x00011800FE380080ull)
555#define CVMX_DTX_RAD_CTL (0x00011800FE380060ull)
556#define CVMX_DTX_RAD_DATX(offset) (0x00011800FE380040ull + ((offset) & 1) * 8)
557#define CVMX_DTX_RAD_ENAX(offset) (0x00011800FE380020ull + ((offset) & 1) * 8)
558#define CVMX_DTX_RAD_SELX(offset) (0x00011800FE380000ull + ((offset) & 1) * 8)
559#define CVMX_DTX_RDEC_BCST_RSP (0x00011800FED68080ull)
560#define CVMX_DTX_RDEC_CTL (0x00011800FED68060ull)
561#define CVMX_DTX_RDEC_DATX(offset) (0x00011800FED68040ull + ((offset) & 1) * 8)
562#define CVMX_DTX_RDEC_ENAX(offset) (0x00011800FED68020ull + ((offset) & 1) * 8)
563#define CVMX_DTX_RDEC_SELX(offset) (0x00011800FED68000ull + ((offset) & 1) * 8)
564#define CVMX_DTX_RFIF_BCST_RSP (0x00011800FE6A8080ull)
565#define CVMX_DTX_RFIF_CTL (0x00011800FE6A8060ull)
566#define CVMX_DTX_RFIF_DATX(offset) (0x00011800FE6A8040ull + ((offset) & 1) * 8)
567#define CVMX_DTX_RFIF_ENAX(offset) (0x00011800FE6A8020ull + ((offset) & 1) * 8)
568#define CVMX_DTX_RFIF_SELX(offset) (0x00011800FE6A8000ull + ((offset) & 1) * 8)
569#define CVMX_DTX_RMAP_BCST_RSP (0x00011800FED40080ull)
570#define CVMX_DTX_RMAP_CTL (0x00011800FED40060ull)
571#define CVMX_DTX_RMAP_DATX(offset) (0x00011800FED40040ull + ((offset) & 1) * 8)
572#define CVMX_DTX_RMAP_ENAX(offset) (0x00011800FED40020ull + ((offset) & 1) * 8)
573#define CVMX_DTX_RMAP_SELX(offset) (0x00011800FED40000ull + ((offset) & 1) * 8)
574#define CVMX_DTX_RNM_BCST_RSP (0x00011800FE200080ull)
575#define CVMX_DTX_RNM_CTL (0x00011800FE200060ull)
576#define CVMX_DTX_RNM_DATX(offset) (0x00011800FE200040ull + ((offset) & 1) * 8)
577#define CVMX_DTX_RNM_ENAX(offset) (0x00011800FE200020ull + ((offset) & 1) * 8)
578#define CVMX_DTX_RNM_SELX(offset) (0x00011800FE200000ull + ((offset) & 1) * 8)
579#define CVMX_DTX_RST_BCST_RSP (0x00011800FE030080ull)
580#define CVMX_DTX_RST_CTL (0x00011800FE030060ull)
581#define CVMX_DTX_RST_DATX(offset) (0x00011800FE030040ull + ((offset) & 1) * 8)
582#define CVMX_DTX_RST_ENAX(offset) (0x00011800FE030020ull + ((offset) & 1) * 8)
583#define CVMX_DTX_RST_SELX(offset) (0x00011800FE030000ull + ((offset) & 1) * 8)
584#define CVMX_DTX_SATA_BCST_RSP (0x00011800FE360080ull)
585#define CVMX_DTX_SATA_CTL (0x00011800FE360060ull)
586#define CVMX_DTX_SATA_DATX(offset) (0x00011800FE360040ull + ((offset) & 1) * 8)
587#define CVMX_DTX_SATA_ENAX(offset) (0x00011800FE360020ull + ((offset) & 1) * 8)
588#define CVMX_DTX_SATA_SELX(offset) (0x00011800FE360000ull + ((offset) & 1) * 8)
589#define CVMX_DTX_SLI_BCST_RSP (0x00011800FE8F8080ull)
590#define CVMX_DTX_SLI_CTL (0x00011800FE8F8060ull)
591#define CVMX_DTX_SLI_DATX(offset) (0x00011800FE8F8040ull + ((offset) & 1) * 8)
592#define CVMX_DTX_SLI_ENAX(offset) (0x00011800FE8F8020ull + ((offset) & 1) * 8)
593#define CVMX_DTX_SLI_SELX(offset) (0x00011800FE8F8000ull + ((offset) & 1) * 8)
594#define CVMX_DTX_SPEM_BCST_RSP (0x00011800FE600080ull)
595#define CVMX_DTX_SPEM_CTL (0x00011800FE600060ull)
596#define CVMX_DTX_SPEM_DATX(offset) (0x00011800FE600040ull + ((offset) & 1) * 8)
597#define CVMX_DTX_SPEM_ENAX(offset) (0x00011800FE600020ull + ((offset) & 1) * 8)
598#define CVMX_DTX_SPEM_SELX(offset) (0x00011800FE600000ull + ((offset) & 1) * 8)
599#define CVMX_DTX_SRIOX_BCST_RSP(offset) (0x00011800FE640080ull + ((offset) & 1) * 32768)
600#define CVMX_DTX_SRIOX_CTL(offset) (0x00011800FE640060ull + ((offset) & 1) * 32768)
601#define CVMX_DTX_SRIOX_DATX(offset, block_id) \
602 (0x00011800FE640040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
603#define CVMX_DTX_SRIOX_ENAX(offset, block_id) \
604 (0x00011800FE640020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
605#define CVMX_DTX_SRIOX_SELX(offset, block_id) \
606 (0x00011800FE640000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
607#define CVMX_DTX_SSO_BCST_RSP (0x00011800FEB38080ull)
608#define CVMX_DTX_SSO_CTL (0x00011800FEB38060ull)
609#define CVMX_DTX_SSO_DATX(offset) (0x00011800FEB38040ull + ((offset) & 1) * 8)
610#define CVMX_DTX_SSO_ENAX(offset) (0x00011800FEB38020ull + ((offset) & 1) * 8)
611#define CVMX_DTX_SSO_SELX(offset) (0x00011800FEB38000ull + ((offset) & 1) * 8)
612#define CVMX_DTX_TDEC_BCST_RSP (0x00011800FED60080ull)
613#define CVMX_DTX_TDEC_CTL (0x00011800FED60060ull)
614#define CVMX_DTX_TDEC_DATX(offset) (0x00011800FED60040ull + ((offset) & 1) * 8)
615#define CVMX_DTX_TDEC_ENAX(offset) (0x00011800FED60020ull + ((offset) & 1) * 8)
616#define CVMX_DTX_TDEC_SELX(offset) (0x00011800FED60000ull + ((offset) & 1) * 8)
617#define CVMX_DTX_TIM_BCST_RSP (0x00011800FE2C0080ull)
618#define CVMX_DTX_TIM_CTL (0x00011800FE2C0060ull)
619#define CVMX_DTX_TIM_DATX(offset) (0x00011800FE2C0040ull + ((offset) & 1) * 8)
620#define CVMX_DTX_TIM_ENAX(offset) (0x00011800FE2C0020ull + ((offset) & 1) * 8)
621#define CVMX_DTX_TIM_SELX(offset) (0x00011800FE2C0000ull + ((offset) & 1) * 8)
622#define CVMX_DTX_ULFE_BCST_RSP (0x00011800FED08080ull)
623#define CVMX_DTX_ULFE_CTL (0x00011800FED08060ull)
624#define CVMX_DTX_ULFE_DATX(offset) (0x00011800FED08040ull + ((offset) & 1) * 8)
625#define CVMX_DTX_ULFE_ENAX(offset) (0x00011800FED08020ull + ((offset) & 1) * 8)
626#define CVMX_DTX_ULFE_SELX(offset) (0x00011800FED08000ull + ((offset) & 1) * 8)
627#define CVMX_DTX_USBDRDX_BCST_RSP(offset) (0x00011800FE340080ull + ((offset) & 1) * 32768)
628#define CVMX_DTX_USBDRDX_CTL(offset) (0x00011800FE340060ull + ((offset) & 1) * 32768)
629#define CVMX_DTX_USBDRDX_DATX(offset, block_id) \
630 (0x00011800FE340040ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
631#define CVMX_DTX_USBDRDX_ENAX(offset, block_id) \
632 (0x00011800FE340020ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
633#define CVMX_DTX_USBDRDX_SELX(offset, block_id) \
634 (0x00011800FE340000ull + (((offset) & 1) + ((block_id) & 1) * 0x1000ull) * 8)
635#define CVMX_DTX_USBHX_BCST_RSP(offset) (0x00011800FE340080ull)
636#define CVMX_DTX_USBHX_CTL(offset) (0x00011800FE340060ull)
637#define CVMX_DTX_USBHX_DATX(offset, block_id) \
638 (0x00011800FE340040ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
639#define CVMX_DTX_USBHX_ENAX(offset, block_id) \
640 (0x00011800FE340020ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
641#define CVMX_DTX_USBHX_SELX(offset, block_id) \
642 (0x00011800FE340000ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
643#define CVMX_DTX_VDEC_BCST_RSP (0x00011800FED70080ull)
644#define CVMX_DTX_VDEC_CTL (0x00011800FED70060ull)
645#define CVMX_DTX_VDEC_DATX(offset) (0x00011800FED70040ull + ((offset) & 1) * 8)
646#define CVMX_DTX_VDEC_ENAX(offset) (0x00011800FED70020ull + ((offset) & 1) * 8)
647#define CVMX_DTX_VDEC_SELX(offset) (0x00011800FED70000ull + ((offset) & 1) * 8)
648#define CVMX_DTX_WPSE_BCST_RSP (0x00011800FED10080ull)
649#define CVMX_DTX_WPSE_CTL (0x00011800FED10060ull)
650#define CVMX_DTX_WPSE_DATX(offset) (0x00011800FED10040ull + ((offset) & 1) * 8)
651#define CVMX_DTX_WPSE_ENAX(offset) (0x00011800FED10020ull + ((offset) & 1) * 8)
652#define CVMX_DTX_WPSE_SELX(offset) (0x00011800FED10000ull + ((offset) & 1) * 8)
653#define CVMX_DTX_WRCE_BCST_RSP (0x00011800FED38080ull)
654#define CVMX_DTX_WRCE_CTL (0x00011800FED38060ull)
655#define CVMX_DTX_WRCE_DATX(offset) (0x00011800FED38040ull + ((offset) & 1) * 8)
656#define CVMX_DTX_WRCE_ENAX(offset) (0x00011800FED38020ull + ((offset) & 1) * 8)
657#define CVMX_DTX_WRCE_SELX(offset) (0x00011800FED38000ull + ((offset) & 1) * 8)
658#define CVMX_DTX_WRDE_BCST_RSP (0x00011800FED58080ull)
659#define CVMX_DTX_WRDE_CTL (0x00011800FED58060ull)
660#define CVMX_DTX_WRDE_DATX(offset) (0x00011800FED58040ull + ((offset) & 1) * 8)
661#define CVMX_DTX_WRDE_ENAX(offset) (0x00011800FED58020ull + ((offset) & 1) * 8)
662#define CVMX_DTX_WRDE_SELX(offset) (0x00011800FED58000ull + ((offset) & 1) * 8)
663#define CVMX_DTX_WRSE_BCST_RSP (0x00011800FED28080ull)
664#define CVMX_DTX_WRSE_CTL (0x00011800FED28060ull)
665#define CVMX_DTX_WRSE_DATX(offset) (0x00011800FED28040ull + ((offset) & 1) * 8)
666#define CVMX_DTX_WRSE_ENAX(offset) (0x00011800FED28020ull + ((offset) & 1) * 8)
667#define CVMX_DTX_WRSE_SELX(offset) (0x00011800FED28000ull + ((offset) & 1) * 8)
668#define CVMX_DTX_WTXE_BCST_RSP (0x00011800FED20080ull)
669#define CVMX_DTX_WTXE_CTL (0x00011800FED20060ull)
670#define CVMX_DTX_WTXE_DATX(offset) (0x00011800FED20040ull + ((offset) & 1) * 8)
671#define CVMX_DTX_WTXE_ENAX(offset) (0x00011800FED20020ull + ((offset) & 1) * 8)
672#define CVMX_DTX_WTXE_SELX(offset) (0x00011800FED20000ull + ((offset) & 1) * 8)
673#define CVMX_DTX_XCV_BCST_RSP (0x00011800FE6D8080ull)
674#define CVMX_DTX_XCV_CTL (0x00011800FE6D8060ull)
675#define CVMX_DTX_XCV_DATX(offset) (0x00011800FE6D8040ull + ((offset) & 1) * 8)
676#define CVMX_DTX_XCV_ENAX(offset) (0x00011800FE6D8020ull + ((offset) & 1) * 8)
677#define CVMX_DTX_XCV_SELX(offset) (0x00011800FE6D8000ull + ((offset) & 1) * 8)
678#define CVMX_DTX_XSX_BCST_RSP (0x00011800FE5A8080ull)
679#define CVMX_DTX_XSX_CTL (0x00011800FE5A8060ull)
680#define CVMX_DTX_XSX_DATX(offset) (0x00011800FE5A8040ull + ((offset) & 1) * 8)
681#define CVMX_DTX_XSX_ENAX(offset) (0x00011800FE5A8020ull + ((offset) & 1) * 8)
682#define CVMX_DTX_XSX_SELX(offset) (0x00011800FE5A8000ull + ((offset) & 1) * 8)
683#define CVMX_DTX_ZIP_BCST_RSP (0x00011800FE1C0080ull)
684#define CVMX_DTX_ZIP_CTL (0x00011800FE1C0060ull)
685#define CVMX_DTX_ZIP_DATX(offset) (0x00011800FE1C0040ull + ((offset) & 1) * 8)
686#define CVMX_DTX_ZIP_ENAX(offset) (0x00011800FE1C0020ull + ((offset) & 1) * 8)
687#define CVMX_DTX_ZIP_SELX(offset) (0x00011800FE1C0000ull + ((offset) & 1) * 8)
688
689/**
690 * cvmx_dtx_agl_bcst_rsp
691 */
692union cvmx_dtx_agl_bcst_rsp {
693 u64 u64;
694 struct cvmx_dtx_agl_bcst_rsp_s {
695 u64 reserved_1_63 : 63;
696 u64 ena : 1;
697 } s;
698 struct cvmx_dtx_agl_bcst_rsp_s cn70xx;
699 struct cvmx_dtx_agl_bcst_rsp_s cn70xxp1;
700};
701
702typedef union cvmx_dtx_agl_bcst_rsp cvmx_dtx_agl_bcst_rsp_t;
703
704/**
705 * cvmx_dtx_agl_ctl
706 */
707union cvmx_dtx_agl_ctl {
708 u64 u64;
709 struct cvmx_dtx_agl_ctl_s {
710 u64 reserved_5_63 : 59;
711 u64 active : 1;
712 u64 reserved_2_3 : 2;
713 u64 echoen : 1;
714 u64 swap : 1;
715 } s;
716 struct cvmx_dtx_agl_ctl_s cn70xx;
717 struct cvmx_dtx_agl_ctl_s cn70xxp1;
718};
719
720typedef union cvmx_dtx_agl_ctl cvmx_dtx_agl_ctl_t;
721
722/**
723 * cvmx_dtx_agl_dat#
724 */
725union cvmx_dtx_agl_datx {
726 u64 u64;
727 struct cvmx_dtx_agl_datx_s {
728 u64 reserved_36_63 : 28;
729 u64 raw : 36;
730 } s;
731 struct cvmx_dtx_agl_datx_s cn70xx;
732 struct cvmx_dtx_agl_datx_s cn70xxp1;
733};
734
735typedef union cvmx_dtx_agl_datx cvmx_dtx_agl_datx_t;
736
737/**
738 * cvmx_dtx_agl_ena#
739 */
740union cvmx_dtx_agl_enax {
741 u64 u64;
742 struct cvmx_dtx_agl_enax_s {
743 u64 reserved_36_63 : 28;
744 u64 ena : 36;
745 } s;
746 struct cvmx_dtx_agl_enax_s cn70xx;
747 struct cvmx_dtx_agl_enax_s cn70xxp1;
748};
749
750typedef union cvmx_dtx_agl_enax cvmx_dtx_agl_enax_t;
751
752/**
753 * cvmx_dtx_agl_sel#
754 */
755union cvmx_dtx_agl_selx {
756 u64 u64;
757 struct cvmx_dtx_agl_selx_s {
758 u64 reserved_24_63 : 40;
759 u64 value : 24;
760 } s;
761 struct cvmx_dtx_agl_selx_s cn70xx;
762 struct cvmx_dtx_agl_selx_s cn70xxp1;
763};
764
765typedef union cvmx_dtx_agl_selx cvmx_dtx_agl_selx_t;
766
767/**
768 * cvmx_dtx_ase_bcst_rsp
769 */
770union cvmx_dtx_ase_bcst_rsp {
771 u64 u64;
772 struct cvmx_dtx_ase_bcst_rsp_s {
773 u64 reserved_1_63 : 63;
774 u64 ena : 1;
775 } s;
776 struct cvmx_dtx_ase_bcst_rsp_s cn78xx;
777 struct cvmx_dtx_ase_bcst_rsp_s cn78xxp1;
778};
779
780typedef union cvmx_dtx_ase_bcst_rsp cvmx_dtx_ase_bcst_rsp_t;
781
782/**
783 * cvmx_dtx_ase_ctl
784 */
785union cvmx_dtx_ase_ctl {
786 u64 u64;
787 struct cvmx_dtx_ase_ctl_s {
788 u64 reserved_5_63 : 59;
789 u64 active : 1;
790 u64 reserved_2_3 : 2;
791 u64 echoen : 1;
792 u64 swap : 1;
793 } s;
794 struct cvmx_dtx_ase_ctl_s cn78xx;
795 struct cvmx_dtx_ase_ctl_s cn78xxp1;
796};
797
798typedef union cvmx_dtx_ase_ctl cvmx_dtx_ase_ctl_t;
799
800/**
801 * cvmx_dtx_ase_dat#
802 */
803union cvmx_dtx_ase_datx {
804 u64 u64;
805 struct cvmx_dtx_ase_datx_s {
806 u64 reserved_36_63 : 28;
807 u64 raw : 36;
808 } s;
809 struct cvmx_dtx_ase_datx_s cn78xx;
810 struct cvmx_dtx_ase_datx_s cn78xxp1;
811};
812
813typedef union cvmx_dtx_ase_datx cvmx_dtx_ase_datx_t;
814
815/**
816 * cvmx_dtx_ase_ena#
817 */
818union cvmx_dtx_ase_enax {
819 u64 u64;
820 struct cvmx_dtx_ase_enax_s {
821 u64 reserved_36_63 : 28;
822 u64 ena : 36;
823 } s;
824 struct cvmx_dtx_ase_enax_s cn78xx;
825 struct cvmx_dtx_ase_enax_s cn78xxp1;
826};
827
828typedef union cvmx_dtx_ase_enax cvmx_dtx_ase_enax_t;
829
830/**
831 * cvmx_dtx_ase_sel#
832 */
833union cvmx_dtx_ase_selx {
834 u64 u64;
835 struct cvmx_dtx_ase_selx_s {
836 u64 reserved_24_63 : 40;
837 u64 value : 24;
838 } s;
839 struct cvmx_dtx_ase_selx_s cn78xx;
840 struct cvmx_dtx_ase_selx_s cn78xxp1;
841};
842
843typedef union cvmx_dtx_ase_selx cvmx_dtx_ase_selx_t;
844
845/**
846 * cvmx_dtx_bbx1i_bcst_rsp
847 */
848union cvmx_dtx_bbx1i_bcst_rsp {
849 u64 u64;
850 struct cvmx_dtx_bbx1i_bcst_rsp_s {
851 u64 reserved_1_63 : 63;
852 u64 ena : 1;
853 } s;
854 struct cvmx_dtx_bbx1i_bcst_rsp_s cnf75xx;
855};
856
857typedef union cvmx_dtx_bbx1i_bcst_rsp cvmx_dtx_bbx1i_bcst_rsp_t;
858
859/**
860 * cvmx_dtx_bbx1i_ctl
861 */
862union cvmx_dtx_bbx1i_ctl {
863 u64 u64;
864 struct cvmx_dtx_bbx1i_ctl_s {
865 u64 reserved_5_63 : 59;
866 u64 active : 1;
867 u64 reserved_2_3 : 2;
868 u64 echoen : 1;
869 u64 swap : 1;
870 } s;
871 struct cvmx_dtx_bbx1i_ctl_s cnf75xx;
872};
873
874typedef union cvmx_dtx_bbx1i_ctl cvmx_dtx_bbx1i_ctl_t;
875
876/**
877 * cvmx_dtx_bbx1i_dat#
878 */
879union cvmx_dtx_bbx1i_datx {
880 u64 u64;
881 struct cvmx_dtx_bbx1i_datx_s {
882 u64 reserved_36_63 : 28;
883 u64 raw : 36;
884 } s;
885 struct cvmx_dtx_bbx1i_datx_s cnf75xx;
886};
887
888typedef union cvmx_dtx_bbx1i_datx cvmx_dtx_bbx1i_datx_t;
889
890/**
891 * cvmx_dtx_bbx1i_ena#
892 */
893union cvmx_dtx_bbx1i_enax {
894 u64 u64;
895 struct cvmx_dtx_bbx1i_enax_s {
896 u64 reserved_36_63 : 28;
897 u64 ena : 36;
898 } s;
899 struct cvmx_dtx_bbx1i_enax_s cnf75xx;
900};
901
902typedef union cvmx_dtx_bbx1i_enax cvmx_dtx_bbx1i_enax_t;
903
904/**
905 * cvmx_dtx_bbx1i_sel#
906 */
907union cvmx_dtx_bbx1i_selx {
908 u64 u64;
909 struct cvmx_dtx_bbx1i_selx_s {
910 u64 reserved_24_63 : 40;
911 u64 value : 24;
912 } s;
913 struct cvmx_dtx_bbx1i_selx_s cnf75xx;
914};
915
916typedef union cvmx_dtx_bbx1i_selx cvmx_dtx_bbx1i_selx_t;
917
918/**
919 * cvmx_dtx_bbx2i_bcst_rsp
920 */
921union cvmx_dtx_bbx2i_bcst_rsp {
922 u64 u64;
923 struct cvmx_dtx_bbx2i_bcst_rsp_s {
924 u64 reserved_1_63 : 63;
925 u64 ena : 1;
926 } s;
927 struct cvmx_dtx_bbx2i_bcst_rsp_s cnf75xx;
928};
929
930typedef union cvmx_dtx_bbx2i_bcst_rsp cvmx_dtx_bbx2i_bcst_rsp_t;
931
932/**
933 * cvmx_dtx_bbx2i_ctl
934 */
935union cvmx_dtx_bbx2i_ctl {
936 u64 u64;
937 struct cvmx_dtx_bbx2i_ctl_s {
938 u64 reserved_5_63 : 59;
939 u64 active : 1;
940 u64 reserved_2_3 : 2;
941 u64 echoen : 1;
942 u64 swap : 1;
943 } s;
944 struct cvmx_dtx_bbx2i_ctl_s cnf75xx;
945};
946
947typedef union cvmx_dtx_bbx2i_ctl cvmx_dtx_bbx2i_ctl_t;
948
949/**
950 * cvmx_dtx_bbx2i_dat#
951 */
952union cvmx_dtx_bbx2i_datx {
953 u64 u64;
954 struct cvmx_dtx_bbx2i_datx_s {
955 u64 reserved_36_63 : 28;
956 u64 raw : 36;
957 } s;
958 struct cvmx_dtx_bbx2i_datx_s cnf75xx;
959};
960
961typedef union cvmx_dtx_bbx2i_datx cvmx_dtx_bbx2i_datx_t;
962
963/**
964 * cvmx_dtx_bbx2i_ena#
965 */
966union cvmx_dtx_bbx2i_enax {
967 u64 u64;
968 struct cvmx_dtx_bbx2i_enax_s {
969 u64 reserved_36_63 : 28;
970 u64 ena : 36;
971 } s;
972 struct cvmx_dtx_bbx2i_enax_s cnf75xx;
973};
974
975typedef union cvmx_dtx_bbx2i_enax cvmx_dtx_bbx2i_enax_t;
976
977/**
978 * cvmx_dtx_bbx2i_sel#
979 */
980union cvmx_dtx_bbx2i_selx {
981 u64 u64;
982 struct cvmx_dtx_bbx2i_selx_s {
983 u64 reserved_24_63 : 40;
984 u64 value : 24;
985 } s;
986 struct cvmx_dtx_bbx2i_selx_s cnf75xx;
987};
988
989typedef union cvmx_dtx_bbx2i_selx cvmx_dtx_bbx2i_selx_t;
990
991/**
992 * cvmx_dtx_bbx3i_bcst_rsp
993 */
994union cvmx_dtx_bbx3i_bcst_rsp {
995 u64 u64;
996 struct cvmx_dtx_bbx3i_bcst_rsp_s {
997 u64 reserved_1_63 : 63;
998 u64 ena : 1;
999 } s;
1000 struct cvmx_dtx_bbx3i_bcst_rsp_s cnf75xx;
1001};
1002
1003typedef union cvmx_dtx_bbx3i_bcst_rsp cvmx_dtx_bbx3i_bcst_rsp_t;
1004
1005/**
1006 * cvmx_dtx_bbx3i_ctl
1007 */
1008union cvmx_dtx_bbx3i_ctl {
1009 u64 u64;
1010 struct cvmx_dtx_bbx3i_ctl_s {
1011 u64 reserved_5_63 : 59;
1012 u64 active : 1;
1013 u64 reserved_2_3 : 2;
1014 u64 echoen : 1;
1015 u64 swap : 1;
1016 } s;
1017 struct cvmx_dtx_bbx3i_ctl_s cnf75xx;
1018};
1019
1020typedef union cvmx_dtx_bbx3i_ctl cvmx_dtx_bbx3i_ctl_t;
1021
1022/**
1023 * cvmx_dtx_bbx3i_dat#
1024 */
1025union cvmx_dtx_bbx3i_datx {
1026 u64 u64;
1027 struct cvmx_dtx_bbx3i_datx_s {
1028 u64 reserved_36_63 : 28;
1029 u64 raw : 36;
1030 } s;
1031 struct cvmx_dtx_bbx3i_datx_s cnf75xx;
1032};
1033
1034typedef union cvmx_dtx_bbx3i_datx cvmx_dtx_bbx3i_datx_t;
1035
1036/**
1037 * cvmx_dtx_bbx3i_ena#
1038 */
1039union cvmx_dtx_bbx3i_enax {
1040 u64 u64;
1041 struct cvmx_dtx_bbx3i_enax_s {
1042 u64 reserved_36_63 : 28;
1043 u64 ena : 36;
1044 } s;
1045 struct cvmx_dtx_bbx3i_enax_s cnf75xx;
1046};
1047
1048typedef union cvmx_dtx_bbx3i_enax cvmx_dtx_bbx3i_enax_t;
1049
1050/**
1051 * cvmx_dtx_bbx3i_sel#
1052 */
1053union cvmx_dtx_bbx3i_selx {
1054 u64 u64;
1055 struct cvmx_dtx_bbx3i_selx_s {
1056 u64 reserved_24_63 : 40;
1057 u64 value : 24;
1058 } s;
1059 struct cvmx_dtx_bbx3i_selx_s cnf75xx;
1060};
1061
1062typedef union cvmx_dtx_bbx3i_selx cvmx_dtx_bbx3i_selx_t;
1063
1064/**
1065 * cvmx_dtx_bch_bcst_rsp
1066 */
1067union cvmx_dtx_bch_bcst_rsp {
1068 u64 u64;
1069 struct cvmx_dtx_bch_bcst_rsp_s {
1070 u64 reserved_1_63 : 63;
1071 u64 ena : 1;
1072 } s;
1073 struct cvmx_dtx_bch_bcst_rsp_s cn73xx;
1074 struct cvmx_dtx_bch_bcst_rsp_s cnf75xx;
1075};
1076
1077typedef union cvmx_dtx_bch_bcst_rsp cvmx_dtx_bch_bcst_rsp_t;
1078
1079/**
1080 * cvmx_dtx_bch_ctl
1081 */
1082union cvmx_dtx_bch_ctl {
1083 u64 u64;
1084 struct cvmx_dtx_bch_ctl_s {
1085 u64 reserved_5_63 : 59;
1086 u64 active : 1;
1087 u64 reserved_2_3 : 2;
1088 u64 echoen : 1;
1089 u64 swap : 1;
1090 } s;
1091 struct cvmx_dtx_bch_ctl_s cn73xx;
1092 struct cvmx_dtx_bch_ctl_s cnf75xx;
1093};
1094
1095typedef union cvmx_dtx_bch_ctl cvmx_dtx_bch_ctl_t;
1096
1097/**
1098 * cvmx_dtx_bch_dat#
1099 */
1100union cvmx_dtx_bch_datx {
1101 u64 u64;
1102 struct cvmx_dtx_bch_datx_s {
1103 u64 reserved_36_63 : 28;
1104 u64 raw : 36;
1105 } s;
1106 struct cvmx_dtx_bch_datx_s cn73xx;
1107 struct cvmx_dtx_bch_datx_s cnf75xx;
1108};
1109
1110typedef union cvmx_dtx_bch_datx cvmx_dtx_bch_datx_t;
1111
1112/**
1113 * cvmx_dtx_bch_ena#
1114 */
1115union cvmx_dtx_bch_enax {
1116 u64 u64;
1117 struct cvmx_dtx_bch_enax_s {
1118 u64 reserved_36_63 : 28;
1119 u64 ena : 36;
1120 } s;
1121 struct cvmx_dtx_bch_enax_s cn73xx;
1122 struct cvmx_dtx_bch_enax_s cnf75xx;
1123};
1124
1125typedef union cvmx_dtx_bch_enax cvmx_dtx_bch_enax_t;
1126
1127/**
1128 * cvmx_dtx_bch_sel#
1129 */
1130union cvmx_dtx_bch_selx {
1131 u64 u64;
1132 struct cvmx_dtx_bch_selx_s {
1133 u64 reserved_24_63 : 40;
1134 u64 value : 24;
1135 } s;
1136 struct cvmx_dtx_bch_selx_s cn73xx;
1137 struct cvmx_dtx_bch_selx_s cnf75xx;
1138};
1139
1140typedef union cvmx_dtx_bch_selx cvmx_dtx_bch_selx_t;
1141
1142/**
1143 * cvmx_dtx_bgx#_bcst_rsp
1144 */
1145union cvmx_dtx_bgxx_bcst_rsp {
1146 u64 u64;
1147 struct cvmx_dtx_bgxx_bcst_rsp_s {
1148 u64 reserved_1_63 : 63;
1149 u64 ena : 1;
1150 } s;
1151 struct cvmx_dtx_bgxx_bcst_rsp_s cn73xx;
1152 struct cvmx_dtx_bgxx_bcst_rsp_s cn78xx;
1153 struct cvmx_dtx_bgxx_bcst_rsp_s cn78xxp1;
1154 struct cvmx_dtx_bgxx_bcst_rsp_s cnf75xx;
1155};
1156
1157typedef union cvmx_dtx_bgxx_bcst_rsp cvmx_dtx_bgxx_bcst_rsp_t;
1158
1159/**
1160 * cvmx_dtx_bgx#_ctl
1161 */
1162union cvmx_dtx_bgxx_ctl {
1163 u64 u64;
1164 struct cvmx_dtx_bgxx_ctl_s {
1165 u64 reserved_5_63 : 59;
1166 u64 active : 1;
1167 u64 reserved_2_3 : 2;
1168 u64 echoen : 1;
1169 u64 swap : 1;
1170 } s;
1171 struct cvmx_dtx_bgxx_ctl_s cn73xx;
1172 struct cvmx_dtx_bgxx_ctl_s cn78xx;
1173 struct cvmx_dtx_bgxx_ctl_s cn78xxp1;
1174 struct cvmx_dtx_bgxx_ctl_s cnf75xx;
1175};
1176
1177typedef union cvmx_dtx_bgxx_ctl cvmx_dtx_bgxx_ctl_t;
1178
1179/**
1180 * cvmx_dtx_bgx#_dat#
1181 */
1182union cvmx_dtx_bgxx_datx {
1183 u64 u64;
1184 struct cvmx_dtx_bgxx_datx_s {
1185 u64 reserved_36_63 : 28;
1186 u64 raw : 36;
1187 } s;
1188 struct cvmx_dtx_bgxx_datx_s cn73xx;
1189 struct cvmx_dtx_bgxx_datx_s cn78xx;
1190 struct cvmx_dtx_bgxx_datx_s cn78xxp1;
1191 struct cvmx_dtx_bgxx_datx_s cnf75xx;
1192};
1193
1194typedef union cvmx_dtx_bgxx_datx cvmx_dtx_bgxx_datx_t;
1195
1196/**
1197 * cvmx_dtx_bgx#_ena#
1198 */
1199union cvmx_dtx_bgxx_enax {
1200 u64 u64;
1201 struct cvmx_dtx_bgxx_enax_s {
1202 u64 reserved_36_63 : 28;
1203 u64 ena : 36;
1204 } s;
1205 struct cvmx_dtx_bgxx_enax_s cn73xx;
1206 struct cvmx_dtx_bgxx_enax_s cn78xx;
1207 struct cvmx_dtx_bgxx_enax_s cn78xxp1;
1208 struct cvmx_dtx_bgxx_enax_s cnf75xx;
1209};
1210
1211typedef union cvmx_dtx_bgxx_enax cvmx_dtx_bgxx_enax_t;
1212
1213/**
1214 * cvmx_dtx_bgx#_sel#
1215 */
1216union cvmx_dtx_bgxx_selx {
1217 u64 u64;
1218 struct cvmx_dtx_bgxx_selx_s {
1219 u64 reserved_24_63 : 40;
1220 u64 value : 24;
1221 } s;
1222 struct cvmx_dtx_bgxx_selx_s cn73xx;
1223 struct cvmx_dtx_bgxx_selx_s cn78xx;
1224 struct cvmx_dtx_bgxx_selx_s cn78xxp1;
1225 struct cvmx_dtx_bgxx_selx_s cnf75xx;
1226};
1227
1228typedef union cvmx_dtx_bgxx_selx cvmx_dtx_bgxx_selx_t;
1229
1230/**
1231 * cvmx_dtx_broadcast_ctl
1232 */
1233union cvmx_dtx_broadcast_ctl {
1234 u64 u64;
1235 struct cvmx_dtx_broadcast_ctl_s {
1236 u64 reserved_5_63 : 59;
1237 u64 active : 1;
1238 u64 reserved_2_3 : 2;
1239 u64 echoen : 1;
1240 u64 swap : 1;
1241 } s;
1242 struct cvmx_dtx_broadcast_ctl_s cn70xx;
1243 struct cvmx_dtx_broadcast_ctl_s cn70xxp1;
1244 struct cvmx_dtx_broadcast_ctl_s cn73xx;
1245 struct cvmx_dtx_broadcast_ctl_s cn78xx;
1246 struct cvmx_dtx_broadcast_ctl_s cn78xxp1;
1247 struct cvmx_dtx_broadcast_ctl_s cnf75xx;
1248};
1249
1250typedef union cvmx_dtx_broadcast_ctl cvmx_dtx_broadcast_ctl_t;
1251
1252/**
1253 * cvmx_dtx_broadcast_ena#
1254 */
1255union cvmx_dtx_broadcast_enax {
1256 u64 u64;
1257 struct cvmx_dtx_broadcast_enax_s {
1258 u64 reserved_36_63 : 28;
1259 u64 ena : 36;
1260 } s;
1261 struct cvmx_dtx_broadcast_enax_s cn70xx;
1262 struct cvmx_dtx_broadcast_enax_s cn70xxp1;
1263 struct cvmx_dtx_broadcast_enax_s cn73xx;
1264 struct cvmx_dtx_broadcast_enax_s cn78xx;
1265 struct cvmx_dtx_broadcast_enax_s cn78xxp1;
1266 struct cvmx_dtx_broadcast_enax_s cnf75xx;
1267};
1268
1269typedef union cvmx_dtx_broadcast_enax cvmx_dtx_broadcast_enax_t;
1270
1271/**
1272 * cvmx_dtx_broadcast_sel#
1273 */
1274union cvmx_dtx_broadcast_selx {
1275 u64 u64;
1276 struct cvmx_dtx_broadcast_selx_s {
1277 u64 reserved_24_63 : 40;
1278 u64 value : 24;
1279 } s;
1280 struct cvmx_dtx_broadcast_selx_s cn70xx;
1281 struct cvmx_dtx_broadcast_selx_s cn70xxp1;
1282 struct cvmx_dtx_broadcast_selx_s cn73xx;
1283 struct cvmx_dtx_broadcast_selx_s cn78xx;
1284 struct cvmx_dtx_broadcast_selx_s cn78xxp1;
1285 struct cvmx_dtx_broadcast_selx_s cnf75xx;
1286};
1287
1288typedef union cvmx_dtx_broadcast_selx cvmx_dtx_broadcast_selx_t;
1289
1290/**
1291 * cvmx_dtx_bts_bcst_rsp
1292 */
1293union cvmx_dtx_bts_bcst_rsp {
1294 u64 u64;
1295 struct cvmx_dtx_bts_bcst_rsp_s {
1296 u64 reserved_1_63 : 63;
1297 u64 ena : 1;
1298 } s;
1299 struct cvmx_dtx_bts_bcst_rsp_s cnf75xx;
1300};
1301
1302typedef union cvmx_dtx_bts_bcst_rsp cvmx_dtx_bts_bcst_rsp_t;
1303
1304/**
1305 * cvmx_dtx_bts_ctl
1306 */
1307union cvmx_dtx_bts_ctl {
1308 u64 u64;
1309 struct cvmx_dtx_bts_ctl_s {
1310 u64 reserved_5_63 : 59;
1311 u64 active : 1;
1312 u64 reserved_2_3 : 2;
1313 u64 echoen : 1;
1314 u64 swap : 1;
1315 } s;
1316 struct cvmx_dtx_bts_ctl_s cnf75xx;
1317};
1318
1319typedef union cvmx_dtx_bts_ctl cvmx_dtx_bts_ctl_t;
1320
1321/**
1322 * cvmx_dtx_bts_dat#
1323 */
1324union cvmx_dtx_bts_datx {
1325 u64 u64;
1326 struct cvmx_dtx_bts_datx_s {
1327 u64 reserved_36_63 : 28;
1328 u64 raw : 36;
1329 } s;
1330 struct cvmx_dtx_bts_datx_s cnf75xx;
1331};
1332
1333typedef union cvmx_dtx_bts_datx cvmx_dtx_bts_datx_t;
1334
1335/**
1336 * cvmx_dtx_bts_ena#
1337 */
1338union cvmx_dtx_bts_enax {
1339 u64 u64;
1340 struct cvmx_dtx_bts_enax_s {
1341 u64 reserved_36_63 : 28;
1342 u64 ena : 36;
1343 } s;
1344 struct cvmx_dtx_bts_enax_s cnf75xx;
1345};
1346
1347typedef union cvmx_dtx_bts_enax cvmx_dtx_bts_enax_t;
1348
1349/**
1350 * cvmx_dtx_bts_sel#
1351 */
1352union cvmx_dtx_bts_selx {
1353 u64 u64;
1354 struct cvmx_dtx_bts_selx_s {
1355 u64 reserved_24_63 : 40;
1356 u64 value : 24;
1357 } s;
1358 struct cvmx_dtx_bts_selx_s cnf75xx;
1359};
1360
1361typedef union cvmx_dtx_bts_selx cvmx_dtx_bts_selx_t;
1362
1363/**
1364 * cvmx_dtx_ciu_bcst_rsp
1365 */
1366union cvmx_dtx_ciu_bcst_rsp {
1367 u64 u64;
1368 struct cvmx_dtx_ciu_bcst_rsp_s {
1369 u64 reserved_1_63 : 63;
1370 u64 ena : 1;
1371 } s;
1372 struct cvmx_dtx_ciu_bcst_rsp_s cn73xx;
1373 struct cvmx_dtx_ciu_bcst_rsp_s cn78xx;
1374 struct cvmx_dtx_ciu_bcst_rsp_s cn78xxp1;
1375 struct cvmx_dtx_ciu_bcst_rsp_s cnf75xx;
1376};
1377
1378typedef union cvmx_dtx_ciu_bcst_rsp cvmx_dtx_ciu_bcst_rsp_t;
1379
1380/**
1381 * cvmx_dtx_ciu_ctl
1382 */
1383union cvmx_dtx_ciu_ctl {
1384 u64 u64;
1385 struct cvmx_dtx_ciu_ctl_s {
1386 u64 reserved_5_63 : 59;
1387 u64 active : 1;
1388 u64 reserved_2_3 : 2;
1389 u64 echoen : 1;
1390 u64 swap : 1;
1391 } s;
1392 struct cvmx_dtx_ciu_ctl_s cn73xx;
1393 struct cvmx_dtx_ciu_ctl_s cn78xx;
1394 struct cvmx_dtx_ciu_ctl_s cn78xxp1;
1395 struct cvmx_dtx_ciu_ctl_s cnf75xx;
1396};
1397
1398typedef union cvmx_dtx_ciu_ctl cvmx_dtx_ciu_ctl_t;
1399
1400/**
1401 * cvmx_dtx_ciu_dat#
1402 */
1403union cvmx_dtx_ciu_datx {
1404 u64 u64;
1405 struct cvmx_dtx_ciu_datx_s {
1406 u64 reserved_36_63 : 28;
1407 u64 raw : 36;
1408 } s;
1409 struct cvmx_dtx_ciu_datx_s cn73xx;
1410 struct cvmx_dtx_ciu_datx_s cn78xx;
1411 struct cvmx_dtx_ciu_datx_s cn78xxp1;
1412 struct cvmx_dtx_ciu_datx_s cnf75xx;
1413};
1414
1415typedef union cvmx_dtx_ciu_datx cvmx_dtx_ciu_datx_t;
1416
1417/**
1418 * cvmx_dtx_ciu_ena#
1419 */
1420union cvmx_dtx_ciu_enax {
1421 u64 u64;
1422 struct cvmx_dtx_ciu_enax_s {
1423 u64 reserved_36_63 : 28;
1424 u64 ena : 36;
1425 } s;
1426 struct cvmx_dtx_ciu_enax_s cn73xx;
1427 struct cvmx_dtx_ciu_enax_s cn78xx;
1428 struct cvmx_dtx_ciu_enax_s cn78xxp1;
1429 struct cvmx_dtx_ciu_enax_s cnf75xx;
1430};
1431
1432typedef union cvmx_dtx_ciu_enax cvmx_dtx_ciu_enax_t;
1433
1434/**
1435 * cvmx_dtx_ciu_sel#
1436 */
1437union cvmx_dtx_ciu_selx {
1438 u64 u64;
1439 struct cvmx_dtx_ciu_selx_s {
1440 u64 reserved_24_63 : 40;
1441 u64 value : 24;
1442 } s;
1443 struct cvmx_dtx_ciu_selx_s cn73xx;
1444 struct cvmx_dtx_ciu_selx_s cn78xx;
1445 struct cvmx_dtx_ciu_selx_s cn78xxp1;
1446 struct cvmx_dtx_ciu_selx_s cnf75xx;
1447};
1448
1449typedef union cvmx_dtx_ciu_selx cvmx_dtx_ciu_selx_t;
1450
1451/**
1452 * cvmx_dtx_denc_bcst_rsp
1453 */
1454union cvmx_dtx_denc_bcst_rsp {
1455 u64 u64;
1456 struct cvmx_dtx_denc_bcst_rsp_s {
1457 u64 reserved_1_63 : 63;
1458 u64 ena : 1;
1459 } s;
1460 struct cvmx_dtx_denc_bcst_rsp_s cnf75xx;
1461};
1462
1463typedef union cvmx_dtx_denc_bcst_rsp cvmx_dtx_denc_bcst_rsp_t;
1464
1465/**
1466 * cvmx_dtx_denc_ctl
1467 */
1468union cvmx_dtx_denc_ctl {
1469 u64 u64;
1470 struct cvmx_dtx_denc_ctl_s {
1471 u64 reserved_5_63 : 59;
1472 u64 active : 1;
1473 u64 reserved_2_3 : 2;
1474 u64 echoen : 1;
1475 u64 swap : 1;
1476 } s;
1477 struct cvmx_dtx_denc_ctl_s cnf75xx;
1478};
1479
1480typedef union cvmx_dtx_denc_ctl cvmx_dtx_denc_ctl_t;
1481
1482/**
1483 * cvmx_dtx_denc_dat#
1484 */
1485union cvmx_dtx_denc_datx {
1486 u64 u64;
1487 struct cvmx_dtx_denc_datx_s {
1488 u64 reserved_36_63 : 28;
1489 u64 raw : 36;
1490 } s;
1491 struct cvmx_dtx_denc_datx_s cnf75xx;
1492};
1493
1494typedef union cvmx_dtx_denc_datx cvmx_dtx_denc_datx_t;
1495
1496/**
1497 * cvmx_dtx_denc_ena#
1498 */
1499union cvmx_dtx_denc_enax {
1500 u64 u64;
1501 struct cvmx_dtx_denc_enax_s {
1502 u64 reserved_36_63 : 28;
1503 u64 ena : 36;
1504 } s;
1505 struct cvmx_dtx_denc_enax_s cnf75xx;
1506};
1507
1508typedef union cvmx_dtx_denc_enax cvmx_dtx_denc_enax_t;
1509
1510/**
1511 * cvmx_dtx_denc_sel#
1512 */
1513union cvmx_dtx_denc_selx {
1514 u64 u64;
1515 struct cvmx_dtx_denc_selx_s {
1516 u64 reserved_24_63 : 40;
1517 u64 value : 24;
1518 } s;
1519 struct cvmx_dtx_denc_selx_s cnf75xx;
1520};
1521
1522typedef union cvmx_dtx_denc_selx cvmx_dtx_denc_selx_t;
1523
1524/**
1525 * cvmx_dtx_dfa_bcst_rsp
1526 */
1527union cvmx_dtx_dfa_bcst_rsp {
1528 u64 u64;
1529 struct cvmx_dtx_dfa_bcst_rsp_s {
1530 u64 reserved_1_63 : 63;
1531 u64 ena : 1;
1532 } s;
1533 struct cvmx_dtx_dfa_bcst_rsp_s cn70xx;
1534 struct cvmx_dtx_dfa_bcst_rsp_s cn70xxp1;
1535 struct cvmx_dtx_dfa_bcst_rsp_s cn73xx;
1536 struct cvmx_dtx_dfa_bcst_rsp_s cn78xx;
1537 struct cvmx_dtx_dfa_bcst_rsp_s cn78xxp1;
1538};
1539
1540typedef union cvmx_dtx_dfa_bcst_rsp cvmx_dtx_dfa_bcst_rsp_t;
1541
1542/**
1543 * cvmx_dtx_dfa_ctl
1544 */
1545union cvmx_dtx_dfa_ctl {
1546 u64 u64;
1547 struct cvmx_dtx_dfa_ctl_s {
1548 u64 reserved_5_63 : 59;
1549 u64 active : 1;
1550 u64 reserved_2_3 : 2;
1551 u64 echoen : 1;
1552 u64 swap : 1;
1553 } s;
1554 struct cvmx_dtx_dfa_ctl_s cn70xx;
1555 struct cvmx_dtx_dfa_ctl_s cn70xxp1;
1556 struct cvmx_dtx_dfa_ctl_s cn73xx;
1557 struct cvmx_dtx_dfa_ctl_s cn78xx;
1558 struct cvmx_dtx_dfa_ctl_s cn78xxp1;
1559};
1560
1561typedef union cvmx_dtx_dfa_ctl cvmx_dtx_dfa_ctl_t;
1562
1563/**
1564 * cvmx_dtx_dfa_dat#
1565 */
1566union cvmx_dtx_dfa_datx {
1567 u64 u64;
1568 struct cvmx_dtx_dfa_datx_s {
1569 u64 reserved_36_63 : 28;
1570 u64 raw : 36;
1571 } s;
1572 struct cvmx_dtx_dfa_datx_s cn70xx;
1573 struct cvmx_dtx_dfa_datx_s cn70xxp1;
1574 struct cvmx_dtx_dfa_datx_s cn73xx;
1575 struct cvmx_dtx_dfa_datx_s cn78xx;
1576 struct cvmx_dtx_dfa_datx_s cn78xxp1;
1577};
1578
1579typedef union cvmx_dtx_dfa_datx cvmx_dtx_dfa_datx_t;
1580
1581/**
1582 * cvmx_dtx_dfa_ena#
1583 */
1584union cvmx_dtx_dfa_enax {
1585 u64 u64;
1586 struct cvmx_dtx_dfa_enax_s {
1587 u64 reserved_36_63 : 28;
1588 u64 ena : 36;
1589 } s;
1590 struct cvmx_dtx_dfa_enax_s cn70xx;
1591 struct cvmx_dtx_dfa_enax_s cn70xxp1;
1592 struct cvmx_dtx_dfa_enax_s cn73xx;
1593 struct cvmx_dtx_dfa_enax_s cn78xx;
1594 struct cvmx_dtx_dfa_enax_s cn78xxp1;
1595};
1596
1597typedef union cvmx_dtx_dfa_enax cvmx_dtx_dfa_enax_t;
1598
1599/**
1600 * cvmx_dtx_dfa_sel#
1601 */
1602union cvmx_dtx_dfa_selx {
1603 u64 u64;
1604 struct cvmx_dtx_dfa_selx_s {
1605 u64 reserved_24_63 : 40;
1606 u64 value : 24;
1607 } s;
1608 struct cvmx_dtx_dfa_selx_s cn70xx;
1609 struct cvmx_dtx_dfa_selx_s cn70xxp1;
1610 struct cvmx_dtx_dfa_selx_s cn73xx;
1611 struct cvmx_dtx_dfa_selx_s cn78xx;
1612 struct cvmx_dtx_dfa_selx_s cn78xxp1;
1613};
1614
1615typedef union cvmx_dtx_dfa_selx cvmx_dtx_dfa_selx_t;
1616
1617/**
1618 * cvmx_dtx_dlfe_bcst_rsp
1619 */
1620union cvmx_dtx_dlfe_bcst_rsp {
1621 u64 u64;
1622 struct cvmx_dtx_dlfe_bcst_rsp_s {
1623 u64 reserved_1_63 : 63;
1624 u64 ena : 1;
1625 } s;
1626 struct cvmx_dtx_dlfe_bcst_rsp_s cnf75xx;
1627};
1628
1629typedef union cvmx_dtx_dlfe_bcst_rsp cvmx_dtx_dlfe_bcst_rsp_t;
1630
1631/**
1632 * cvmx_dtx_dlfe_ctl
1633 */
1634union cvmx_dtx_dlfe_ctl {
1635 u64 u64;
1636 struct cvmx_dtx_dlfe_ctl_s {
1637 u64 reserved_5_63 : 59;
1638 u64 active : 1;
1639 u64 reserved_2_3 : 2;
1640 u64 echoen : 1;
1641 u64 swap : 1;
1642 } s;
1643 struct cvmx_dtx_dlfe_ctl_s cnf75xx;
1644};
1645
1646typedef union cvmx_dtx_dlfe_ctl cvmx_dtx_dlfe_ctl_t;
1647
1648/**
1649 * cvmx_dtx_dlfe_dat#
1650 */
1651union cvmx_dtx_dlfe_datx {
1652 u64 u64;
1653 struct cvmx_dtx_dlfe_datx_s {
1654 u64 reserved_36_63 : 28;
1655 u64 raw : 36;
1656 } s;
1657 struct cvmx_dtx_dlfe_datx_s cnf75xx;
1658};
1659
1660typedef union cvmx_dtx_dlfe_datx cvmx_dtx_dlfe_datx_t;
1661
1662/**
1663 * cvmx_dtx_dlfe_ena#
1664 */
1665union cvmx_dtx_dlfe_enax {
1666 u64 u64;
1667 struct cvmx_dtx_dlfe_enax_s {
1668 u64 reserved_36_63 : 28;
1669 u64 ena : 36;
1670 } s;
1671 struct cvmx_dtx_dlfe_enax_s cnf75xx;
1672};
1673
1674typedef union cvmx_dtx_dlfe_enax cvmx_dtx_dlfe_enax_t;
1675
1676/**
1677 * cvmx_dtx_dlfe_sel#
1678 */
1679union cvmx_dtx_dlfe_selx {
1680 u64 u64;
1681 struct cvmx_dtx_dlfe_selx_s {
1682 u64 reserved_24_63 : 40;
1683 u64 value : 24;
1684 } s;
1685 struct cvmx_dtx_dlfe_selx_s cnf75xx;
1686};
1687
1688typedef union cvmx_dtx_dlfe_selx cvmx_dtx_dlfe_selx_t;
1689
1690/**
1691 * cvmx_dtx_dpi_bcst_rsp
1692 */
1693union cvmx_dtx_dpi_bcst_rsp {
1694 u64 u64;
1695 struct cvmx_dtx_dpi_bcst_rsp_s {
1696 u64 reserved_1_63 : 63;
1697 u64 ena : 1;
1698 } s;
1699 struct cvmx_dtx_dpi_bcst_rsp_s cn70xx;
1700 struct cvmx_dtx_dpi_bcst_rsp_s cn70xxp1;
1701 struct cvmx_dtx_dpi_bcst_rsp_s cn73xx;
1702 struct cvmx_dtx_dpi_bcst_rsp_s cn78xx;
1703 struct cvmx_dtx_dpi_bcst_rsp_s cn78xxp1;
1704 struct cvmx_dtx_dpi_bcst_rsp_s cnf75xx;
1705};
1706
1707typedef union cvmx_dtx_dpi_bcst_rsp cvmx_dtx_dpi_bcst_rsp_t;
1708
1709/**
1710 * cvmx_dtx_dpi_ctl
1711 */
1712union cvmx_dtx_dpi_ctl {
1713 u64 u64;
1714 struct cvmx_dtx_dpi_ctl_s {
1715 u64 reserved_5_63 : 59;
1716 u64 active : 1;
1717 u64 reserved_2_3 : 2;
1718 u64 echoen : 1;
1719 u64 swap : 1;
1720 } s;
1721 struct cvmx_dtx_dpi_ctl_s cn70xx;
1722 struct cvmx_dtx_dpi_ctl_s cn70xxp1;
1723 struct cvmx_dtx_dpi_ctl_s cn73xx;
1724 struct cvmx_dtx_dpi_ctl_s cn78xx;
1725 struct cvmx_dtx_dpi_ctl_s cn78xxp1;
1726 struct cvmx_dtx_dpi_ctl_s cnf75xx;
1727};
1728
1729typedef union cvmx_dtx_dpi_ctl cvmx_dtx_dpi_ctl_t;
1730
1731/**
1732 * cvmx_dtx_dpi_dat#
1733 */
1734union cvmx_dtx_dpi_datx {
1735 u64 u64;
1736 struct cvmx_dtx_dpi_datx_s {
1737 u64 reserved_36_63 : 28;
1738 u64 raw : 36;
1739 } s;
1740 struct cvmx_dtx_dpi_datx_s cn70xx;
1741 struct cvmx_dtx_dpi_datx_s cn70xxp1;
1742 struct cvmx_dtx_dpi_datx_s cn73xx;
1743 struct cvmx_dtx_dpi_datx_s cn78xx;
1744 struct cvmx_dtx_dpi_datx_s cn78xxp1;
1745 struct cvmx_dtx_dpi_datx_s cnf75xx;
1746};
1747
1748typedef union cvmx_dtx_dpi_datx cvmx_dtx_dpi_datx_t;
1749
1750/**
1751 * cvmx_dtx_dpi_ena#
1752 */
1753union cvmx_dtx_dpi_enax {
1754 u64 u64;
1755 struct cvmx_dtx_dpi_enax_s {
1756 u64 reserved_36_63 : 28;
1757 u64 ena : 36;
1758 } s;
1759 struct cvmx_dtx_dpi_enax_s cn70xx;
1760 struct cvmx_dtx_dpi_enax_s cn70xxp1;
1761 struct cvmx_dtx_dpi_enax_s cn73xx;
1762 struct cvmx_dtx_dpi_enax_s cn78xx;
1763 struct cvmx_dtx_dpi_enax_s cn78xxp1;
1764 struct cvmx_dtx_dpi_enax_s cnf75xx;
1765};
1766
1767typedef union cvmx_dtx_dpi_enax cvmx_dtx_dpi_enax_t;
1768
1769/**
1770 * cvmx_dtx_dpi_sel#
1771 */
1772union cvmx_dtx_dpi_selx {
1773 u64 u64;
1774 struct cvmx_dtx_dpi_selx_s {
1775 u64 reserved_24_63 : 40;
1776 u64 value : 24;
1777 } s;
1778 struct cvmx_dtx_dpi_selx_s cn70xx;
1779 struct cvmx_dtx_dpi_selx_s cn70xxp1;
1780 struct cvmx_dtx_dpi_selx_s cn73xx;
1781 struct cvmx_dtx_dpi_selx_s cn78xx;
1782 struct cvmx_dtx_dpi_selx_s cn78xxp1;
1783 struct cvmx_dtx_dpi_selx_s cnf75xx;
1784};
1785
1786typedef union cvmx_dtx_dpi_selx cvmx_dtx_dpi_selx_t;
1787
1788/**
1789 * cvmx_dtx_fdeq#_bcst_rsp
1790 */
1791union cvmx_dtx_fdeqx_bcst_rsp {
1792 u64 u64;
1793 struct cvmx_dtx_fdeqx_bcst_rsp_s {
1794 u64 reserved_1_63 : 63;
1795 u64 ena : 1;
1796 } s;
1797 struct cvmx_dtx_fdeqx_bcst_rsp_s cnf75xx;
1798};
1799
1800typedef union cvmx_dtx_fdeqx_bcst_rsp cvmx_dtx_fdeqx_bcst_rsp_t;
1801
1802/**
1803 * cvmx_dtx_fdeq#_ctl
1804 */
1805union cvmx_dtx_fdeqx_ctl {
1806 u64 u64;
1807 struct cvmx_dtx_fdeqx_ctl_s {
1808 u64 reserved_5_63 : 59;
1809 u64 active : 1;
1810 u64 reserved_2_3 : 2;
1811 u64 echoen : 1;
1812 u64 swap : 1;
1813 } s;
1814 struct cvmx_dtx_fdeqx_ctl_s cnf75xx;
1815};
1816
1817typedef union cvmx_dtx_fdeqx_ctl cvmx_dtx_fdeqx_ctl_t;
1818
1819/**
1820 * cvmx_dtx_fdeq#_dat#
1821 */
1822union cvmx_dtx_fdeqx_datx {
1823 u64 u64;
1824 struct cvmx_dtx_fdeqx_datx_s {
1825 u64 reserved_36_63 : 28;
1826 u64 raw : 36;
1827 } s;
1828 struct cvmx_dtx_fdeqx_datx_s cnf75xx;
1829};
1830
1831typedef union cvmx_dtx_fdeqx_datx cvmx_dtx_fdeqx_datx_t;
1832
1833/**
1834 * cvmx_dtx_fdeq#_ena#
1835 */
1836union cvmx_dtx_fdeqx_enax {
1837 u64 u64;
1838 struct cvmx_dtx_fdeqx_enax_s {
1839 u64 reserved_36_63 : 28;
1840 u64 ena : 36;
1841 } s;
1842 struct cvmx_dtx_fdeqx_enax_s cnf75xx;
1843};
1844
1845typedef union cvmx_dtx_fdeqx_enax cvmx_dtx_fdeqx_enax_t;
1846
1847/**
1848 * cvmx_dtx_fdeq#_sel#
1849 */
1850union cvmx_dtx_fdeqx_selx {
1851 u64 u64;
1852 struct cvmx_dtx_fdeqx_selx_s {
1853 u64 reserved_24_63 : 40;
1854 u64 value : 24;
1855 } s;
1856 struct cvmx_dtx_fdeqx_selx_s cnf75xx;
1857};
1858
1859typedef union cvmx_dtx_fdeqx_selx cvmx_dtx_fdeqx_selx_t;
1860
1861/**
1862 * cvmx_dtx_fpa_bcst_rsp
1863 */
1864union cvmx_dtx_fpa_bcst_rsp {
1865 u64 u64;
1866 struct cvmx_dtx_fpa_bcst_rsp_s {
1867 u64 reserved_1_63 : 63;
1868 u64 ena : 1;
1869 } s;
1870 struct cvmx_dtx_fpa_bcst_rsp_s cn70xx;
1871 struct cvmx_dtx_fpa_bcst_rsp_s cn70xxp1;
1872 struct cvmx_dtx_fpa_bcst_rsp_s cn73xx;
1873 struct cvmx_dtx_fpa_bcst_rsp_s cn78xx;
1874 struct cvmx_dtx_fpa_bcst_rsp_s cn78xxp1;
1875 struct cvmx_dtx_fpa_bcst_rsp_s cnf75xx;
1876};
1877
1878typedef union cvmx_dtx_fpa_bcst_rsp cvmx_dtx_fpa_bcst_rsp_t;
1879
1880/**
1881 * cvmx_dtx_fpa_ctl
1882 */
1883union cvmx_dtx_fpa_ctl {
1884 u64 u64;
1885 struct cvmx_dtx_fpa_ctl_s {
1886 u64 reserved_5_63 : 59;
1887 u64 active : 1;
1888 u64 reserved_2_3 : 2;
1889 u64 echoen : 1;
1890 u64 swap : 1;
1891 } s;
1892 struct cvmx_dtx_fpa_ctl_s cn70xx;
1893 struct cvmx_dtx_fpa_ctl_s cn70xxp1;
1894 struct cvmx_dtx_fpa_ctl_s cn73xx;
1895 struct cvmx_dtx_fpa_ctl_s cn78xx;
1896 struct cvmx_dtx_fpa_ctl_s cn78xxp1;
1897 struct cvmx_dtx_fpa_ctl_s cnf75xx;
1898};
1899
1900typedef union cvmx_dtx_fpa_ctl cvmx_dtx_fpa_ctl_t;
1901
1902/**
1903 * cvmx_dtx_fpa_dat#
1904 */
1905union cvmx_dtx_fpa_datx {
1906 u64 u64;
1907 struct cvmx_dtx_fpa_datx_s {
1908 u64 reserved_36_63 : 28;
1909 u64 raw : 36;
1910 } s;
1911 struct cvmx_dtx_fpa_datx_s cn70xx;
1912 struct cvmx_dtx_fpa_datx_s cn70xxp1;
1913 struct cvmx_dtx_fpa_datx_s cn73xx;
1914 struct cvmx_dtx_fpa_datx_s cn78xx;
1915 struct cvmx_dtx_fpa_datx_s cn78xxp1;
1916 struct cvmx_dtx_fpa_datx_s cnf75xx;
1917};
1918
1919typedef union cvmx_dtx_fpa_datx cvmx_dtx_fpa_datx_t;
1920
1921/**
1922 * cvmx_dtx_fpa_ena#
1923 */
1924union cvmx_dtx_fpa_enax {
1925 u64 u64;
1926 struct cvmx_dtx_fpa_enax_s {
1927 u64 reserved_36_63 : 28;
1928 u64 ena : 36;
1929 } s;
1930 struct cvmx_dtx_fpa_enax_s cn70xx;
1931 struct cvmx_dtx_fpa_enax_s cn70xxp1;
1932 struct cvmx_dtx_fpa_enax_s cn73xx;
1933 struct cvmx_dtx_fpa_enax_s cn78xx;
1934 struct cvmx_dtx_fpa_enax_s cn78xxp1;
1935 struct cvmx_dtx_fpa_enax_s cnf75xx;
1936};
1937
1938typedef union cvmx_dtx_fpa_enax cvmx_dtx_fpa_enax_t;
1939
1940/**
1941 * cvmx_dtx_fpa_sel#
1942 */
1943union cvmx_dtx_fpa_selx {
1944 u64 u64;
1945 struct cvmx_dtx_fpa_selx_s {
1946 u64 reserved_24_63 : 40;
1947 u64 value : 24;
1948 } s;
1949 struct cvmx_dtx_fpa_selx_s cn70xx;
1950 struct cvmx_dtx_fpa_selx_s cn70xxp1;
1951 struct cvmx_dtx_fpa_selx_s cn73xx;
1952 struct cvmx_dtx_fpa_selx_s cn78xx;
1953 struct cvmx_dtx_fpa_selx_s cn78xxp1;
1954 struct cvmx_dtx_fpa_selx_s cnf75xx;
1955};
1956
1957typedef union cvmx_dtx_fpa_selx cvmx_dtx_fpa_selx_t;
1958
1959/**
1960 * cvmx_dtx_gmx#_bcst_rsp
1961 */
1962union cvmx_dtx_gmxx_bcst_rsp {
1963 u64 u64;
1964 struct cvmx_dtx_gmxx_bcst_rsp_s {
1965 u64 reserved_1_63 : 63;
1966 u64 ena : 1;
1967 } s;
1968 struct cvmx_dtx_gmxx_bcst_rsp_s cn70xx;
1969 struct cvmx_dtx_gmxx_bcst_rsp_s cn70xxp1;
1970};
1971
1972typedef union cvmx_dtx_gmxx_bcst_rsp cvmx_dtx_gmxx_bcst_rsp_t;
1973
1974/**
1975 * cvmx_dtx_gmx#_ctl
1976 */
1977union cvmx_dtx_gmxx_ctl {
1978 u64 u64;
1979 struct cvmx_dtx_gmxx_ctl_s {
1980 u64 reserved_5_63 : 59;
1981 u64 active : 1;
1982 u64 reserved_2_3 : 2;
1983 u64 echoen : 1;
1984 u64 swap : 1;
1985 } s;
1986 struct cvmx_dtx_gmxx_ctl_s cn70xx;
1987 struct cvmx_dtx_gmxx_ctl_s cn70xxp1;
1988};
1989
1990typedef union cvmx_dtx_gmxx_ctl cvmx_dtx_gmxx_ctl_t;
1991
1992/**
1993 * cvmx_dtx_gmx#_dat#
1994 */
1995union cvmx_dtx_gmxx_datx {
1996 u64 u64;
1997 struct cvmx_dtx_gmxx_datx_s {
1998 u64 reserved_36_63 : 28;
1999 u64 raw : 36;
2000 } s;
2001 struct cvmx_dtx_gmxx_datx_s cn70xx;
2002 struct cvmx_dtx_gmxx_datx_s cn70xxp1;
2003};
2004
2005typedef union cvmx_dtx_gmxx_datx cvmx_dtx_gmxx_datx_t;
2006
2007/**
2008 * cvmx_dtx_gmx#_ena#
2009 */
2010union cvmx_dtx_gmxx_enax {
2011 u64 u64;
2012 struct cvmx_dtx_gmxx_enax_s {
2013 u64 reserved_36_63 : 28;
2014 u64 ena : 36;
2015 } s;
2016 struct cvmx_dtx_gmxx_enax_s cn70xx;
2017 struct cvmx_dtx_gmxx_enax_s cn70xxp1;
2018};
2019
2020typedef union cvmx_dtx_gmxx_enax cvmx_dtx_gmxx_enax_t;
2021
2022/**
2023 * cvmx_dtx_gmx#_sel#
2024 */
2025union cvmx_dtx_gmxx_selx {
2026 u64 u64;
2027 struct cvmx_dtx_gmxx_selx_s {
2028 u64 reserved_24_63 : 40;
2029 u64 value : 24;
2030 } s;
2031 struct cvmx_dtx_gmxx_selx_s cn70xx;
2032 struct cvmx_dtx_gmxx_selx_s cn70xxp1;
2033};
2034
2035typedef union cvmx_dtx_gmxx_selx cvmx_dtx_gmxx_selx_t;
2036
2037/**
2038 * cvmx_dtx_gser#_bcst_rsp
2039 */
2040union cvmx_dtx_gserx_bcst_rsp {
2041 u64 u64;
2042 struct cvmx_dtx_gserx_bcst_rsp_s {
2043 u64 reserved_1_63 : 63;
2044 u64 ena : 1;
2045 } s;
2046 struct cvmx_dtx_gserx_bcst_rsp_s cn73xx;
2047 struct cvmx_dtx_gserx_bcst_rsp_s cn78xx;
2048 struct cvmx_dtx_gserx_bcst_rsp_s cn78xxp1;
2049 struct cvmx_dtx_gserx_bcst_rsp_s cnf75xx;
2050};
2051
2052typedef union cvmx_dtx_gserx_bcst_rsp cvmx_dtx_gserx_bcst_rsp_t;
2053
2054/**
2055 * cvmx_dtx_gser#_ctl
2056 */
2057union cvmx_dtx_gserx_ctl {
2058 u64 u64;
2059 struct cvmx_dtx_gserx_ctl_s {
2060 u64 reserved_5_63 : 59;
2061 u64 active : 1;
2062 u64 reserved_2_3 : 2;
2063 u64 echoen : 1;
2064 u64 swap : 1;
2065 } s;
2066 struct cvmx_dtx_gserx_ctl_s cn73xx;
2067 struct cvmx_dtx_gserx_ctl_s cn78xx;
2068 struct cvmx_dtx_gserx_ctl_s cn78xxp1;
2069 struct cvmx_dtx_gserx_ctl_s cnf75xx;
2070};
2071
2072typedef union cvmx_dtx_gserx_ctl cvmx_dtx_gserx_ctl_t;
2073
2074/**
2075 * cvmx_dtx_gser#_dat#
2076 */
2077union cvmx_dtx_gserx_datx {
2078 u64 u64;
2079 struct cvmx_dtx_gserx_datx_s {
2080 u64 reserved_36_63 : 28;
2081 u64 raw : 36;
2082 } s;
2083 struct cvmx_dtx_gserx_datx_s cn73xx;
2084 struct cvmx_dtx_gserx_datx_s cn78xx;
2085 struct cvmx_dtx_gserx_datx_s cn78xxp1;
2086 struct cvmx_dtx_gserx_datx_s cnf75xx;
2087};
2088
2089typedef union cvmx_dtx_gserx_datx cvmx_dtx_gserx_datx_t;
2090
2091/**
2092 * cvmx_dtx_gser#_ena#
2093 */
2094union cvmx_dtx_gserx_enax {
2095 u64 u64;
2096 struct cvmx_dtx_gserx_enax_s {
2097 u64 reserved_36_63 : 28;
2098 u64 ena : 36;
2099 } s;
2100 struct cvmx_dtx_gserx_enax_s cn73xx;
2101 struct cvmx_dtx_gserx_enax_s cn78xx;
2102 struct cvmx_dtx_gserx_enax_s cn78xxp1;
2103 struct cvmx_dtx_gserx_enax_s cnf75xx;
2104};
2105
2106typedef union cvmx_dtx_gserx_enax cvmx_dtx_gserx_enax_t;
2107
2108/**
2109 * cvmx_dtx_gser#_sel#
2110 */
2111union cvmx_dtx_gserx_selx {
2112 u64 u64;
2113 struct cvmx_dtx_gserx_selx_s {
2114 u64 reserved_24_63 : 40;
2115 u64 value : 24;
2116 } s;
2117 struct cvmx_dtx_gserx_selx_s cn73xx;
2118 struct cvmx_dtx_gserx_selx_s cn78xx;
2119 struct cvmx_dtx_gserx_selx_s cn78xxp1;
2120 struct cvmx_dtx_gserx_selx_s cnf75xx;
2121};
2122
2123typedef union cvmx_dtx_gserx_selx cvmx_dtx_gserx_selx_t;
2124
2125/**
2126 * cvmx_dtx_hna_bcst_rsp
2127 */
2128union cvmx_dtx_hna_bcst_rsp {
2129 u64 u64;
2130 struct cvmx_dtx_hna_bcst_rsp_s {
2131 u64 reserved_1_63 : 63;
2132 u64 ena : 1;
2133 } s;
2134 struct cvmx_dtx_hna_bcst_rsp_s cn73xx;
2135 struct cvmx_dtx_hna_bcst_rsp_s cn78xx;
2136 struct cvmx_dtx_hna_bcst_rsp_s cn78xxp1;
2137};
2138
2139typedef union cvmx_dtx_hna_bcst_rsp cvmx_dtx_hna_bcst_rsp_t;
2140
2141/**
2142 * cvmx_dtx_hna_ctl
2143 */
2144union cvmx_dtx_hna_ctl {
2145 u64 u64;
2146 struct cvmx_dtx_hna_ctl_s {
2147 u64 reserved_5_63 : 59;
2148 u64 active : 1;
2149 u64 reserved_2_3 : 2;
2150 u64 echoen : 1;
2151 u64 swap : 1;
2152 } s;
2153 struct cvmx_dtx_hna_ctl_s cn73xx;
2154 struct cvmx_dtx_hna_ctl_s cn78xx;
2155 struct cvmx_dtx_hna_ctl_s cn78xxp1;
2156};
2157
2158typedef union cvmx_dtx_hna_ctl cvmx_dtx_hna_ctl_t;
2159
2160/**
2161 * cvmx_dtx_hna_dat#
2162 */
2163union cvmx_dtx_hna_datx {
2164 u64 u64;
2165 struct cvmx_dtx_hna_datx_s {
2166 u64 reserved_36_63 : 28;
2167 u64 raw : 36;
2168 } s;
2169 struct cvmx_dtx_hna_datx_s cn73xx;
2170 struct cvmx_dtx_hna_datx_s cn78xx;
2171 struct cvmx_dtx_hna_datx_s cn78xxp1;
2172};
2173
2174typedef union cvmx_dtx_hna_datx cvmx_dtx_hna_datx_t;
2175
2176/**
2177 * cvmx_dtx_hna_ena#
2178 */
2179union cvmx_dtx_hna_enax {
2180 u64 u64;
2181 struct cvmx_dtx_hna_enax_s {
2182 u64 reserved_36_63 : 28;
2183 u64 ena : 36;
2184 } s;
2185 struct cvmx_dtx_hna_enax_s cn73xx;
2186 struct cvmx_dtx_hna_enax_s cn78xx;
2187 struct cvmx_dtx_hna_enax_s cn78xxp1;
2188};
2189
2190typedef union cvmx_dtx_hna_enax cvmx_dtx_hna_enax_t;
2191
2192/**
2193 * cvmx_dtx_hna_sel#
2194 */
2195union cvmx_dtx_hna_selx {
2196 u64 u64;
2197 struct cvmx_dtx_hna_selx_s {
2198 u64 reserved_24_63 : 40;
2199 u64 value : 24;
2200 } s;
2201 struct cvmx_dtx_hna_selx_s cn73xx;
2202 struct cvmx_dtx_hna_selx_s cn78xx;
2203 struct cvmx_dtx_hna_selx_s cn78xxp1;
2204};
2205
2206typedef union cvmx_dtx_hna_selx cvmx_dtx_hna_selx_t;
2207
2208/**
2209 * cvmx_dtx_ila_bcst_rsp
2210 */
2211union cvmx_dtx_ila_bcst_rsp {
2212 u64 u64;
2213 struct cvmx_dtx_ila_bcst_rsp_s {
2214 u64 reserved_1_63 : 63;
2215 u64 ena : 1;
2216 } s;
2217 struct cvmx_dtx_ila_bcst_rsp_s cn78xx;
2218 struct cvmx_dtx_ila_bcst_rsp_s cn78xxp1;
2219};
2220
2221typedef union cvmx_dtx_ila_bcst_rsp cvmx_dtx_ila_bcst_rsp_t;
2222
2223/**
2224 * cvmx_dtx_ila_ctl
2225 */
2226union cvmx_dtx_ila_ctl {
2227 u64 u64;
2228 struct cvmx_dtx_ila_ctl_s {
2229 u64 reserved_5_63 : 59;
2230 u64 active : 1;
2231 u64 reserved_2_3 : 2;
2232 u64 echoen : 1;
2233 u64 swap : 1;
2234 } s;
2235 struct cvmx_dtx_ila_ctl_s cn78xx;
2236 struct cvmx_dtx_ila_ctl_s cn78xxp1;
2237};
2238
2239typedef union cvmx_dtx_ila_ctl cvmx_dtx_ila_ctl_t;
2240
2241/**
2242 * cvmx_dtx_ila_dat#
2243 */
2244union cvmx_dtx_ila_datx {
2245 u64 u64;
2246 struct cvmx_dtx_ila_datx_s {
2247 u64 reserved_36_63 : 28;
2248 u64 raw : 36;
2249 } s;
2250 struct cvmx_dtx_ila_datx_s cn78xx;
2251 struct cvmx_dtx_ila_datx_s cn78xxp1;
2252};
2253
2254typedef union cvmx_dtx_ila_datx cvmx_dtx_ila_datx_t;
2255
2256/**
2257 * cvmx_dtx_ila_ena#
2258 */
2259union cvmx_dtx_ila_enax {
2260 u64 u64;
2261 struct cvmx_dtx_ila_enax_s {
2262 u64 reserved_36_63 : 28;
2263 u64 ena : 36;
2264 } s;
2265 struct cvmx_dtx_ila_enax_s cn78xx;
2266 struct cvmx_dtx_ila_enax_s cn78xxp1;
2267};
2268
2269typedef union cvmx_dtx_ila_enax cvmx_dtx_ila_enax_t;
2270
2271/**
2272 * cvmx_dtx_ila_sel#
2273 */
2274union cvmx_dtx_ila_selx {
2275 u64 u64;
2276 struct cvmx_dtx_ila_selx_s {
2277 u64 reserved_24_63 : 40;
2278 u64 value : 24;
2279 } s;
2280 struct cvmx_dtx_ila_selx_s cn78xx;
2281 struct cvmx_dtx_ila_selx_s cn78xxp1;
2282};
2283
2284typedef union cvmx_dtx_ila_selx cvmx_dtx_ila_selx_t;
2285
2286/**
2287 * cvmx_dtx_ilk_bcst_rsp
2288 */
2289union cvmx_dtx_ilk_bcst_rsp {
2290 u64 u64;
2291 struct cvmx_dtx_ilk_bcst_rsp_s {
2292 u64 reserved_1_63 : 63;
2293 u64 ena : 1;
2294 } s;
2295 struct cvmx_dtx_ilk_bcst_rsp_s cn78xx;
2296 struct cvmx_dtx_ilk_bcst_rsp_s cn78xxp1;
2297};
2298
2299typedef union cvmx_dtx_ilk_bcst_rsp cvmx_dtx_ilk_bcst_rsp_t;
2300
2301/**
2302 * cvmx_dtx_ilk_ctl
2303 */
2304union cvmx_dtx_ilk_ctl {
2305 u64 u64;
2306 struct cvmx_dtx_ilk_ctl_s {
2307 u64 reserved_5_63 : 59;
2308 u64 active : 1;
2309 u64 reserved_2_3 : 2;
2310 u64 echoen : 1;
2311 u64 swap : 1;
2312 } s;
2313 struct cvmx_dtx_ilk_ctl_s cn78xx;
2314 struct cvmx_dtx_ilk_ctl_s cn78xxp1;
2315};
2316
2317typedef union cvmx_dtx_ilk_ctl cvmx_dtx_ilk_ctl_t;
2318
2319/**
2320 * cvmx_dtx_ilk_dat#
2321 */
2322union cvmx_dtx_ilk_datx {
2323 u64 u64;
2324 struct cvmx_dtx_ilk_datx_s {
2325 u64 reserved_36_63 : 28;
2326 u64 raw : 36;
2327 } s;
2328 struct cvmx_dtx_ilk_datx_s cn78xx;
2329 struct cvmx_dtx_ilk_datx_s cn78xxp1;
2330};
2331
2332typedef union cvmx_dtx_ilk_datx cvmx_dtx_ilk_datx_t;
2333
2334/**
2335 * cvmx_dtx_ilk_ena#
2336 */
2337union cvmx_dtx_ilk_enax {
2338 u64 u64;
2339 struct cvmx_dtx_ilk_enax_s {
2340 u64 reserved_36_63 : 28;
2341 u64 ena : 36;
2342 } s;
2343 struct cvmx_dtx_ilk_enax_s cn78xx;
2344 struct cvmx_dtx_ilk_enax_s cn78xxp1;
2345};
2346
2347typedef union cvmx_dtx_ilk_enax cvmx_dtx_ilk_enax_t;
2348
2349/**
2350 * cvmx_dtx_ilk_sel#
2351 */
2352union cvmx_dtx_ilk_selx {
2353 u64 u64;
2354 struct cvmx_dtx_ilk_selx_s {
2355 u64 reserved_24_63 : 40;
2356 u64 value : 24;
2357 } s;
2358 struct cvmx_dtx_ilk_selx_s cn78xx;
2359 struct cvmx_dtx_ilk_selx_s cn78xxp1;
2360};
2361
2362typedef union cvmx_dtx_ilk_selx cvmx_dtx_ilk_selx_t;
2363
2364/**
2365 * cvmx_dtx_iob_bcst_rsp
2366 */
2367union cvmx_dtx_iob_bcst_rsp {
2368 u64 u64;
2369 struct cvmx_dtx_iob_bcst_rsp_s {
2370 u64 reserved_1_63 : 63;
2371 u64 ena : 1;
2372 } s;
2373 struct cvmx_dtx_iob_bcst_rsp_s cn70xx;
2374 struct cvmx_dtx_iob_bcst_rsp_s cn70xxp1;
2375};
2376
2377typedef union cvmx_dtx_iob_bcst_rsp cvmx_dtx_iob_bcst_rsp_t;
2378
2379/**
2380 * cvmx_dtx_iob_ctl
2381 */
2382union cvmx_dtx_iob_ctl {
2383 u64 u64;
2384 struct cvmx_dtx_iob_ctl_s {
2385 u64 reserved_5_63 : 59;
2386 u64 active : 1;
2387 u64 reserved_2_3 : 2;
2388 u64 echoen : 1;
2389 u64 swap : 1;
2390 } s;
2391 struct cvmx_dtx_iob_ctl_s cn70xx;
2392 struct cvmx_dtx_iob_ctl_s cn70xxp1;
2393};
2394
2395typedef union cvmx_dtx_iob_ctl cvmx_dtx_iob_ctl_t;
2396
2397/**
2398 * cvmx_dtx_iob_dat#
2399 */
2400union cvmx_dtx_iob_datx {
2401 u64 u64;
2402 struct cvmx_dtx_iob_datx_s {
2403 u64 reserved_36_63 : 28;
2404 u64 raw : 36;
2405 } s;
2406 struct cvmx_dtx_iob_datx_s cn70xx;
2407 struct cvmx_dtx_iob_datx_s cn70xxp1;
2408};
2409
2410typedef union cvmx_dtx_iob_datx cvmx_dtx_iob_datx_t;
2411
2412/**
2413 * cvmx_dtx_iob_ena#
2414 */
2415union cvmx_dtx_iob_enax {
2416 u64 u64;
2417 struct cvmx_dtx_iob_enax_s {
2418 u64 reserved_36_63 : 28;
2419 u64 ena : 36;
2420 } s;
2421 struct cvmx_dtx_iob_enax_s cn70xx;
2422 struct cvmx_dtx_iob_enax_s cn70xxp1;
2423};
2424
2425typedef union cvmx_dtx_iob_enax cvmx_dtx_iob_enax_t;
2426
2427/**
2428 * cvmx_dtx_iob_sel#
2429 */
2430union cvmx_dtx_iob_selx {
2431 u64 u64;
2432 struct cvmx_dtx_iob_selx_s {
2433 u64 reserved_24_63 : 40;
2434 u64 value : 24;
2435 } s;
2436 struct cvmx_dtx_iob_selx_s cn70xx;
2437 struct cvmx_dtx_iob_selx_s cn70xxp1;
2438};
2439
2440typedef union cvmx_dtx_iob_selx cvmx_dtx_iob_selx_t;
2441
2442/**
2443 * cvmx_dtx_iobn_bcst_rsp
2444 */
2445union cvmx_dtx_iobn_bcst_rsp {
2446 u64 u64;
2447 struct cvmx_dtx_iobn_bcst_rsp_s {
2448 u64 reserved_1_63 : 63;
2449 u64 ena : 1;
2450 } s;
2451 struct cvmx_dtx_iobn_bcst_rsp_s cn73xx;
2452 struct cvmx_dtx_iobn_bcst_rsp_s cn78xx;
2453 struct cvmx_dtx_iobn_bcst_rsp_s cn78xxp1;
2454 struct cvmx_dtx_iobn_bcst_rsp_s cnf75xx;
2455};
2456
2457typedef union cvmx_dtx_iobn_bcst_rsp cvmx_dtx_iobn_bcst_rsp_t;
2458
2459/**
2460 * cvmx_dtx_iobn_ctl
2461 */
2462union cvmx_dtx_iobn_ctl {
2463 u64 u64;
2464 struct cvmx_dtx_iobn_ctl_s {
2465 u64 reserved_5_63 : 59;
2466 u64 active : 1;
2467 u64 reserved_2_3 : 2;
2468 u64 echoen : 1;
2469 u64 swap : 1;
2470 } s;
2471 struct cvmx_dtx_iobn_ctl_s cn73xx;
2472 struct cvmx_dtx_iobn_ctl_s cn78xx;
2473 struct cvmx_dtx_iobn_ctl_s cn78xxp1;
2474 struct cvmx_dtx_iobn_ctl_s cnf75xx;
2475};
2476
2477typedef union cvmx_dtx_iobn_ctl cvmx_dtx_iobn_ctl_t;
2478
2479/**
2480 * cvmx_dtx_iobn_dat#
2481 */
2482union cvmx_dtx_iobn_datx {
2483 u64 u64;
2484 struct cvmx_dtx_iobn_datx_s {
2485 u64 reserved_36_63 : 28;
2486 u64 raw : 36;
2487 } s;
2488 struct cvmx_dtx_iobn_datx_s cn73xx;
2489 struct cvmx_dtx_iobn_datx_s cn78xx;
2490 struct cvmx_dtx_iobn_datx_s cn78xxp1;
2491 struct cvmx_dtx_iobn_datx_s cnf75xx;
2492};
2493
2494typedef union cvmx_dtx_iobn_datx cvmx_dtx_iobn_datx_t;
2495
2496/**
2497 * cvmx_dtx_iobn_ena#
2498 */
2499union cvmx_dtx_iobn_enax {
2500 u64 u64;
2501 struct cvmx_dtx_iobn_enax_s {
2502 u64 reserved_36_63 : 28;
2503 u64 ena : 36;
2504 } s;
2505 struct cvmx_dtx_iobn_enax_s cn73xx;
2506 struct cvmx_dtx_iobn_enax_s cn78xx;
2507 struct cvmx_dtx_iobn_enax_s cn78xxp1;
2508 struct cvmx_dtx_iobn_enax_s cnf75xx;
2509};
2510
2511typedef union cvmx_dtx_iobn_enax cvmx_dtx_iobn_enax_t;
2512
2513/**
2514 * cvmx_dtx_iobn_sel#
2515 */
2516union cvmx_dtx_iobn_selx {
2517 u64 u64;
2518 struct cvmx_dtx_iobn_selx_s {
2519 u64 reserved_24_63 : 40;
2520 u64 value : 24;
2521 } s;
2522 struct cvmx_dtx_iobn_selx_s cn73xx;
2523 struct cvmx_dtx_iobn_selx_s cn78xx;
2524 struct cvmx_dtx_iobn_selx_s cn78xxp1;
2525 struct cvmx_dtx_iobn_selx_s cnf75xx;
2526};
2527
2528typedef union cvmx_dtx_iobn_selx cvmx_dtx_iobn_selx_t;
2529
2530/**
2531 * cvmx_dtx_iobp_bcst_rsp
2532 */
2533union cvmx_dtx_iobp_bcst_rsp {
2534 u64 u64;
2535 struct cvmx_dtx_iobp_bcst_rsp_s {
2536 u64 reserved_1_63 : 63;
2537 u64 ena : 1;
2538 } s;
2539 struct cvmx_dtx_iobp_bcst_rsp_s cn73xx;
2540 struct cvmx_dtx_iobp_bcst_rsp_s cn78xx;
2541 struct cvmx_dtx_iobp_bcst_rsp_s cn78xxp1;
2542 struct cvmx_dtx_iobp_bcst_rsp_s cnf75xx;
2543};
2544
2545typedef union cvmx_dtx_iobp_bcst_rsp cvmx_dtx_iobp_bcst_rsp_t;
2546
2547/**
2548 * cvmx_dtx_iobp_ctl
2549 */
2550union cvmx_dtx_iobp_ctl {
2551 u64 u64;
2552 struct cvmx_dtx_iobp_ctl_s {
2553 u64 reserved_5_63 : 59;
2554 u64 active : 1;
2555 u64 reserved_2_3 : 2;
2556 u64 echoen : 1;
2557 u64 swap : 1;
2558 } s;
2559 struct cvmx_dtx_iobp_ctl_s cn73xx;
2560 struct cvmx_dtx_iobp_ctl_s cn78xx;
2561 struct cvmx_dtx_iobp_ctl_s cn78xxp1;
2562 struct cvmx_dtx_iobp_ctl_s cnf75xx;
2563};
2564
2565typedef union cvmx_dtx_iobp_ctl cvmx_dtx_iobp_ctl_t;
2566
2567/**
2568 * cvmx_dtx_iobp_dat#
2569 */
2570union cvmx_dtx_iobp_datx {
2571 u64 u64;
2572 struct cvmx_dtx_iobp_datx_s {
2573 u64 reserved_36_63 : 28;
2574 u64 raw : 36;
2575 } s;
2576 struct cvmx_dtx_iobp_datx_s cn73xx;
2577 struct cvmx_dtx_iobp_datx_s cn78xx;
2578 struct cvmx_dtx_iobp_datx_s cn78xxp1;
2579 struct cvmx_dtx_iobp_datx_s cnf75xx;
2580};
2581
2582typedef union cvmx_dtx_iobp_datx cvmx_dtx_iobp_datx_t;
2583
2584/**
2585 * cvmx_dtx_iobp_ena#
2586 */
2587union cvmx_dtx_iobp_enax {
2588 u64 u64;
2589 struct cvmx_dtx_iobp_enax_s {
2590 u64 reserved_36_63 : 28;
2591 u64 ena : 36;
2592 } s;
2593 struct cvmx_dtx_iobp_enax_s cn73xx;
2594 struct cvmx_dtx_iobp_enax_s cn78xx;
2595 struct cvmx_dtx_iobp_enax_s cn78xxp1;
2596 struct cvmx_dtx_iobp_enax_s cnf75xx;
2597};
2598
2599typedef union cvmx_dtx_iobp_enax cvmx_dtx_iobp_enax_t;
2600
2601/**
2602 * cvmx_dtx_iobp_sel#
2603 */
2604union cvmx_dtx_iobp_selx {
2605 u64 u64;
2606 struct cvmx_dtx_iobp_selx_s {
2607 u64 reserved_24_63 : 40;
2608 u64 value : 24;
2609 } s;
2610 struct cvmx_dtx_iobp_selx_s cn73xx;
2611 struct cvmx_dtx_iobp_selx_s cn78xx;
2612 struct cvmx_dtx_iobp_selx_s cn78xxp1;
2613 struct cvmx_dtx_iobp_selx_s cnf75xx;
2614};
2615
2616typedef union cvmx_dtx_iobp_selx cvmx_dtx_iobp_selx_t;
2617
2618/**
2619 * cvmx_dtx_ipd_bcst_rsp
2620 */
2621union cvmx_dtx_ipd_bcst_rsp {
2622 u64 u64;
2623 struct cvmx_dtx_ipd_bcst_rsp_s {
2624 u64 reserved_1_63 : 63;
2625 u64 ena : 1;
2626 } s;
2627 struct cvmx_dtx_ipd_bcst_rsp_s cn70xx;
2628 struct cvmx_dtx_ipd_bcst_rsp_s cn70xxp1;
2629};
2630
2631typedef union cvmx_dtx_ipd_bcst_rsp cvmx_dtx_ipd_bcst_rsp_t;
2632
2633/**
2634 * cvmx_dtx_ipd_ctl
2635 */
2636union cvmx_dtx_ipd_ctl {
2637 u64 u64;
2638 struct cvmx_dtx_ipd_ctl_s {
2639 u64 reserved_5_63 : 59;
2640 u64 active : 1;
2641 u64 reserved_2_3 : 2;
2642 u64 echoen : 1;
2643 u64 swap : 1;
2644 } s;
2645 struct cvmx_dtx_ipd_ctl_s cn70xx;
2646 struct cvmx_dtx_ipd_ctl_s cn70xxp1;
2647};
2648
2649typedef union cvmx_dtx_ipd_ctl cvmx_dtx_ipd_ctl_t;
2650
2651/**
2652 * cvmx_dtx_ipd_dat#
2653 */
2654union cvmx_dtx_ipd_datx {
2655 u64 u64;
2656 struct cvmx_dtx_ipd_datx_s {
2657 u64 reserved_36_63 : 28;
2658 u64 raw : 36;
2659 } s;
2660 struct cvmx_dtx_ipd_datx_s cn70xx;
2661 struct cvmx_dtx_ipd_datx_s cn70xxp1;
2662};
2663
2664typedef union cvmx_dtx_ipd_datx cvmx_dtx_ipd_datx_t;
2665
2666/**
2667 * cvmx_dtx_ipd_ena#
2668 */
2669union cvmx_dtx_ipd_enax {
2670 u64 u64;
2671 struct cvmx_dtx_ipd_enax_s {
2672 u64 reserved_36_63 : 28;
2673 u64 ena : 36;
2674 } s;
2675 struct cvmx_dtx_ipd_enax_s cn70xx;
2676 struct cvmx_dtx_ipd_enax_s cn70xxp1;
2677};
2678
2679typedef union cvmx_dtx_ipd_enax cvmx_dtx_ipd_enax_t;
2680
2681/**
2682 * cvmx_dtx_ipd_sel#
2683 */
2684union cvmx_dtx_ipd_selx {
2685 u64 u64;
2686 struct cvmx_dtx_ipd_selx_s {
2687 u64 reserved_24_63 : 40;
2688 u64 value : 24;
2689 } s;
2690 struct cvmx_dtx_ipd_selx_s cn70xx;
2691 struct cvmx_dtx_ipd_selx_s cn70xxp1;
2692};
2693
2694typedef union cvmx_dtx_ipd_selx cvmx_dtx_ipd_selx_t;
2695
2696/**
2697 * cvmx_dtx_key_bcst_rsp
2698 */
2699union cvmx_dtx_key_bcst_rsp {
2700 u64 u64;
2701 struct cvmx_dtx_key_bcst_rsp_s {
2702 u64 reserved_1_63 : 63;
2703 u64 ena : 1;
2704 } s;
2705 struct cvmx_dtx_key_bcst_rsp_s cn70xx;
2706 struct cvmx_dtx_key_bcst_rsp_s cn70xxp1;
2707 struct cvmx_dtx_key_bcst_rsp_s cn73xx;
2708 struct cvmx_dtx_key_bcst_rsp_s cn78xx;
2709 struct cvmx_dtx_key_bcst_rsp_s cn78xxp1;
2710 struct cvmx_dtx_key_bcst_rsp_s cnf75xx;
2711};
2712
2713typedef union cvmx_dtx_key_bcst_rsp cvmx_dtx_key_bcst_rsp_t;
2714
2715/**
2716 * cvmx_dtx_key_ctl
2717 */
2718union cvmx_dtx_key_ctl {
2719 u64 u64;
2720 struct cvmx_dtx_key_ctl_s {
2721 u64 reserved_5_63 : 59;
2722 u64 active : 1;
2723 u64 reserved_2_3 : 2;
2724 u64 echoen : 1;
2725 u64 swap : 1;
2726 } s;
2727 struct cvmx_dtx_key_ctl_s cn70xx;
2728 struct cvmx_dtx_key_ctl_s cn70xxp1;
2729 struct cvmx_dtx_key_ctl_s cn73xx;
2730 struct cvmx_dtx_key_ctl_s cn78xx;
2731 struct cvmx_dtx_key_ctl_s cn78xxp1;
2732 struct cvmx_dtx_key_ctl_s cnf75xx;
2733};
2734
2735typedef union cvmx_dtx_key_ctl cvmx_dtx_key_ctl_t;
2736
2737/**
2738 * cvmx_dtx_key_dat#
2739 */
2740union cvmx_dtx_key_datx {
2741 u64 u64;
2742 struct cvmx_dtx_key_datx_s {
2743 u64 reserved_36_63 : 28;
2744 u64 raw : 36;
2745 } s;
2746 struct cvmx_dtx_key_datx_s cn70xx;
2747 struct cvmx_dtx_key_datx_s cn70xxp1;
2748 struct cvmx_dtx_key_datx_s cn73xx;
2749 struct cvmx_dtx_key_datx_s cn78xx;
2750 struct cvmx_dtx_key_datx_s cn78xxp1;
2751 struct cvmx_dtx_key_datx_s cnf75xx;
2752};
2753
2754typedef union cvmx_dtx_key_datx cvmx_dtx_key_datx_t;
2755
2756/**
2757 * cvmx_dtx_key_ena#
2758 */
2759union cvmx_dtx_key_enax {
2760 u64 u64;
2761 struct cvmx_dtx_key_enax_s {
2762 u64 reserved_36_63 : 28;
2763 u64 ena : 36;
2764 } s;
2765 struct cvmx_dtx_key_enax_s cn70xx;
2766 struct cvmx_dtx_key_enax_s cn70xxp1;
2767 struct cvmx_dtx_key_enax_s cn73xx;
2768 struct cvmx_dtx_key_enax_s cn78xx;
2769 struct cvmx_dtx_key_enax_s cn78xxp1;
2770 struct cvmx_dtx_key_enax_s cnf75xx;
2771};
2772
2773typedef union cvmx_dtx_key_enax cvmx_dtx_key_enax_t;
2774
2775/**
2776 * cvmx_dtx_key_sel#
2777 */
2778union cvmx_dtx_key_selx {
2779 u64 u64;
2780 struct cvmx_dtx_key_selx_s {
2781 u64 reserved_24_63 : 40;
2782 u64 value : 24;
2783 } s;
2784 struct cvmx_dtx_key_selx_s cn70xx;
2785 struct cvmx_dtx_key_selx_s cn70xxp1;
2786 struct cvmx_dtx_key_selx_s cn73xx;
2787 struct cvmx_dtx_key_selx_s cn78xx;
2788 struct cvmx_dtx_key_selx_s cn78xxp1;
2789 struct cvmx_dtx_key_selx_s cnf75xx;
2790};
2791
2792typedef union cvmx_dtx_key_selx cvmx_dtx_key_selx_t;
2793
2794/**
2795 * cvmx_dtx_l2c_cbc#_bcst_rsp
2796 */
2797union cvmx_dtx_l2c_cbcx_bcst_rsp {
2798 u64 u64;
2799 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s {
2800 u64 reserved_1_63 : 63;
2801 u64 ena : 1;
2802 } s;
2803 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn70xx;
2804 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn70xxp1;
2805 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn73xx;
2806 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn78xx;
2807 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s cn78xxp1;
2808 struct cvmx_dtx_l2c_cbcx_bcst_rsp_s cnf75xx;
2809};
2810
2811typedef union cvmx_dtx_l2c_cbcx_bcst_rsp cvmx_dtx_l2c_cbcx_bcst_rsp_t;
2812
2813/**
2814 * cvmx_dtx_l2c_cbc#_ctl
2815 */
2816union cvmx_dtx_l2c_cbcx_ctl {
2817 u64 u64;
2818 struct cvmx_dtx_l2c_cbcx_ctl_s {
2819 u64 reserved_5_63 : 59;
2820 u64 active : 1;
2821 u64 reserved_2_3 : 2;
2822 u64 echoen : 1;
2823 u64 swap : 1;
2824 } s;
2825 struct cvmx_dtx_l2c_cbcx_ctl_s cn70xx;
2826 struct cvmx_dtx_l2c_cbcx_ctl_s cn70xxp1;
2827 struct cvmx_dtx_l2c_cbcx_ctl_s cn73xx;
2828 struct cvmx_dtx_l2c_cbcx_ctl_s cn78xx;
2829 struct cvmx_dtx_l2c_cbcx_ctl_s cn78xxp1;
2830 struct cvmx_dtx_l2c_cbcx_ctl_s cnf75xx;
2831};
2832
2833typedef union cvmx_dtx_l2c_cbcx_ctl cvmx_dtx_l2c_cbcx_ctl_t;
2834
2835/**
2836 * cvmx_dtx_l2c_cbc#_dat#
2837 */
2838union cvmx_dtx_l2c_cbcx_datx {
2839 u64 u64;
2840 struct cvmx_dtx_l2c_cbcx_datx_s {
2841 u64 reserved_36_63 : 28;
2842 u64 raw : 36;
2843 } s;
2844 struct cvmx_dtx_l2c_cbcx_datx_s cn70xx;
2845 struct cvmx_dtx_l2c_cbcx_datx_s cn70xxp1;
2846 struct cvmx_dtx_l2c_cbcx_datx_s cn73xx;
2847 struct cvmx_dtx_l2c_cbcx_datx_s cn78xx;
2848 struct cvmx_dtx_l2c_cbcx_datx_s cn78xxp1;
2849 struct cvmx_dtx_l2c_cbcx_datx_s cnf75xx;
2850};
2851
2852typedef union cvmx_dtx_l2c_cbcx_datx cvmx_dtx_l2c_cbcx_datx_t;
2853
2854/**
2855 * cvmx_dtx_l2c_cbc#_ena#
2856 */
2857union cvmx_dtx_l2c_cbcx_enax {
2858 u64 u64;
2859 struct cvmx_dtx_l2c_cbcx_enax_s {
2860 u64 reserved_36_63 : 28;
2861 u64 ena : 36;
2862 } s;
2863 struct cvmx_dtx_l2c_cbcx_enax_s cn70xx;
2864 struct cvmx_dtx_l2c_cbcx_enax_s cn70xxp1;
2865 struct cvmx_dtx_l2c_cbcx_enax_s cn73xx;
2866 struct cvmx_dtx_l2c_cbcx_enax_s cn78xx;
2867 struct cvmx_dtx_l2c_cbcx_enax_s cn78xxp1;
2868 struct cvmx_dtx_l2c_cbcx_enax_s cnf75xx;
2869};
2870
2871typedef union cvmx_dtx_l2c_cbcx_enax cvmx_dtx_l2c_cbcx_enax_t;
2872
2873/**
2874 * cvmx_dtx_l2c_cbc#_sel#
2875 */
2876union cvmx_dtx_l2c_cbcx_selx {
2877 u64 u64;
2878 struct cvmx_dtx_l2c_cbcx_selx_s {
2879 u64 reserved_24_63 : 40;
2880 u64 value : 24;
2881 } s;
2882 struct cvmx_dtx_l2c_cbcx_selx_s cn70xx;
2883 struct cvmx_dtx_l2c_cbcx_selx_s cn70xxp1;
2884 struct cvmx_dtx_l2c_cbcx_selx_s cn73xx;
2885 struct cvmx_dtx_l2c_cbcx_selx_s cn78xx;
2886 struct cvmx_dtx_l2c_cbcx_selx_s cn78xxp1;
2887 struct cvmx_dtx_l2c_cbcx_selx_s cnf75xx;
2888};
2889
2890typedef union cvmx_dtx_l2c_cbcx_selx cvmx_dtx_l2c_cbcx_selx_t;
2891
2892/**
2893 * cvmx_dtx_l2c_mci#_bcst_rsp
2894 */
2895union cvmx_dtx_l2c_mcix_bcst_rsp {
2896 u64 u64;
2897 struct cvmx_dtx_l2c_mcix_bcst_rsp_s {
2898 u64 reserved_1_63 : 63;
2899 u64 ena : 1;
2900 } s;
2901 struct cvmx_dtx_l2c_mcix_bcst_rsp_s cn70xx;
2902 struct cvmx_dtx_l2c_mcix_bcst_rsp_s cn70xxp1;
2903 struct cvmx_dtx_l2c_mcix_bcst_rsp_s cn73xx;
2904 struct cvmx_dtx_l2c_mcix_bcst_rsp_s cn78xx;
2905 struct cvmx_dtx_l2c_mcix_bcst_rsp_s cn78xxp1;
2906 struct cvmx_dtx_l2c_mcix_bcst_rsp_s cnf75xx;
2907};
2908
2909typedef union cvmx_dtx_l2c_mcix_bcst_rsp cvmx_dtx_l2c_mcix_bcst_rsp_t;
2910
2911/**
2912 * cvmx_dtx_l2c_mci#_ctl
2913 */
2914union cvmx_dtx_l2c_mcix_ctl {
2915 u64 u64;
2916 struct cvmx_dtx_l2c_mcix_ctl_s {
2917 u64 reserved_5_63 : 59;
2918 u64 active : 1;
2919 u64 reserved_2_3 : 2;
2920 u64 echoen : 1;
2921 u64 swap : 1;
2922 } s;
2923 struct cvmx_dtx_l2c_mcix_ctl_s cn70xx;
2924 struct cvmx_dtx_l2c_mcix_ctl_s cn70xxp1;
2925 struct cvmx_dtx_l2c_mcix_ctl_s cn73xx;
2926 struct cvmx_dtx_l2c_mcix_ctl_s cn78xx;
2927 struct cvmx_dtx_l2c_mcix_ctl_s cn78xxp1;
2928 struct cvmx_dtx_l2c_mcix_ctl_s cnf75xx;
2929};
2930
2931typedef union cvmx_dtx_l2c_mcix_ctl cvmx_dtx_l2c_mcix_ctl_t;
2932
2933/**
2934 * cvmx_dtx_l2c_mci#_dat#
2935 */
2936union cvmx_dtx_l2c_mcix_datx {
2937 u64 u64;
2938 struct cvmx_dtx_l2c_mcix_datx_s {
2939 u64 reserved_36_63 : 28;
2940 u64 raw : 36;
2941 } s;
2942 struct cvmx_dtx_l2c_mcix_datx_s cn70xx;
2943 struct cvmx_dtx_l2c_mcix_datx_s cn70xxp1;
2944 struct cvmx_dtx_l2c_mcix_datx_s cn73xx;
2945 struct cvmx_dtx_l2c_mcix_datx_s cn78xx;
2946 struct cvmx_dtx_l2c_mcix_datx_s cn78xxp1;
2947 struct cvmx_dtx_l2c_mcix_datx_s cnf75xx;
2948};
2949
2950typedef union cvmx_dtx_l2c_mcix_datx cvmx_dtx_l2c_mcix_datx_t;
2951
2952/**
2953 * cvmx_dtx_l2c_mci#_ena#
2954 */
2955union cvmx_dtx_l2c_mcix_enax {
2956 u64 u64;
2957 struct cvmx_dtx_l2c_mcix_enax_s {
2958 u64 reserved_36_63 : 28;
2959 u64 ena : 36;
2960 } s;
2961 struct cvmx_dtx_l2c_mcix_enax_s cn70xx;
2962 struct cvmx_dtx_l2c_mcix_enax_s cn70xxp1;
2963 struct cvmx_dtx_l2c_mcix_enax_s cn73xx;
2964 struct cvmx_dtx_l2c_mcix_enax_s cn78xx;
2965 struct cvmx_dtx_l2c_mcix_enax_s cn78xxp1;
2966 struct cvmx_dtx_l2c_mcix_enax_s cnf75xx;
2967};
2968
2969typedef union cvmx_dtx_l2c_mcix_enax cvmx_dtx_l2c_mcix_enax_t;
2970
2971/**
2972 * cvmx_dtx_l2c_mci#_sel#
2973 */
2974union cvmx_dtx_l2c_mcix_selx {
2975 u64 u64;
2976 struct cvmx_dtx_l2c_mcix_selx_s {
2977 u64 reserved_24_63 : 40;
2978 u64 value : 24;
2979 } s;
2980 struct cvmx_dtx_l2c_mcix_selx_s cn70xx;
2981 struct cvmx_dtx_l2c_mcix_selx_s cn70xxp1;
2982 struct cvmx_dtx_l2c_mcix_selx_s cn73xx;
2983 struct cvmx_dtx_l2c_mcix_selx_s cn78xx;
2984 struct cvmx_dtx_l2c_mcix_selx_s cn78xxp1;
2985 struct cvmx_dtx_l2c_mcix_selx_s cnf75xx;
2986};
2987
2988typedef union cvmx_dtx_l2c_mcix_selx cvmx_dtx_l2c_mcix_selx_t;
2989
2990/**
2991 * cvmx_dtx_l2c_tad#_bcst_rsp
2992 */
2993union cvmx_dtx_l2c_tadx_bcst_rsp {
2994 u64 u64;
2995 struct cvmx_dtx_l2c_tadx_bcst_rsp_s {
2996 u64 reserved_1_63 : 63;
2997 u64 ena : 1;
2998 } s;
2999 struct cvmx_dtx_l2c_tadx_bcst_rsp_s cn70xx;
3000 struct cvmx_dtx_l2c_tadx_bcst_rsp_s cn70xxp1;
3001 struct cvmx_dtx_l2c_tadx_bcst_rsp_s cn73xx;
3002 struct cvmx_dtx_l2c_tadx_bcst_rsp_s cn78xx;
3003 struct cvmx_dtx_l2c_tadx_bcst_rsp_s cn78xxp1;
3004 struct cvmx_dtx_l2c_tadx_bcst_rsp_s cnf75xx;
3005};
3006
3007typedef union cvmx_dtx_l2c_tadx_bcst_rsp cvmx_dtx_l2c_tadx_bcst_rsp_t;
3008
3009/**
3010 * cvmx_dtx_l2c_tad#_ctl
3011 */
3012union cvmx_dtx_l2c_tadx_ctl {
3013 u64 u64;
3014 struct cvmx_dtx_l2c_tadx_ctl_s {
3015 u64 reserved_5_63 : 59;
3016 u64 active : 1;
3017 u64 reserved_2_3 : 2;
3018 u64 echoen : 1;
3019 u64 swap : 1;
3020 } s;
3021 struct cvmx_dtx_l2c_tadx_ctl_s cn70xx;
3022 struct cvmx_dtx_l2c_tadx_ctl_s cn70xxp1;
3023 struct cvmx_dtx_l2c_tadx_ctl_s cn73xx;
3024 struct cvmx_dtx_l2c_tadx_ctl_s cn78xx;
3025 struct cvmx_dtx_l2c_tadx_ctl_s cn78xxp1;
3026 struct cvmx_dtx_l2c_tadx_ctl_s cnf75xx;
3027};
3028
3029typedef union cvmx_dtx_l2c_tadx_ctl cvmx_dtx_l2c_tadx_ctl_t;
3030
3031/**
3032 * cvmx_dtx_l2c_tad#_dat#
3033 */
3034union cvmx_dtx_l2c_tadx_datx {
3035 u64 u64;
3036 struct cvmx_dtx_l2c_tadx_datx_s {
3037 u64 reserved_36_63 : 28;
3038 u64 raw : 36;
3039 } s;
3040 struct cvmx_dtx_l2c_tadx_datx_s cn70xx;
3041 struct cvmx_dtx_l2c_tadx_datx_s cn70xxp1;
3042 struct cvmx_dtx_l2c_tadx_datx_s cn73xx;
3043 struct cvmx_dtx_l2c_tadx_datx_s cn78xx;
3044 struct cvmx_dtx_l2c_tadx_datx_s cn78xxp1;
3045 struct cvmx_dtx_l2c_tadx_datx_s cnf75xx;
3046};
3047
3048typedef union cvmx_dtx_l2c_tadx_datx cvmx_dtx_l2c_tadx_datx_t;
3049
3050/**
3051 * cvmx_dtx_l2c_tad#_ena#
3052 */
3053union cvmx_dtx_l2c_tadx_enax {
3054 u64 u64;
3055 struct cvmx_dtx_l2c_tadx_enax_s {
3056 u64 reserved_36_63 : 28;
3057 u64 ena : 36;
3058 } s;
3059 struct cvmx_dtx_l2c_tadx_enax_s cn70xx;
3060 struct cvmx_dtx_l2c_tadx_enax_s cn70xxp1;
3061 struct cvmx_dtx_l2c_tadx_enax_s cn73xx;
3062 struct cvmx_dtx_l2c_tadx_enax_s cn78xx;
3063 struct cvmx_dtx_l2c_tadx_enax_s cn78xxp1;
3064 struct cvmx_dtx_l2c_tadx_enax_s cnf75xx;
3065};
3066
3067typedef union cvmx_dtx_l2c_tadx_enax cvmx_dtx_l2c_tadx_enax_t;
3068
3069/**
3070 * cvmx_dtx_l2c_tad#_sel#
3071 */
3072union cvmx_dtx_l2c_tadx_selx {
3073 u64 u64;
3074 struct cvmx_dtx_l2c_tadx_selx_s {
3075 u64 reserved_24_63 : 40;
3076 u64 value : 24;
3077 } s;
3078 struct cvmx_dtx_l2c_tadx_selx_s cn70xx;
3079 struct cvmx_dtx_l2c_tadx_selx_s cn70xxp1;
3080 struct cvmx_dtx_l2c_tadx_selx_s cn73xx;
3081 struct cvmx_dtx_l2c_tadx_selx_s cn78xx;
3082 struct cvmx_dtx_l2c_tadx_selx_s cn78xxp1;
3083 struct cvmx_dtx_l2c_tadx_selx_s cnf75xx;
3084};
3085
3086typedef union cvmx_dtx_l2c_tadx_selx cvmx_dtx_l2c_tadx_selx_t;
3087
3088/**
3089 * cvmx_dtx_lap#_bcst_rsp
3090 */
3091union cvmx_dtx_lapx_bcst_rsp {
3092 u64 u64;
3093 struct cvmx_dtx_lapx_bcst_rsp_s {
3094 u64 reserved_1_63 : 63;
3095 u64 ena : 1;
3096 } s;
3097 struct cvmx_dtx_lapx_bcst_rsp_s cn78xx;
3098 struct cvmx_dtx_lapx_bcst_rsp_s cn78xxp1;
3099};
3100
3101typedef union cvmx_dtx_lapx_bcst_rsp cvmx_dtx_lapx_bcst_rsp_t;
3102
3103/**
3104 * cvmx_dtx_lap#_ctl
3105 */
3106union cvmx_dtx_lapx_ctl {
3107 u64 u64;
3108 struct cvmx_dtx_lapx_ctl_s {
3109 u64 reserved_5_63 : 59;
3110 u64 active : 1;
3111 u64 reserved_2_3 : 2;
3112 u64 echoen : 1;
3113 u64 swap : 1;
3114 } s;
3115 struct cvmx_dtx_lapx_ctl_s cn78xx;
3116 struct cvmx_dtx_lapx_ctl_s cn78xxp1;
3117};
3118
3119typedef union cvmx_dtx_lapx_ctl cvmx_dtx_lapx_ctl_t;
3120
3121/**
3122 * cvmx_dtx_lap#_dat#
3123 */
3124union cvmx_dtx_lapx_datx {
3125 u64 u64;
3126 struct cvmx_dtx_lapx_datx_s {
3127 u64 reserved_36_63 : 28;
3128 u64 raw : 36;
3129 } s;
3130 struct cvmx_dtx_lapx_datx_s cn78xx;
3131 struct cvmx_dtx_lapx_datx_s cn78xxp1;
3132};
3133
3134typedef union cvmx_dtx_lapx_datx cvmx_dtx_lapx_datx_t;
3135
3136/**
3137 * cvmx_dtx_lap#_ena#
3138 */
3139union cvmx_dtx_lapx_enax {
3140 u64 u64;
3141 struct cvmx_dtx_lapx_enax_s {
3142 u64 reserved_36_63 : 28;
3143 u64 ena : 36;
3144 } s;
3145 struct cvmx_dtx_lapx_enax_s cn78xx;
3146 struct cvmx_dtx_lapx_enax_s cn78xxp1;
3147};
3148
3149typedef union cvmx_dtx_lapx_enax cvmx_dtx_lapx_enax_t;
3150
3151/**
3152 * cvmx_dtx_lap#_sel#
3153 */
3154union cvmx_dtx_lapx_selx {
3155 u64 u64;
3156 struct cvmx_dtx_lapx_selx_s {
3157 u64 reserved_24_63 : 40;
3158 u64 value : 24;
3159 } s;
3160 struct cvmx_dtx_lapx_selx_s cn78xx;
3161 struct cvmx_dtx_lapx_selx_s cn78xxp1;
3162};
3163
3164typedef union cvmx_dtx_lapx_selx cvmx_dtx_lapx_selx_t;
3165
3166/**
3167 * cvmx_dtx_lbk_bcst_rsp
3168 */
3169union cvmx_dtx_lbk_bcst_rsp {
3170 u64 u64;
3171 struct cvmx_dtx_lbk_bcst_rsp_s {
3172 u64 reserved_1_63 : 63;
3173 u64 ena : 1;
3174 } s;
3175 struct cvmx_dtx_lbk_bcst_rsp_s cn73xx;
3176 struct cvmx_dtx_lbk_bcst_rsp_s cn78xx;
3177 struct cvmx_dtx_lbk_bcst_rsp_s cn78xxp1;
3178 struct cvmx_dtx_lbk_bcst_rsp_s cnf75xx;
3179};
3180
3181typedef union cvmx_dtx_lbk_bcst_rsp cvmx_dtx_lbk_bcst_rsp_t;
3182
3183/**
3184 * cvmx_dtx_lbk_ctl
3185 */
3186union cvmx_dtx_lbk_ctl {
3187 u64 u64;
3188 struct cvmx_dtx_lbk_ctl_s {
3189 u64 reserved_5_63 : 59;
3190 u64 active : 1;
3191 u64 reserved_2_3 : 2;
3192 u64 echoen : 1;
3193 u64 swap : 1;
3194 } s;
3195 struct cvmx_dtx_lbk_ctl_s cn73xx;
3196 struct cvmx_dtx_lbk_ctl_s cn78xx;
3197 struct cvmx_dtx_lbk_ctl_s cn78xxp1;
3198 struct cvmx_dtx_lbk_ctl_s cnf75xx;
3199};
3200
3201typedef union cvmx_dtx_lbk_ctl cvmx_dtx_lbk_ctl_t;
3202
3203/**
3204 * cvmx_dtx_lbk_dat#
3205 */
3206union cvmx_dtx_lbk_datx {
3207 u64 u64;
3208 struct cvmx_dtx_lbk_datx_s {
3209 u64 reserved_36_63 : 28;
3210 u64 raw : 36;
3211 } s;
3212 struct cvmx_dtx_lbk_datx_s cn73xx;
3213 struct cvmx_dtx_lbk_datx_s cn78xx;
3214 struct cvmx_dtx_lbk_datx_s cn78xxp1;
3215 struct cvmx_dtx_lbk_datx_s cnf75xx;
3216};
3217
3218typedef union cvmx_dtx_lbk_datx cvmx_dtx_lbk_datx_t;
3219
3220/**
3221 * cvmx_dtx_lbk_ena#
3222 */
3223union cvmx_dtx_lbk_enax {
3224 u64 u64;
3225 struct cvmx_dtx_lbk_enax_s {
3226 u64 reserved_36_63 : 28;
3227 u64 ena : 36;
3228 } s;
3229 struct cvmx_dtx_lbk_enax_s cn73xx;
3230 struct cvmx_dtx_lbk_enax_s cn78xx;
3231 struct cvmx_dtx_lbk_enax_s cn78xxp1;
3232 struct cvmx_dtx_lbk_enax_s cnf75xx;
3233};
3234
3235typedef union cvmx_dtx_lbk_enax cvmx_dtx_lbk_enax_t;
3236
3237/**
3238 * cvmx_dtx_lbk_sel#
3239 */
3240union cvmx_dtx_lbk_selx {
3241 u64 u64;
3242 struct cvmx_dtx_lbk_selx_s {
3243 u64 reserved_24_63 : 40;
3244 u64 value : 24;
3245 } s;
3246 struct cvmx_dtx_lbk_selx_s cn73xx;
3247 struct cvmx_dtx_lbk_selx_s cn78xx;
3248 struct cvmx_dtx_lbk_selx_s cn78xxp1;
3249 struct cvmx_dtx_lbk_selx_s cnf75xx;
3250};
3251
3252typedef union cvmx_dtx_lbk_selx cvmx_dtx_lbk_selx_t;
3253
3254/**
3255 * cvmx_dtx_lmc#_bcst_rsp
3256 */
3257union cvmx_dtx_lmcx_bcst_rsp {
3258 u64 u64;
3259 struct cvmx_dtx_lmcx_bcst_rsp_s {
3260 u64 reserved_1_63 : 63;
3261 u64 ena : 1;
3262 } s;
3263 struct cvmx_dtx_lmcx_bcst_rsp_s cn70xx;
3264 struct cvmx_dtx_lmcx_bcst_rsp_s cn70xxp1;
3265 struct cvmx_dtx_lmcx_bcst_rsp_s cn73xx;
3266 struct cvmx_dtx_lmcx_bcst_rsp_s cn78xx;
3267 struct cvmx_dtx_lmcx_bcst_rsp_s cn78xxp1;
3268 struct cvmx_dtx_lmcx_bcst_rsp_s cnf75xx;
3269};
3270
3271typedef union cvmx_dtx_lmcx_bcst_rsp cvmx_dtx_lmcx_bcst_rsp_t;
3272
3273/**
3274 * cvmx_dtx_lmc#_ctl
3275 */
3276union cvmx_dtx_lmcx_ctl {
3277 u64 u64;
3278 struct cvmx_dtx_lmcx_ctl_s {
3279 u64 reserved_5_63 : 59;
3280 u64 active : 1;
3281 u64 reserved_2_3 : 2;
3282 u64 echoen : 1;
3283 u64 swap : 1;
3284 } s;
3285 struct cvmx_dtx_lmcx_ctl_s cn70xx;
3286 struct cvmx_dtx_lmcx_ctl_s cn70xxp1;
3287 struct cvmx_dtx_lmcx_ctl_s cn73xx;
3288 struct cvmx_dtx_lmcx_ctl_s cn78xx;
3289 struct cvmx_dtx_lmcx_ctl_s cn78xxp1;
3290 struct cvmx_dtx_lmcx_ctl_s cnf75xx;
3291};
3292
3293typedef union cvmx_dtx_lmcx_ctl cvmx_dtx_lmcx_ctl_t;
3294
3295/**
3296 * cvmx_dtx_lmc#_dat#
3297 */
3298union cvmx_dtx_lmcx_datx {
3299 u64 u64;
3300 struct cvmx_dtx_lmcx_datx_s {
3301 u64 reserved_36_63 : 28;
3302 u64 raw : 36;
3303 } s;
3304 struct cvmx_dtx_lmcx_datx_s cn70xx;
3305 struct cvmx_dtx_lmcx_datx_s cn70xxp1;
3306 struct cvmx_dtx_lmcx_datx_s cn73xx;
3307 struct cvmx_dtx_lmcx_datx_s cn78xx;
3308 struct cvmx_dtx_lmcx_datx_s cn78xxp1;
3309 struct cvmx_dtx_lmcx_datx_s cnf75xx;
3310};
3311
3312typedef union cvmx_dtx_lmcx_datx cvmx_dtx_lmcx_datx_t;
3313
3314/**
3315 * cvmx_dtx_lmc#_ena#
3316 */
3317union cvmx_dtx_lmcx_enax {
3318 u64 u64;
3319 struct cvmx_dtx_lmcx_enax_s {
3320 u64 reserved_36_63 : 28;
3321 u64 ena : 36;
3322 } s;
3323 struct cvmx_dtx_lmcx_enax_s cn70xx;
3324 struct cvmx_dtx_lmcx_enax_s cn70xxp1;
3325 struct cvmx_dtx_lmcx_enax_s cn73xx;
3326 struct cvmx_dtx_lmcx_enax_s cn78xx;
3327 struct cvmx_dtx_lmcx_enax_s cn78xxp1;
3328 struct cvmx_dtx_lmcx_enax_s cnf75xx;
3329};
3330
3331typedef union cvmx_dtx_lmcx_enax cvmx_dtx_lmcx_enax_t;
3332
3333/**
3334 * cvmx_dtx_lmc#_sel#
3335 */
3336union cvmx_dtx_lmcx_selx {
3337 u64 u64;
3338 struct cvmx_dtx_lmcx_selx_s {
3339 u64 reserved_24_63 : 40;
3340 u64 value : 24;
3341 } s;
3342 struct cvmx_dtx_lmcx_selx_s cn70xx;
3343 struct cvmx_dtx_lmcx_selx_s cn70xxp1;
3344 struct cvmx_dtx_lmcx_selx_s cn73xx;
3345 struct cvmx_dtx_lmcx_selx_s cn78xx;
3346 struct cvmx_dtx_lmcx_selx_s cn78xxp1;
3347 struct cvmx_dtx_lmcx_selx_s cnf75xx;
3348};
3349
3350typedef union cvmx_dtx_lmcx_selx cvmx_dtx_lmcx_selx_t;
3351
3352/**
3353 * cvmx_dtx_mdb#_bcst_rsp
3354 */
3355union cvmx_dtx_mdbx_bcst_rsp {
3356 u64 u64;
3357 struct cvmx_dtx_mdbx_bcst_rsp_s {
3358 u64 reserved_1_63 : 63;
3359 u64 ena : 1;
3360 } s;
3361 struct cvmx_dtx_mdbx_bcst_rsp_s cnf75xx;
3362};
3363
3364typedef union cvmx_dtx_mdbx_bcst_rsp cvmx_dtx_mdbx_bcst_rsp_t;
3365
3366/**
3367 * cvmx_dtx_mdb#_ctl
3368 */
3369union cvmx_dtx_mdbx_ctl {
3370 u64 u64;
3371 struct cvmx_dtx_mdbx_ctl_s {
3372 u64 reserved_5_63 : 59;
3373 u64 active : 1;
3374 u64 reserved_2_3 : 2;
3375 u64 echoen : 1;
3376 u64 swap : 1;
3377 } s;
3378 struct cvmx_dtx_mdbx_ctl_s cnf75xx;
3379};
3380
3381typedef union cvmx_dtx_mdbx_ctl cvmx_dtx_mdbx_ctl_t;
3382
3383/**
3384 * cvmx_dtx_mdb#_dat#
3385 */
3386union cvmx_dtx_mdbx_datx {
3387 u64 u64;
3388 struct cvmx_dtx_mdbx_datx_s {
3389 u64 reserved_36_63 : 28;
3390 u64 raw : 36;
3391 } s;
3392 struct cvmx_dtx_mdbx_datx_s cnf75xx;
3393};
3394
3395typedef union cvmx_dtx_mdbx_datx cvmx_dtx_mdbx_datx_t;
3396
3397/**
3398 * cvmx_dtx_mdb#_ena#
3399 */
3400union cvmx_dtx_mdbx_enax {
3401 u64 u64;
3402 struct cvmx_dtx_mdbx_enax_s {
3403 u64 reserved_36_63 : 28;
3404 u64 ena : 36;
3405 } s;
3406 struct cvmx_dtx_mdbx_enax_s cnf75xx;
3407};
3408
3409typedef union cvmx_dtx_mdbx_enax cvmx_dtx_mdbx_enax_t;
3410
3411/**
3412 * cvmx_dtx_mdb#_sel#
3413 */
3414union cvmx_dtx_mdbx_selx {
3415 u64 u64;
3416 struct cvmx_dtx_mdbx_selx_s {
3417 u64 reserved_24_63 : 40;
3418 u64 value : 24;
3419 } s;
3420 struct cvmx_dtx_mdbx_selx_s cnf75xx;
3421};
3422
3423typedef union cvmx_dtx_mdbx_selx cvmx_dtx_mdbx_selx_t;
3424
3425/**
3426 * cvmx_dtx_mhbw_bcst_rsp
3427 */
3428union cvmx_dtx_mhbw_bcst_rsp {
3429 u64 u64;
3430 struct cvmx_dtx_mhbw_bcst_rsp_s {
3431 u64 reserved_1_63 : 63;
3432 u64 ena : 1;
3433 } s;
3434 struct cvmx_dtx_mhbw_bcst_rsp_s cnf75xx;
3435};
3436
3437typedef union cvmx_dtx_mhbw_bcst_rsp cvmx_dtx_mhbw_bcst_rsp_t;
3438
3439/**
3440 * cvmx_dtx_mhbw_ctl
3441 */
3442union cvmx_dtx_mhbw_ctl {
3443 u64 u64;
3444 struct cvmx_dtx_mhbw_ctl_s {
3445 u64 reserved_5_63 : 59;
3446 u64 active : 1;
3447 u64 reserved_2_3 : 2;
3448 u64 echoen : 1;
3449 u64 swap : 1;
3450 } s;
3451 struct cvmx_dtx_mhbw_ctl_s cnf75xx;
3452};
3453
3454typedef union cvmx_dtx_mhbw_ctl cvmx_dtx_mhbw_ctl_t;
3455
3456/**
3457 * cvmx_dtx_mhbw_dat#
3458 */
3459union cvmx_dtx_mhbw_datx {
3460 u64 u64;
3461 struct cvmx_dtx_mhbw_datx_s {
3462 u64 reserved_36_63 : 28;
3463 u64 raw : 36;
3464 } s;
3465 struct cvmx_dtx_mhbw_datx_s cnf75xx;
3466};
3467
3468typedef union cvmx_dtx_mhbw_datx cvmx_dtx_mhbw_datx_t;
3469
3470/**
3471 * cvmx_dtx_mhbw_ena#
3472 */
3473union cvmx_dtx_mhbw_enax {
3474 u64 u64;
3475 struct cvmx_dtx_mhbw_enax_s {
3476 u64 reserved_36_63 : 28;
3477 u64 ena : 36;
3478 } s;
3479 struct cvmx_dtx_mhbw_enax_s cnf75xx;
3480};
3481
3482typedef union cvmx_dtx_mhbw_enax cvmx_dtx_mhbw_enax_t;
3483
3484/**
3485 * cvmx_dtx_mhbw_sel#
3486 */
3487union cvmx_dtx_mhbw_selx {
3488 u64 u64;
3489 struct cvmx_dtx_mhbw_selx_s {
3490 u64 reserved_24_63 : 40;
3491 u64 value : 24;
3492 } s;
3493 struct cvmx_dtx_mhbw_selx_s cnf75xx;
3494};
3495
3496typedef union cvmx_dtx_mhbw_selx cvmx_dtx_mhbw_selx_t;
3497
3498/**
3499 * cvmx_dtx_mio_bcst_rsp
3500 */
3501union cvmx_dtx_mio_bcst_rsp {
3502 u64 u64;
3503 struct cvmx_dtx_mio_bcst_rsp_s {
3504 u64 reserved_1_63 : 63;
3505 u64 ena : 1;
3506 } s;
3507 struct cvmx_dtx_mio_bcst_rsp_s cn70xx;
3508 struct cvmx_dtx_mio_bcst_rsp_s cn70xxp1;
3509 struct cvmx_dtx_mio_bcst_rsp_s cn73xx;
3510 struct cvmx_dtx_mio_bcst_rsp_s cn78xx;
3511 struct cvmx_dtx_mio_bcst_rsp_s cn78xxp1;
3512 struct cvmx_dtx_mio_bcst_rsp_s cnf75xx;
3513};
3514
3515typedef union cvmx_dtx_mio_bcst_rsp cvmx_dtx_mio_bcst_rsp_t;
3516
3517/**
3518 * cvmx_dtx_mio_ctl
3519 */
3520union cvmx_dtx_mio_ctl {
3521 u64 u64;
3522 struct cvmx_dtx_mio_ctl_s {
3523 u64 reserved_5_63 : 59;
3524 u64 active : 1;
3525 u64 reserved_2_3 : 2;
3526 u64 echoen : 1;
3527 u64 swap : 1;
3528 } s;
3529 struct cvmx_dtx_mio_ctl_s cn70xx;
3530 struct cvmx_dtx_mio_ctl_s cn70xxp1;
3531 struct cvmx_dtx_mio_ctl_s cn73xx;
3532 struct cvmx_dtx_mio_ctl_s cn78xx;
3533 struct cvmx_dtx_mio_ctl_s cn78xxp1;
3534 struct cvmx_dtx_mio_ctl_s cnf75xx;
3535};
3536
3537typedef union cvmx_dtx_mio_ctl cvmx_dtx_mio_ctl_t;
3538
3539/**
3540 * cvmx_dtx_mio_dat#
3541 */
3542union cvmx_dtx_mio_datx {
3543 u64 u64;
3544 struct cvmx_dtx_mio_datx_s {
3545 u64 reserved_36_63 : 28;
3546 u64 raw : 36;
3547 } s;
3548 struct cvmx_dtx_mio_datx_s cn70xx;
3549 struct cvmx_dtx_mio_datx_s cn70xxp1;
3550 struct cvmx_dtx_mio_datx_s cn73xx;
3551 struct cvmx_dtx_mio_datx_s cn78xx;
3552 struct cvmx_dtx_mio_datx_s cn78xxp1;
3553 struct cvmx_dtx_mio_datx_s cnf75xx;
3554};
3555
3556typedef union cvmx_dtx_mio_datx cvmx_dtx_mio_datx_t;
3557
3558/**
3559 * cvmx_dtx_mio_ena#
3560 */
3561union cvmx_dtx_mio_enax {
3562 u64 u64;
3563 struct cvmx_dtx_mio_enax_s {
3564 u64 reserved_36_63 : 28;
3565 u64 ena : 36;
3566 } s;
3567 struct cvmx_dtx_mio_enax_s cn70xx;
3568 struct cvmx_dtx_mio_enax_s cn70xxp1;
3569 struct cvmx_dtx_mio_enax_s cn73xx;
3570 struct cvmx_dtx_mio_enax_s cn78xx;
3571 struct cvmx_dtx_mio_enax_s cn78xxp1;
3572 struct cvmx_dtx_mio_enax_s cnf75xx;
3573};
3574
3575typedef union cvmx_dtx_mio_enax cvmx_dtx_mio_enax_t;
3576
3577/**
3578 * cvmx_dtx_mio_sel#
3579 */
3580union cvmx_dtx_mio_selx {
3581 u64 u64;
3582 struct cvmx_dtx_mio_selx_s {
3583 u64 reserved_24_63 : 40;
3584 u64 value : 24;
3585 } s;
3586 struct cvmx_dtx_mio_selx_s cn70xx;
3587 struct cvmx_dtx_mio_selx_s cn70xxp1;
3588 struct cvmx_dtx_mio_selx_s cn73xx;
3589 struct cvmx_dtx_mio_selx_s cn78xx;
3590 struct cvmx_dtx_mio_selx_s cn78xxp1;
3591 struct cvmx_dtx_mio_selx_s cnf75xx;
3592};
3593
3594typedef union cvmx_dtx_mio_selx cvmx_dtx_mio_selx_t;
3595
3596/**
3597 * cvmx_dtx_ocx_bot_bcst_rsp
3598 */
3599union cvmx_dtx_ocx_bot_bcst_rsp {
3600 u64 u64;
3601 struct cvmx_dtx_ocx_bot_bcst_rsp_s {
3602 u64 reserved_1_63 : 63;
3603 u64 ena : 1;
3604 } s;
3605 struct cvmx_dtx_ocx_bot_bcst_rsp_s cn78xx;
3606 struct cvmx_dtx_ocx_bot_bcst_rsp_s cn78xxp1;
3607};
3608
3609typedef union cvmx_dtx_ocx_bot_bcst_rsp cvmx_dtx_ocx_bot_bcst_rsp_t;
3610
3611/**
3612 * cvmx_dtx_ocx_bot_ctl
3613 */
3614union cvmx_dtx_ocx_bot_ctl {
3615 u64 u64;
3616 struct cvmx_dtx_ocx_bot_ctl_s {
3617 u64 reserved_5_63 : 59;
3618 u64 active : 1;
3619 u64 reserved_2_3 : 2;
3620 u64 echoen : 1;
3621 u64 swap : 1;
3622 } s;
3623 struct cvmx_dtx_ocx_bot_ctl_s cn78xx;
3624 struct cvmx_dtx_ocx_bot_ctl_s cn78xxp1;
3625};
3626
3627typedef union cvmx_dtx_ocx_bot_ctl cvmx_dtx_ocx_bot_ctl_t;
3628
3629/**
3630 * cvmx_dtx_ocx_bot_dat#
3631 */
3632union cvmx_dtx_ocx_bot_datx {
3633 u64 u64;
3634 struct cvmx_dtx_ocx_bot_datx_s {
3635 u64 reserved_36_63 : 28;
3636 u64 raw : 36;
3637 } s;
3638 struct cvmx_dtx_ocx_bot_datx_s cn78xx;
3639 struct cvmx_dtx_ocx_bot_datx_s cn78xxp1;
3640};
3641
3642typedef union cvmx_dtx_ocx_bot_datx cvmx_dtx_ocx_bot_datx_t;
3643
3644/**
3645 * cvmx_dtx_ocx_bot_ena#
3646 */
3647union cvmx_dtx_ocx_bot_enax {
3648 u64 u64;
3649 struct cvmx_dtx_ocx_bot_enax_s {
3650 u64 reserved_36_63 : 28;
3651 u64 ena : 36;
3652 } s;
3653 struct cvmx_dtx_ocx_bot_enax_s cn78xx;
3654 struct cvmx_dtx_ocx_bot_enax_s cn78xxp1;
3655};
3656
3657typedef union cvmx_dtx_ocx_bot_enax cvmx_dtx_ocx_bot_enax_t;
3658
3659/**
3660 * cvmx_dtx_ocx_bot_sel#
3661 */
3662union cvmx_dtx_ocx_bot_selx {
3663 u64 u64;
3664 struct cvmx_dtx_ocx_bot_selx_s {
3665 u64 reserved_24_63 : 40;
3666 u64 value : 24;
3667 } s;
3668 struct cvmx_dtx_ocx_bot_selx_s cn78xx;
3669 struct cvmx_dtx_ocx_bot_selx_s cn78xxp1;
3670};
3671
3672typedef union cvmx_dtx_ocx_bot_selx cvmx_dtx_ocx_bot_selx_t;
3673
3674/**
3675 * cvmx_dtx_ocx_lnk#_bcst_rsp
3676 */
3677union cvmx_dtx_ocx_lnkx_bcst_rsp {
3678 u64 u64;
3679 struct cvmx_dtx_ocx_lnkx_bcst_rsp_s {
3680 u64 reserved_1_63 : 63;
3681 u64 ena : 1;
3682 } s;
3683 struct cvmx_dtx_ocx_lnkx_bcst_rsp_s cn78xx;
3684 struct cvmx_dtx_ocx_lnkx_bcst_rsp_s cn78xxp1;
3685};
3686
3687typedef union cvmx_dtx_ocx_lnkx_bcst_rsp cvmx_dtx_ocx_lnkx_bcst_rsp_t;
3688
3689/**
3690 * cvmx_dtx_ocx_lnk#_ctl
3691 */
3692union cvmx_dtx_ocx_lnkx_ctl {
3693 u64 u64;
3694 struct cvmx_dtx_ocx_lnkx_ctl_s {
3695 u64 reserved_5_63 : 59;
3696 u64 active : 1;
3697 u64 reserved_2_3 : 2;
3698 u64 echoen : 1;
3699 u64 swap : 1;
3700 } s;
3701 struct cvmx_dtx_ocx_lnkx_ctl_s cn78xx;
3702 struct cvmx_dtx_ocx_lnkx_ctl_s cn78xxp1;
3703};
3704
3705typedef union cvmx_dtx_ocx_lnkx_ctl cvmx_dtx_ocx_lnkx_ctl_t;
3706
3707/**
3708 * cvmx_dtx_ocx_lnk#_dat#
3709 */
3710union cvmx_dtx_ocx_lnkx_datx {
3711 u64 u64;
3712 struct cvmx_dtx_ocx_lnkx_datx_s {
3713 u64 reserved_36_63 : 28;
3714 u64 raw : 36;
3715 } s;
3716 struct cvmx_dtx_ocx_lnkx_datx_s cn78xx;
3717 struct cvmx_dtx_ocx_lnkx_datx_s cn78xxp1;
3718};
3719
3720typedef union cvmx_dtx_ocx_lnkx_datx cvmx_dtx_ocx_lnkx_datx_t;
3721
3722/**
3723 * cvmx_dtx_ocx_lnk#_ena#
3724 */
3725union cvmx_dtx_ocx_lnkx_enax {
3726 u64 u64;
3727 struct cvmx_dtx_ocx_lnkx_enax_s {
3728 u64 reserved_36_63 : 28;
3729 u64 ena : 36;
3730 } s;
3731 struct cvmx_dtx_ocx_lnkx_enax_s cn78xx;
3732 struct cvmx_dtx_ocx_lnkx_enax_s cn78xxp1;
3733};
3734
3735typedef union cvmx_dtx_ocx_lnkx_enax cvmx_dtx_ocx_lnkx_enax_t;
3736
3737/**
3738 * cvmx_dtx_ocx_lnk#_sel#
3739 */
3740union cvmx_dtx_ocx_lnkx_selx {
3741 u64 u64;
3742 struct cvmx_dtx_ocx_lnkx_selx_s {
3743 u64 reserved_24_63 : 40;
3744 u64 value : 24;
3745 } s;
3746 struct cvmx_dtx_ocx_lnkx_selx_s cn78xx;
3747 struct cvmx_dtx_ocx_lnkx_selx_s cn78xxp1;
3748};
3749
3750typedef union cvmx_dtx_ocx_lnkx_selx cvmx_dtx_ocx_lnkx_selx_t;
3751
3752/**
3753 * cvmx_dtx_ocx_ole#_bcst_rsp
3754 */
3755union cvmx_dtx_ocx_olex_bcst_rsp {
3756 u64 u64;
3757 struct cvmx_dtx_ocx_olex_bcst_rsp_s {
3758 u64 reserved_1_63 : 63;
3759 u64 ena : 1;
3760 } s;
3761 struct cvmx_dtx_ocx_olex_bcst_rsp_s cn78xx;
3762 struct cvmx_dtx_ocx_olex_bcst_rsp_s cn78xxp1;
3763};
3764
3765typedef union cvmx_dtx_ocx_olex_bcst_rsp cvmx_dtx_ocx_olex_bcst_rsp_t;
3766
3767/**
3768 * cvmx_dtx_ocx_ole#_ctl
3769 */
3770union cvmx_dtx_ocx_olex_ctl {
3771 u64 u64;
3772 struct cvmx_dtx_ocx_olex_ctl_s {
3773 u64 reserved_5_63 : 59;
3774 u64 active : 1;
3775 u64 reserved_2_3 : 2;
3776 u64 echoen : 1;
3777 u64 swap : 1;
3778 } s;
3779 struct cvmx_dtx_ocx_olex_ctl_s cn78xx;
3780 struct cvmx_dtx_ocx_olex_ctl_s cn78xxp1;
3781};
3782
3783typedef union cvmx_dtx_ocx_olex_ctl cvmx_dtx_ocx_olex_ctl_t;
3784
3785/**
3786 * cvmx_dtx_ocx_ole#_dat#
3787 */
3788union cvmx_dtx_ocx_olex_datx {
3789 u64 u64;
3790 struct cvmx_dtx_ocx_olex_datx_s {
3791 u64 reserved_36_63 : 28;
3792 u64 raw : 36;
3793 } s;
3794 struct cvmx_dtx_ocx_olex_datx_s cn78xx;
3795 struct cvmx_dtx_ocx_olex_datx_s cn78xxp1;
3796};
3797
3798typedef union cvmx_dtx_ocx_olex_datx cvmx_dtx_ocx_olex_datx_t;
3799
3800/**
3801 * cvmx_dtx_ocx_ole#_ena#
3802 */
3803union cvmx_dtx_ocx_olex_enax {
3804 u64 u64;
3805 struct cvmx_dtx_ocx_olex_enax_s {
3806 u64 reserved_36_63 : 28;
3807 u64 ena : 36;
3808 } s;
3809 struct cvmx_dtx_ocx_olex_enax_s cn78xx;
3810 struct cvmx_dtx_ocx_olex_enax_s cn78xxp1;
3811};
3812
3813typedef union cvmx_dtx_ocx_olex_enax cvmx_dtx_ocx_olex_enax_t;
3814
3815/**
3816 * cvmx_dtx_ocx_ole#_sel#
3817 */
3818union cvmx_dtx_ocx_olex_selx {
3819 u64 u64;
3820 struct cvmx_dtx_ocx_olex_selx_s {
3821 u64 reserved_24_63 : 40;
3822 u64 value : 24;
3823 } s;
3824 struct cvmx_dtx_ocx_olex_selx_s cn78xx;
3825 struct cvmx_dtx_ocx_olex_selx_s cn78xxp1;
3826};
3827
3828typedef union cvmx_dtx_ocx_olex_selx cvmx_dtx_ocx_olex_selx_t;
3829
3830/**
3831 * cvmx_dtx_ocx_top_bcst_rsp
3832 */
3833union cvmx_dtx_ocx_top_bcst_rsp {
3834 u64 u64;
3835 struct cvmx_dtx_ocx_top_bcst_rsp_s {
3836 u64 reserved_1_63 : 63;
3837 u64 ena : 1;
3838 } s;
3839 struct cvmx_dtx_ocx_top_bcst_rsp_s cn78xx;
3840 struct cvmx_dtx_ocx_top_bcst_rsp_s cn78xxp1;
3841};
3842
3843typedef union cvmx_dtx_ocx_top_bcst_rsp cvmx_dtx_ocx_top_bcst_rsp_t;
3844
3845/**
3846 * cvmx_dtx_ocx_top_ctl
3847 */
3848union cvmx_dtx_ocx_top_ctl {
3849 u64 u64;
3850 struct cvmx_dtx_ocx_top_ctl_s {
3851 u64 reserved_5_63 : 59;
3852 u64 active : 1;
3853 u64 reserved_2_3 : 2;
3854 u64 echoen : 1;
3855 u64 swap : 1;
3856 } s;
3857 struct cvmx_dtx_ocx_top_ctl_s cn78xx;
3858 struct cvmx_dtx_ocx_top_ctl_s cn78xxp1;
3859};
3860
3861typedef union cvmx_dtx_ocx_top_ctl cvmx_dtx_ocx_top_ctl_t;
3862
3863/**
3864 * cvmx_dtx_ocx_top_dat#
3865 */
3866union cvmx_dtx_ocx_top_datx {
3867 u64 u64;
3868 struct cvmx_dtx_ocx_top_datx_s {
3869 u64 reserved_36_63 : 28;
3870 u64 raw : 36;
3871 } s;
3872 struct cvmx_dtx_ocx_top_datx_s cn78xx;
3873 struct cvmx_dtx_ocx_top_datx_s cn78xxp1;
3874};
3875
3876typedef union cvmx_dtx_ocx_top_datx cvmx_dtx_ocx_top_datx_t;
3877
3878/**
3879 * cvmx_dtx_ocx_top_ena#
3880 */
3881union cvmx_dtx_ocx_top_enax {
3882 u64 u64;
3883 struct cvmx_dtx_ocx_top_enax_s {
3884 u64 reserved_36_63 : 28;
3885 u64 ena : 36;
3886 } s;
3887 struct cvmx_dtx_ocx_top_enax_s cn78xx;
3888 struct cvmx_dtx_ocx_top_enax_s cn78xxp1;
3889};
3890
3891typedef union cvmx_dtx_ocx_top_enax cvmx_dtx_ocx_top_enax_t;
3892
3893/**
3894 * cvmx_dtx_ocx_top_sel#
3895 */
3896union cvmx_dtx_ocx_top_selx {
3897 u64 u64;
3898 struct cvmx_dtx_ocx_top_selx_s {
3899 u64 reserved_24_63 : 40;
3900 u64 value : 24;
3901 } s;
3902 struct cvmx_dtx_ocx_top_selx_s cn78xx;
3903 struct cvmx_dtx_ocx_top_selx_s cn78xxp1;
3904};
3905
3906typedef union cvmx_dtx_ocx_top_selx cvmx_dtx_ocx_top_selx_t;
3907
3908/**
3909 * cvmx_dtx_osm_bcst_rsp
3910 */
3911union cvmx_dtx_osm_bcst_rsp {
3912 u64 u64;
3913 struct cvmx_dtx_osm_bcst_rsp_s {
3914 u64 reserved_1_63 : 63;
3915 u64 ena : 1;
3916 } s;
3917 struct cvmx_dtx_osm_bcst_rsp_s cn73xx;
3918 struct cvmx_dtx_osm_bcst_rsp_s cn78xx;
3919 struct cvmx_dtx_osm_bcst_rsp_s cn78xxp1;
3920};
3921
3922typedef union cvmx_dtx_osm_bcst_rsp cvmx_dtx_osm_bcst_rsp_t;
3923
3924/**
3925 * cvmx_dtx_osm_ctl
3926 */
3927union cvmx_dtx_osm_ctl {
3928 u64 u64;
3929 struct cvmx_dtx_osm_ctl_s {
3930 u64 reserved_5_63 : 59;
3931 u64 active : 1;
3932 u64 reserved_2_3 : 2;
3933 u64 echoen : 1;
3934 u64 swap : 1;
3935 } s;
3936 struct cvmx_dtx_osm_ctl_s cn73xx;
3937 struct cvmx_dtx_osm_ctl_s cn78xx;
3938 struct cvmx_dtx_osm_ctl_s cn78xxp1;
3939};
3940
3941typedef union cvmx_dtx_osm_ctl cvmx_dtx_osm_ctl_t;
3942
3943/**
3944 * cvmx_dtx_osm_dat#
3945 */
3946union cvmx_dtx_osm_datx {
3947 u64 u64;
3948 struct cvmx_dtx_osm_datx_s {
3949 u64 reserved_36_63 : 28;
3950 u64 raw : 36;
3951 } s;
3952 struct cvmx_dtx_osm_datx_s cn73xx;
3953 struct cvmx_dtx_osm_datx_s cn78xx;
3954 struct cvmx_dtx_osm_datx_s cn78xxp1;
3955};
3956
3957typedef union cvmx_dtx_osm_datx cvmx_dtx_osm_datx_t;
3958
3959/**
3960 * cvmx_dtx_osm_ena#
3961 */
3962union cvmx_dtx_osm_enax {
3963 u64 u64;
3964 struct cvmx_dtx_osm_enax_s {
3965 u64 reserved_36_63 : 28;
3966 u64 ena : 36;
3967 } s;
3968 struct cvmx_dtx_osm_enax_s cn73xx;
3969 struct cvmx_dtx_osm_enax_s cn78xx;
3970 struct cvmx_dtx_osm_enax_s cn78xxp1;
3971};
3972
3973typedef union cvmx_dtx_osm_enax cvmx_dtx_osm_enax_t;
3974
3975/**
3976 * cvmx_dtx_osm_sel#
3977 */
3978union cvmx_dtx_osm_selx {
3979 u64 u64;
3980 struct cvmx_dtx_osm_selx_s {
3981 u64 reserved_24_63 : 40;
3982 u64 value : 24;
3983 } s;
3984 struct cvmx_dtx_osm_selx_s cn73xx;
3985 struct cvmx_dtx_osm_selx_s cn78xx;
3986 struct cvmx_dtx_osm_selx_s cn78xxp1;
3987};
3988
3989typedef union cvmx_dtx_osm_selx cvmx_dtx_osm_selx_t;
3990
3991/**
3992 * cvmx_dtx_pcs#_bcst_rsp
3993 */
3994union cvmx_dtx_pcsx_bcst_rsp {
3995 u64 u64;
3996 struct cvmx_dtx_pcsx_bcst_rsp_s {
3997 u64 reserved_1_63 : 63;
3998 u64 ena : 1;
3999 } s;
4000 struct cvmx_dtx_pcsx_bcst_rsp_s cn70xx;
4001 struct cvmx_dtx_pcsx_bcst_rsp_s cn70xxp1;
4002};
4003
4004typedef union cvmx_dtx_pcsx_bcst_rsp cvmx_dtx_pcsx_bcst_rsp_t;
4005
4006/**
4007 * cvmx_dtx_pcs#_ctl
4008 */
4009union cvmx_dtx_pcsx_ctl {
4010 u64 u64;
4011 struct cvmx_dtx_pcsx_ctl_s {
4012 u64 reserved_5_63 : 59;
4013 u64 active : 1;
4014 u64 reserved_2_3 : 2;
4015 u64 echoen : 1;
4016 u64 swap : 1;
4017 } s;
4018 struct cvmx_dtx_pcsx_ctl_s cn70xx;
4019 struct cvmx_dtx_pcsx_ctl_s cn70xxp1;
4020};
4021
4022typedef union cvmx_dtx_pcsx_ctl cvmx_dtx_pcsx_ctl_t;
4023
4024/**
4025 * cvmx_dtx_pcs#_dat#
4026 */
4027union cvmx_dtx_pcsx_datx {
4028 u64 u64;
4029 struct cvmx_dtx_pcsx_datx_s {
4030 u64 reserved_36_63 : 28;
4031 u64 raw : 36;
4032 } s;
4033 struct cvmx_dtx_pcsx_datx_s cn70xx;
4034 struct cvmx_dtx_pcsx_datx_s cn70xxp1;
4035};
4036
4037typedef union cvmx_dtx_pcsx_datx cvmx_dtx_pcsx_datx_t;
4038
4039/**
4040 * cvmx_dtx_pcs#_ena#
4041 */
4042union cvmx_dtx_pcsx_enax {
4043 u64 u64;
4044 struct cvmx_dtx_pcsx_enax_s {
4045 u64 reserved_36_63 : 28;
4046 u64 ena : 36;
4047 } s;
4048 struct cvmx_dtx_pcsx_enax_s cn70xx;
4049 struct cvmx_dtx_pcsx_enax_s cn70xxp1;
4050};
4051
4052typedef union cvmx_dtx_pcsx_enax cvmx_dtx_pcsx_enax_t;
4053
4054/**
4055 * cvmx_dtx_pcs#_sel#
4056 */
4057union cvmx_dtx_pcsx_selx {
4058 u64 u64;
4059 struct cvmx_dtx_pcsx_selx_s {
4060 u64 reserved_24_63 : 40;
4061 u64 value : 24;
4062 } s;
4063 struct cvmx_dtx_pcsx_selx_s cn70xx;
4064 struct cvmx_dtx_pcsx_selx_s cn70xxp1;
4065};
4066
4067typedef union cvmx_dtx_pcsx_selx cvmx_dtx_pcsx_selx_t;
4068
4069/**
4070 * cvmx_dtx_pem#_bcst_rsp
4071 */
4072union cvmx_dtx_pemx_bcst_rsp {
4073 u64 u64;
4074 struct cvmx_dtx_pemx_bcst_rsp_s {
4075 u64 reserved_1_63 : 63;
4076 u64 ena : 1;
4077 } s;
4078 struct cvmx_dtx_pemx_bcst_rsp_s cn70xx;
4079 struct cvmx_dtx_pemx_bcst_rsp_s cn70xxp1;
4080 struct cvmx_dtx_pemx_bcst_rsp_s cn73xx;
4081 struct cvmx_dtx_pemx_bcst_rsp_s cn78xx;
4082 struct cvmx_dtx_pemx_bcst_rsp_s cn78xxp1;
4083 struct cvmx_dtx_pemx_bcst_rsp_s cnf75xx;
4084};
4085
4086typedef union cvmx_dtx_pemx_bcst_rsp cvmx_dtx_pemx_bcst_rsp_t;
4087
4088/**
4089 * cvmx_dtx_pem#_ctl
4090 */
4091union cvmx_dtx_pemx_ctl {
4092 u64 u64;
4093 struct cvmx_dtx_pemx_ctl_s {
4094 u64 reserved_5_63 : 59;
4095 u64 active : 1;
4096 u64 reserved_2_3 : 2;
4097 u64 echoen : 1;
4098 u64 swap : 1;
4099 } s;
4100 struct cvmx_dtx_pemx_ctl_s cn70xx;
4101 struct cvmx_dtx_pemx_ctl_s cn70xxp1;
4102 struct cvmx_dtx_pemx_ctl_s cn73xx;
4103 struct cvmx_dtx_pemx_ctl_s cn78xx;
4104 struct cvmx_dtx_pemx_ctl_s cn78xxp1;
4105 struct cvmx_dtx_pemx_ctl_s cnf75xx;
4106};
4107
4108typedef union cvmx_dtx_pemx_ctl cvmx_dtx_pemx_ctl_t;
4109
4110/**
4111 * cvmx_dtx_pem#_dat#
4112 */
4113union cvmx_dtx_pemx_datx {
4114 u64 u64;
4115 struct cvmx_dtx_pemx_datx_s {
4116 u64 reserved_36_63 : 28;
4117 u64 raw : 36;
4118 } s;
4119 struct cvmx_dtx_pemx_datx_s cn70xx;
4120 struct cvmx_dtx_pemx_datx_s cn70xxp1;
4121 struct cvmx_dtx_pemx_datx_s cn73xx;
4122 struct cvmx_dtx_pemx_datx_s cn78xx;
4123 struct cvmx_dtx_pemx_datx_s cn78xxp1;
4124 struct cvmx_dtx_pemx_datx_s cnf75xx;
4125};
4126
4127typedef union cvmx_dtx_pemx_datx cvmx_dtx_pemx_datx_t;
4128
4129/**
4130 * cvmx_dtx_pem#_ena#
4131 */
4132union cvmx_dtx_pemx_enax {
4133 u64 u64;
4134 struct cvmx_dtx_pemx_enax_s {
4135 u64 reserved_36_63 : 28;
4136 u64 ena : 36;
4137 } s;
4138 struct cvmx_dtx_pemx_enax_s cn70xx;
4139 struct cvmx_dtx_pemx_enax_s cn70xxp1;
4140 struct cvmx_dtx_pemx_enax_s cn73xx;
4141 struct cvmx_dtx_pemx_enax_s cn78xx;
4142 struct cvmx_dtx_pemx_enax_s cn78xxp1;
4143 struct cvmx_dtx_pemx_enax_s cnf75xx;
4144};
4145
4146typedef union cvmx_dtx_pemx_enax cvmx_dtx_pemx_enax_t;
4147
4148/**
4149 * cvmx_dtx_pem#_sel#
4150 */
4151union cvmx_dtx_pemx_selx {
4152 u64 u64;
4153 struct cvmx_dtx_pemx_selx_s {
4154 u64 reserved_24_63 : 40;
4155 u64 value : 24;
4156 } s;
4157 struct cvmx_dtx_pemx_selx_s cn70xx;
4158 struct cvmx_dtx_pemx_selx_s cn70xxp1;
4159 struct cvmx_dtx_pemx_selx_s cn73xx;
4160 struct cvmx_dtx_pemx_selx_s cn78xx;
4161 struct cvmx_dtx_pemx_selx_s cn78xxp1;
4162 struct cvmx_dtx_pemx_selx_s cnf75xx;
4163};
4164
4165typedef union cvmx_dtx_pemx_selx cvmx_dtx_pemx_selx_t;
4166
4167/**
4168 * cvmx_dtx_pip_bcst_rsp
4169 */
4170union cvmx_dtx_pip_bcst_rsp {
4171 u64 u64;
4172 struct cvmx_dtx_pip_bcst_rsp_s {
4173 u64 reserved_1_63 : 63;
4174 u64 ena : 1;
4175 } s;
4176 struct cvmx_dtx_pip_bcst_rsp_s cn70xx;
4177 struct cvmx_dtx_pip_bcst_rsp_s cn70xxp1;
4178};
4179
4180typedef union cvmx_dtx_pip_bcst_rsp cvmx_dtx_pip_bcst_rsp_t;
4181
4182/**
4183 * cvmx_dtx_pip_ctl
4184 */
4185union cvmx_dtx_pip_ctl {
4186 u64 u64;
4187 struct cvmx_dtx_pip_ctl_s {
4188 u64 reserved_5_63 : 59;
4189 u64 active : 1;
4190 u64 reserved_2_3 : 2;
4191 u64 echoen : 1;
4192 u64 swap : 1;
4193 } s;
4194 struct cvmx_dtx_pip_ctl_s cn70xx;
4195 struct cvmx_dtx_pip_ctl_s cn70xxp1;
4196};
4197
4198typedef union cvmx_dtx_pip_ctl cvmx_dtx_pip_ctl_t;
4199
4200/**
4201 * cvmx_dtx_pip_dat#
4202 */
4203union cvmx_dtx_pip_datx {
4204 u64 u64;
4205 struct cvmx_dtx_pip_datx_s {
4206 u64 reserved_36_63 : 28;
4207 u64 raw : 36;
4208 } s;
4209 struct cvmx_dtx_pip_datx_s cn70xx;
4210 struct cvmx_dtx_pip_datx_s cn70xxp1;
4211};
4212
4213typedef union cvmx_dtx_pip_datx cvmx_dtx_pip_datx_t;
4214
4215/**
4216 * cvmx_dtx_pip_ena#
4217 */
4218union cvmx_dtx_pip_enax {
4219 u64 u64;
4220 struct cvmx_dtx_pip_enax_s {
4221 u64 reserved_36_63 : 28;
4222 u64 ena : 36;
4223 } s;
4224 struct cvmx_dtx_pip_enax_s cn70xx;
4225 struct cvmx_dtx_pip_enax_s cn70xxp1;
4226};
4227
4228typedef union cvmx_dtx_pip_enax cvmx_dtx_pip_enax_t;
4229
4230/**
4231 * cvmx_dtx_pip_sel#
4232 */
4233union cvmx_dtx_pip_selx {
4234 u64 u64;
4235 struct cvmx_dtx_pip_selx_s {
4236 u64 reserved_24_63 : 40;
4237 u64 value : 24;
4238 } s;
4239 struct cvmx_dtx_pip_selx_s cn70xx;
4240 struct cvmx_dtx_pip_selx_s cn70xxp1;
4241};
4242
4243typedef union cvmx_dtx_pip_selx cvmx_dtx_pip_selx_t;
4244
4245/**
4246 * cvmx_dtx_pki_pbe_bcst_rsp
4247 */
4248union cvmx_dtx_pki_pbe_bcst_rsp {
4249 u64 u64;
4250 struct cvmx_dtx_pki_pbe_bcst_rsp_s {
4251 u64 reserved_1_63 : 63;
4252 u64 ena : 1;
4253 } s;
4254 struct cvmx_dtx_pki_pbe_bcst_rsp_s cn73xx;
4255 struct cvmx_dtx_pki_pbe_bcst_rsp_s cn78xx;
4256 struct cvmx_dtx_pki_pbe_bcst_rsp_s cn78xxp1;
4257 struct cvmx_dtx_pki_pbe_bcst_rsp_s cnf75xx;
4258};
4259
4260typedef union cvmx_dtx_pki_pbe_bcst_rsp cvmx_dtx_pki_pbe_bcst_rsp_t;
4261
4262/**
4263 * cvmx_dtx_pki_pbe_ctl
4264 */
4265union cvmx_dtx_pki_pbe_ctl {
4266 u64 u64;
4267 struct cvmx_dtx_pki_pbe_ctl_s {
4268 u64 reserved_5_63 : 59;
4269 u64 active : 1;
4270 u64 reserved_2_3 : 2;
4271 u64 echoen : 1;
4272 u64 swap : 1;
4273 } s;
4274 struct cvmx_dtx_pki_pbe_ctl_s cn73xx;
4275 struct cvmx_dtx_pki_pbe_ctl_s cn78xx;
4276 struct cvmx_dtx_pki_pbe_ctl_s cn78xxp1;
4277 struct cvmx_dtx_pki_pbe_ctl_s cnf75xx;
4278};
4279
4280typedef union cvmx_dtx_pki_pbe_ctl cvmx_dtx_pki_pbe_ctl_t;
4281
4282/**
4283 * cvmx_dtx_pki_pbe_dat#
4284 */
4285union cvmx_dtx_pki_pbe_datx {
4286 u64 u64;
4287 struct cvmx_dtx_pki_pbe_datx_s {
4288 u64 reserved_36_63 : 28;
4289 u64 raw : 36;
4290 } s;
4291 struct cvmx_dtx_pki_pbe_datx_s cn73xx;
4292 struct cvmx_dtx_pki_pbe_datx_s cn78xx;
4293 struct cvmx_dtx_pki_pbe_datx_s cn78xxp1;
4294 struct cvmx_dtx_pki_pbe_datx_s cnf75xx;
4295};
4296
4297typedef union cvmx_dtx_pki_pbe_datx cvmx_dtx_pki_pbe_datx_t;
4298
4299/**
4300 * cvmx_dtx_pki_pbe_ena#
4301 */
4302union cvmx_dtx_pki_pbe_enax {
4303 u64 u64;
4304 struct cvmx_dtx_pki_pbe_enax_s {
4305 u64 reserved_36_63 : 28;
4306 u64 ena : 36;
4307 } s;
4308 struct cvmx_dtx_pki_pbe_enax_s cn73xx;
4309 struct cvmx_dtx_pki_pbe_enax_s cn78xx;
4310 struct cvmx_dtx_pki_pbe_enax_s cn78xxp1;
4311 struct cvmx_dtx_pki_pbe_enax_s cnf75xx;
4312};
4313
4314typedef union cvmx_dtx_pki_pbe_enax cvmx_dtx_pki_pbe_enax_t;
4315
4316/**
4317 * cvmx_dtx_pki_pbe_sel#
4318 */
4319union cvmx_dtx_pki_pbe_selx {
4320 u64 u64;
4321 struct cvmx_dtx_pki_pbe_selx_s {
4322 u64 reserved_24_63 : 40;
4323 u64 value : 24;
4324 } s;
4325 struct cvmx_dtx_pki_pbe_selx_s cn73xx;
4326 struct cvmx_dtx_pki_pbe_selx_s cn78xx;
4327 struct cvmx_dtx_pki_pbe_selx_s cn78xxp1;
4328 struct cvmx_dtx_pki_pbe_selx_s cnf75xx;
4329};
4330
4331typedef union cvmx_dtx_pki_pbe_selx cvmx_dtx_pki_pbe_selx_t;
4332
4333/**
4334 * cvmx_dtx_pki_pfe_bcst_rsp
4335 */
4336union cvmx_dtx_pki_pfe_bcst_rsp {
4337 u64 u64;
4338 struct cvmx_dtx_pki_pfe_bcst_rsp_s {
4339 u64 reserved_1_63 : 63;
4340 u64 ena : 1;
4341 } s;
4342 struct cvmx_dtx_pki_pfe_bcst_rsp_s cn73xx;
4343 struct cvmx_dtx_pki_pfe_bcst_rsp_s cn78xx;
4344 struct cvmx_dtx_pki_pfe_bcst_rsp_s cn78xxp1;
4345 struct cvmx_dtx_pki_pfe_bcst_rsp_s cnf75xx;
4346};
4347
4348typedef union cvmx_dtx_pki_pfe_bcst_rsp cvmx_dtx_pki_pfe_bcst_rsp_t;
4349
4350/**
4351 * cvmx_dtx_pki_pfe_ctl
4352 */
4353union cvmx_dtx_pki_pfe_ctl {
4354 u64 u64;
4355 struct cvmx_dtx_pki_pfe_ctl_s {
4356 u64 reserved_5_63 : 59;
4357 u64 active : 1;
4358 u64 reserved_2_3 : 2;
4359 u64 echoen : 1;
4360 u64 swap : 1;
4361 } s;
4362 struct cvmx_dtx_pki_pfe_ctl_s cn73xx;
4363 struct cvmx_dtx_pki_pfe_ctl_s cn78xx;
4364 struct cvmx_dtx_pki_pfe_ctl_s cn78xxp1;
4365 struct cvmx_dtx_pki_pfe_ctl_s cnf75xx;
4366};
4367
4368typedef union cvmx_dtx_pki_pfe_ctl cvmx_dtx_pki_pfe_ctl_t;
4369
4370/**
4371 * cvmx_dtx_pki_pfe_dat#
4372 */
4373union cvmx_dtx_pki_pfe_datx {
4374 u64 u64;
4375 struct cvmx_dtx_pki_pfe_datx_s {
4376 u64 reserved_36_63 : 28;
4377 u64 raw : 36;
4378 } s;
4379 struct cvmx_dtx_pki_pfe_datx_s cn73xx;
4380 struct cvmx_dtx_pki_pfe_datx_s cn78xx;
4381 struct cvmx_dtx_pki_pfe_datx_s cn78xxp1;
4382 struct cvmx_dtx_pki_pfe_datx_s cnf75xx;
4383};
4384
4385typedef union cvmx_dtx_pki_pfe_datx cvmx_dtx_pki_pfe_datx_t;
4386
4387/**
4388 * cvmx_dtx_pki_pfe_ena#
4389 */
4390union cvmx_dtx_pki_pfe_enax {
4391 u64 u64;
4392 struct cvmx_dtx_pki_pfe_enax_s {
4393 u64 reserved_36_63 : 28;
4394 u64 ena : 36;
4395 } s;
4396 struct cvmx_dtx_pki_pfe_enax_s cn73xx;
4397 struct cvmx_dtx_pki_pfe_enax_s cn78xx;
4398 struct cvmx_dtx_pki_pfe_enax_s cn78xxp1;
4399 struct cvmx_dtx_pki_pfe_enax_s cnf75xx;
4400};
4401
4402typedef union cvmx_dtx_pki_pfe_enax cvmx_dtx_pki_pfe_enax_t;
4403
4404/**
4405 * cvmx_dtx_pki_pfe_sel#
4406 */
4407union cvmx_dtx_pki_pfe_selx {
4408 u64 u64;
4409 struct cvmx_dtx_pki_pfe_selx_s {
4410 u64 reserved_24_63 : 40;
4411 u64 value : 24;
4412 } s;
4413 struct cvmx_dtx_pki_pfe_selx_s cn73xx;
4414 struct cvmx_dtx_pki_pfe_selx_s cn78xx;
4415 struct cvmx_dtx_pki_pfe_selx_s cn78xxp1;
4416 struct cvmx_dtx_pki_pfe_selx_s cnf75xx;
4417};
4418
4419typedef union cvmx_dtx_pki_pfe_selx cvmx_dtx_pki_pfe_selx_t;
4420
4421/**
4422 * cvmx_dtx_pki_pix_bcst_rsp
4423 */
4424union cvmx_dtx_pki_pix_bcst_rsp {
4425 u64 u64;
4426 struct cvmx_dtx_pki_pix_bcst_rsp_s {
4427 u64 reserved_1_63 : 63;
4428 u64 ena : 1;
4429 } s;
4430 struct cvmx_dtx_pki_pix_bcst_rsp_s cn73xx;
4431 struct cvmx_dtx_pki_pix_bcst_rsp_s cn78xx;
4432 struct cvmx_dtx_pki_pix_bcst_rsp_s cn78xxp1;
4433 struct cvmx_dtx_pki_pix_bcst_rsp_s cnf75xx;
4434};
4435
4436typedef union cvmx_dtx_pki_pix_bcst_rsp cvmx_dtx_pki_pix_bcst_rsp_t;
4437
4438/**
4439 * cvmx_dtx_pki_pix_ctl
4440 */
4441union cvmx_dtx_pki_pix_ctl {
4442 u64 u64;
4443 struct cvmx_dtx_pki_pix_ctl_s {
4444 u64 reserved_5_63 : 59;
4445 u64 active : 1;
4446 u64 reserved_2_3 : 2;
4447 u64 echoen : 1;
4448 u64 swap : 1;
4449 } s;
4450 struct cvmx_dtx_pki_pix_ctl_s cn73xx;
4451 struct cvmx_dtx_pki_pix_ctl_s cn78xx;
4452 struct cvmx_dtx_pki_pix_ctl_s cn78xxp1;
4453 struct cvmx_dtx_pki_pix_ctl_s cnf75xx;
4454};
4455
4456typedef union cvmx_dtx_pki_pix_ctl cvmx_dtx_pki_pix_ctl_t;
4457
4458/**
4459 * cvmx_dtx_pki_pix_dat#
4460 */
4461union cvmx_dtx_pki_pix_datx {
4462 u64 u64;
4463 struct cvmx_dtx_pki_pix_datx_s {
4464 u64 reserved_36_63 : 28;
4465 u64 raw : 36;
4466 } s;
4467 struct cvmx_dtx_pki_pix_datx_s cn73xx;
4468 struct cvmx_dtx_pki_pix_datx_s cn78xx;
4469 struct cvmx_dtx_pki_pix_datx_s cn78xxp1;
4470 struct cvmx_dtx_pki_pix_datx_s cnf75xx;
4471};
4472
4473typedef union cvmx_dtx_pki_pix_datx cvmx_dtx_pki_pix_datx_t;
4474
4475/**
4476 * cvmx_dtx_pki_pix_ena#
4477 */
4478union cvmx_dtx_pki_pix_enax {
4479 u64 u64;
4480 struct cvmx_dtx_pki_pix_enax_s {
4481 u64 reserved_36_63 : 28;
4482 u64 ena : 36;
4483 } s;
4484 struct cvmx_dtx_pki_pix_enax_s cn73xx;
4485 struct cvmx_dtx_pki_pix_enax_s cn78xx;
4486 struct cvmx_dtx_pki_pix_enax_s cn78xxp1;
4487 struct cvmx_dtx_pki_pix_enax_s cnf75xx;
4488};
4489
4490typedef union cvmx_dtx_pki_pix_enax cvmx_dtx_pki_pix_enax_t;
4491
4492/**
4493 * cvmx_dtx_pki_pix_sel#
4494 */
4495union cvmx_dtx_pki_pix_selx {
4496 u64 u64;
4497 struct cvmx_dtx_pki_pix_selx_s {
4498 u64 reserved_24_63 : 40;
4499 u64 value : 24;
4500 } s;
4501 struct cvmx_dtx_pki_pix_selx_s cn73xx;
4502 struct cvmx_dtx_pki_pix_selx_s cn78xx;
4503 struct cvmx_dtx_pki_pix_selx_s cn78xxp1;
4504 struct cvmx_dtx_pki_pix_selx_s cnf75xx;
4505};
4506
4507typedef union cvmx_dtx_pki_pix_selx cvmx_dtx_pki_pix_selx_t;
4508
4509/**
4510 * cvmx_dtx_pko_bcst_rsp
4511 */
4512union cvmx_dtx_pko_bcst_rsp {
4513 u64 u64;
4514 struct cvmx_dtx_pko_bcst_rsp_s {
4515 u64 reserved_1_63 : 63;
4516 u64 ena : 1;
4517 } s;
4518 struct cvmx_dtx_pko_bcst_rsp_s cn70xx;
4519 struct cvmx_dtx_pko_bcst_rsp_s cn70xxp1;
4520 struct cvmx_dtx_pko_bcst_rsp_s cn73xx;
4521 struct cvmx_dtx_pko_bcst_rsp_s cn78xx;
4522 struct cvmx_dtx_pko_bcst_rsp_s cn78xxp1;
4523 struct cvmx_dtx_pko_bcst_rsp_s cnf75xx;
4524};
4525
4526typedef union cvmx_dtx_pko_bcst_rsp cvmx_dtx_pko_bcst_rsp_t;
4527
4528/**
4529 * cvmx_dtx_pko_ctl
4530 */
4531union cvmx_dtx_pko_ctl {
4532 u64 u64;
4533 struct cvmx_dtx_pko_ctl_s {
4534 u64 reserved_5_63 : 59;
4535 u64 active : 1;
4536 u64 reserved_2_3 : 2;
4537 u64 echoen : 1;
4538 u64 swap : 1;
4539 } s;
4540 struct cvmx_dtx_pko_ctl_s cn70xx;
4541 struct cvmx_dtx_pko_ctl_s cn70xxp1;
4542 struct cvmx_dtx_pko_ctl_s cn73xx;
4543 struct cvmx_dtx_pko_ctl_s cn78xx;
4544 struct cvmx_dtx_pko_ctl_s cn78xxp1;
4545 struct cvmx_dtx_pko_ctl_s cnf75xx;
4546};
4547
4548typedef union cvmx_dtx_pko_ctl cvmx_dtx_pko_ctl_t;
4549
4550/**
4551 * cvmx_dtx_pko_dat#
4552 */
4553union cvmx_dtx_pko_datx {
4554 u64 u64;
4555 struct cvmx_dtx_pko_datx_s {
4556 u64 reserved_36_63 : 28;
4557 u64 raw : 36;
4558 } s;
4559 struct cvmx_dtx_pko_datx_s cn70xx;
4560 struct cvmx_dtx_pko_datx_s cn70xxp1;
4561 struct cvmx_dtx_pko_datx_s cn73xx;
4562 struct cvmx_dtx_pko_datx_s cn78xx;
4563 struct cvmx_dtx_pko_datx_s cn78xxp1;
4564 struct cvmx_dtx_pko_datx_s cnf75xx;
4565};
4566
4567typedef union cvmx_dtx_pko_datx cvmx_dtx_pko_datx_t;
4568
4569/**
4570 * cvmx_dtx_pko_ena#
4571 */
4572union cvmx_dtx_pko_enax {
4573 u64 u64;
4574 struct cvmx_dtx_pko_enax_s {
4575 u64 reserved_36_63 : 28;
4576 u64 ena : 36;
4577 } s;
4578 struct cvmx_dtx_pko_enax_s cn70xx;
4579 struct cvmx_dtx_pko_enax_s cn70xxp1;
4580 struct cvmx_dtx_pko_enax_s cn73xx;
4581 struct cvmx_dtx_pko_enax_s cn78xx;
4582 struct cvmx_dtx_pko_enax_s cn78xxp1;
4583 struct cvmx_dtx_pko_enax_s cnf75xx;
4584};
4585
4586typedef union cvmx_dtx_pko_enax cvmx_dtx_pko_enax_t;
4587
4588/**
4589 * cvmx_dtx_pko_sel#
4590 */
4591union cvmx_dtx_pko_selx {
4592 u64 u64;
4593 struct cvmx_dtx_pko_selx_s {
4594 u64 reserved_24_63 : 40;
4595 u64 value : 24;
4596 } s;
4597 struct cvmx_dtx_pko_selx_s cn70xx;
4598 struct cvmx_dtx_pko_selx_s cn70xxp1;
4599 struct cvmx_dtx_pko_selx_s cn73xx;
4600 struct cvmx_dtx_pko_selx_s cn78xx;
4601 struct cvmx_dtx_pko_selx_s cn78xxp1;
4602 struct cvmx_dtx_pko_selx_s cnf75xx;
4603};
4604
4605typedef union cvmx_dtx_pko_selx cvmx_dtx_pko_selx_t;
4606
4607/**
4608 * cvmx_dtx_pnb#_bcst_rsp
4609 */
4610union cvmx_dtx_pnbx_bcst_rsp {
4611 u64 u64;
4612 struct cvmx_dtx_pnbx_bcst_rsp_s {
4613 u64 reserved_1_63 : 63;
4614 u64 ena : 1;
4615 } s;
4616 struct cvmx_dtx_pnbx_bcst_rsp_s cnf75xx;
4617};
4618
4619typedef union cvmx_dtx_pnbx_bcst_rsp cvmx_dtx_pnbx_bcst_rsp_t;
4620
4621/**
4622 * cvmx_dtx_pnb#_ctl
4623 */
4624union cvmx_dtx_pnbx_ctl {
4625 u64 u64;
4626 struct cvmx_dtx_pnbx_ctl_s {
4627 u64 reserved_5_63 : 59;
4628 u64 active : 1;
4629 u64 reserved_2_3 : 2;
4630 u64 echoen : 1;
4631 u64 swap : 1;
4632 } s;
4633 struct cvmx_dtx_pnbx_ctl_s cnf75xx;
4634};
4635
4636typedef union cvmx_dtx_pnbx_ctl cvmx_dtx_pnbx_ctl_t;
4637
4638/**
4639 * cvmx_dtx_pnb#_dat#
4640 */
4641union cvmx_dtx_pnbx_datx {
4642 u64 u64;
4643 struct cvmx_dtx_pnbx_datx_s {
4644 u64 reserved_36_63 : 28;
4645 u64 raw : 36;
4646 } s;
4647 struct cvmx_dtx_pnbx_datx_s cnf75xx;
4648};
4649
4650typedef union cvmx_dtx_pnbx_datx cvmx_dtx_pnbx_datx_t;
4651
4652/**
4653 * cvmx_dtx_pnb#_ena#
4654 */
4655union cvmx_dtx_pnbx_enax {
4656 u64 u64;
4657 struct cvmx_dtx_pnbx_enax_s {
4658 u64 reserved_36_63 : 28;
4659 u64 ena : 36;
4660 } s;
4661 struct cvmx_dtx_pnbx_enax_s cnf75xx;
4662};
4663
4664typedef union cvmx_dtx_pnbx_enax cvmx_dtx_pnbx_enax_t;
4665
4666/**
4667 * cvmx_dtx_pnb#_sel#
4668 */
4669union cvmx_dtx_pnbx_selx {
4670 u64 u64;
4671 struct cvmx_dtx_pnbx_selx_s {
4672 u64 reserved_24_63 : 40;
4673 u64 value : 24;
4674 } s;
4675 struct cvmx_dtx_pnbx_selx_s cnf75xx;
4676};
4677
4678typedef union cvmx_dtx_pnbx_selx cvmx_dtx_pnbx_selx_t;
4679
4680/**
4681 * cvmx_dtx_pnbd#_bcst_rsp
4682 */
4683union cvmx_dtx_pnbdx_bcst_rsp {
4684 u64 u64;
4685 struct cvmx_dtx_pnbdx_bcst_rsp_s {
4686 u64 reserved_1_63 : 63;
4687 u64 ena : 1;
4688 } s;
4689 struct cvmx_dtx_pnbdx_bcst_rsp_s cnf75xx;
4690};
4691
4692typedef union cvmx_dtx_pnbdx_bcst_rsp cvmx_dtx_pnbdx_bcst_rsp_t;
4693
4694/**
4695 * cvmx_dtx_pnbd#_ctl
4696 */
4697union cvmx_dtx_pnbdx_ctl {
4698 u64 u64;
4699 struct cvmx_dtx_pnbdx_ctl_s {
4700 u64 reserved_5_63 : 59;
4701 u64 active : 1;
4702 u64 reserved_2_3 : 2;
4703 u64 echoen : 1;
4704 u64 swap : 1;
4705 } s;
4706 struct cvmx_dtx_pnbdx_ctl_s cnf75xx;
4707};
4708
4709typedef union cvmx_dtx_pnbdx_ctl cvmx_dtx_pnbdx_ctl_t;
4710
4711/**
4712 * cvmx_dtx_pnbd#_dat#
4713 */
4714union cvmx_dtx_pnbdx_datx {
4715 u64 u64;
4716 struct cvmx_dtx_pnbdx_datx_s {
4717 u64 reserved_36_63 : 28;
4718 u64 raw : 36;
4719 } s;
4720 struct cvmx_dtx_pnbdx_datx_s cnf75xx;
4721};
4722
4723typedef union cvmx_dtx_pnbdx_datx cvmx_dtx_pnbdx_datx_t;
4724
4725/**
4726 * cvmx_dtx_pnbd#_ena#
4727 */
4728union cvmx_dtx_pnbdx_enax {
4729 u64 u64;
4730 struct cvmx_dtx_pnbdx_enax_s {
4731 u64 reserved_36_63 : 28;
4732 u64 ena : 36;
4733 } s;
4734 struct cvmx_dtx_pnbdx_enax_s cnf75xx;
4735};
4736
4737typedef union cvmx_dtx_pnbdx_enax cvmx_dtx_pnbdx_enax_t;
4738
4739/**
4740 * cvmx_dtx_pnbd#_sel#
4741 */
4742union cvmx_dtx_pnbdx_selx {
4743 u64 u64;
4744 struct cvmx_dtx_pnbdx_selx_s {
4745 u64 reserved_24_63 : 40;
4746 u64 value : 24;
4747 } s;
4748 struct cvmx_dtx_pnbdx_selx_s cnf75xx;
4749};
4750
4751typedef union cvmx_dtx_pnbdx_selx cvmx_dtx_pnbdx_selx_t;
4752
4753/**
4754 * cvmx_dtx_pow_bcst_rsp
4755 */
4756union cvmx_dtx_pow_bcst_rsp {
4757 u64 u64;
4758 struct cvmx_dtx_pow_bcst_rsp_s {
4759 u64 reserved_1_63 : 63;
4760 u64 ena : 1;
4761 } s;
4762 struct cvmx_dtx_pow_bcst_rsp_s cn70xx;
4763 struct cvmx_dtx_pow_bcst_rsp_s cn70xxp1;
4764};
4765
4766typedef union cvmx_dtx_pow_bcst_rsp cvmx_dtx_pow_bcst_rsp_t;
4767
4768/**
4769 * cvmx_dtx_pow_ctl
4770 */
4771union cvmx_dtx_pow_ctl {
4772 u64 u64;
4773 struct cvmx_dtx_pow_ctl_s {
4774 u64 reserved_5_63 : 59;
4775 u64 active : 1;
4776 u64 reserved_2_3 : 2;
4777 u64 echoen : 1;
4778 u64 swap : 1;
4779 } s;
4780 struct cvmx_dtx_pow_ctl_s cn70xx;
4781 struct cvmx_dtx_pow_ctl_s cn70xxp1;
4782};
4783
4784typedef union cvmx_dtx_pow_ctl cvmx_dtx_pow_ctl_t;
4785
4786/**
4787 * cvmx_dtx_pow_dat#
4788 */
4789union cvmx_dtx_pow_datx {
4790 u64 u64;
4791 struct cvmx_dtx_pow_datx_s {
4792 u64 reserved_36_63 : 28;
4793 u64 raw : 36;
4794 } s;
4795 struct cvmx_dtx_pow_datx_s cn70xx;
4796 struct cvmx_dtx_pow_datx_s cn70xxp1;
4797};
4798
4799typedef union cvmx_dtx_pow_datx cvmx_dtx_pow_datx_t;
4800
4801/**
4802 * cvmx_dtx_pow_ena#
4803 */
4804union cvmx_dtx_pow_enax {
4805 u64 u64;
4806 struct cvmx_dtx_pow_enax_s {
4807 u64 reserved_36_63 : 28;
4808 u64 ena : 36;
4809 } s;
4810 struct cvmx_dtx_pow_enax_s cn70xx;
4811 struct cvmx_dtx_pow_enax_s cn70xxp1;
4812};
4813
4814typedef union cvmx_dtx_pow_enax cvmx_dtx_pow_enax_t;
4815
4816/**
4817 * cvmx_dtx_pow_sel#
4818 */
4819union cvmx_dtx_pow_selx {
4820 u64 u64;
4821 struct cvmx_dtx_pow_selx_s {
4822 u64 reserved_24_63 : 40;
4823 u64 value : 24;
4824 } s;
4825 struct cvmx_dtx_pow_selx_s cn70xx;
4826 struct cvmx_dtx_pow_selx_s cn70xxp1;
4827};
4828
4829typedef union cvmx_dtx_pow_selx cvmx_dtx_pow_selx_t;
4830
4831/**
4832 * cvmx_dtx_prch_bcst_rsp
4833 */
4834union cvmx_dtx_prch_bcst_rsp {
4835 u64 u64;
4836 struct cvmx_dtx_prch_bcst_rsp_s {
4837 u64 reserved_1_63 : 63;
4838 u64 ena : 1;
4839 } s;
4840 struct cvmx_dtx_prch_bcst_rsp_s cnf75xx;
4841};
4842
4843typedef union cvmx_dtx_prch_bcst_rsp cvmx_dtx_prch_bcst_rsp_t;
4844
4845/**
4846 * cvmx_dtx_prch_ctl
4847 */
4848union cvmx_dtx_prch_ctl {
4849 u64 u64;
4850 struct cvmx_dtx_prch_ctl_s {
4851 u64 reserved_5_63 : 59;
4852 u64 active : 1;
4853 u64 reserved_2_3 : 2;
4854 u64 echoen : 1;
4855 u64 swap : 1;
4856 } s;
4857 struct cvmx_dtx_prch_ctl_s cnf75xx;
4858};
4859
4860typedef union cvmx_dtx_prch_ctl cvmx_dtx_prch_ctl_t;
4861
4862/**
4863 * cvmx_dtx_prch_dat#
4864 */
4865union cvmx_dtx_prch_datx {
4866 u64 u64;
4867 struct cvmx_dtx_prch_datx_s {
4868 u64 reserved_36_63 : 28;
4869 u64 raw : 36;
4870 } s;
4871 struct cvmx_dtx_prch_datx_s cnf75xx;
4872};
4873
4874typedef union cvmx_dtx_prch_datx cvmx_dtx_prch_datx_t;
4875
4876/**
4877 * cvmx_dtx_prch_ena#
4878 */
4879union cvmx_dtx_prch_enax {
4880 u64 u64;
4881 struct cvmx_dtx_prch_enax_s {
4882 u64 reserved_36_63 : 28;
4883 u64 ena : 36;
4884 } s;
4885 struct cvmx_dtx_prch_enax_s cnf75xx;
4886};
4887
4888typedef union cvmx_dtx_prch_enax cvmx_dtx_prch_enax_t;
4889
4890/**
4891 * cvmx_dtx_prch_sel#
4892 */
4893union cvmx_dtx_prch_selx {
4894 u64 u64;
4895 struct cvmx_dtx_prch_selx_s {
4896 u64 reserved_24_63 : 40;
4897 u64 value : 24;
4898 } s;
4899 struct cvmx_dtx_prch_selx_s cnf75xx;
4900};
4901
4902typedef union cvmx_dtx_prch_selx cvmx_dtx_prch_selx_t;
4903
4904/**
4905 * cvmx_dtx_psm_bcst_rsp
4906 */
4907union cvmx_dtx_psm_bcst_rsp {
4908 u64 u64;
4909 struct cvmx_dtx_psm_bcst_rsp_s {
4910 u64 reserved_1_63 : 63;
4911 u64 ena : 1;
4912 } s;
4913 struct cvmx_dtx_psm_bcst_rsp_s cnf75xx;
4914};
4915
4916typedef union cvmx_dtx_psm_bcst_rsp cvmx_dtx_psm_bcst_rsp_t;
4917
4918/**
4919 * cvmx_dtx_psm_ctl
4920 */
4921union cvmx_dtx_psm_ctl {
4922 u64 u64;
4923 struct cvmx_dtx_psm_ctl_s {
4924 u64 reserved_5_63 : 59;
4925 u64 active : 1;
4926 u64 reserved_2_3 : 2;
4927 u64 echoen : 1;
4928 u64 swap : 1;
4929 } s;
4930 struct cvmx_dtx_psm_ctl_s cnf75xx;
4931};
4932
4933typedef union cvmx_dtx_psm_ctl cvmx_dtx_psm_ctl_t;
4934
4935/**
4936 * cvmx_dtx_psm_dat#
4937 */
4938union cvmx_dtx_psm_datx {
4939 u64 u64;
4940 struct cvmx_dtx_psm_datx_s {
4941 u64 reserved_36_63 : 28;
4942 u64 raw : 36;
4943 } s;
4944 struct cvmx_dtx_psm_datx_s cnf75xx;
4945};
4946
4947typedef union cvmx_dtx_psm_datx cvmx_dtx_psm_datx_t;
4948
4949/**
4950 * cvmx_dtx_psm_ena#
4951 */
4952union cvmx_dtx_psm_enax {
4953 u64 u64;
4954 struct cvmx_dtx_psm_enax_s {
4955 u64 reserved_36_63 : 28;
4956 u64 ena : 36;
4957 } s;
4958 struct cvmx_dtx_psm_enax_s cnf75xx;
4959};
4960
4961typedef union cvmx_dtx_psm_enax cvmx_dtx_psm_enax_t;
4962
4963/**
4964 * cvmx_dtx_psm_sel#
4965 */
4966union cvmx_dtx_psm_selx {
4967 u64 u64;
4968 struct cvmx_dtx_psm_selx_s {
4969 u64 reserved_24_63 : 40;
4970 u64 value : 24;
4971 } s;
4972 struct cvmx_dtx_psm_selx_s cnf75xx;
4973};
4974
4975typedef union cvmx_dtx_psm_selx cvmx_dtx_psm_selx_t;
4976
4977/**
4978 * cvmx_dtx_rad_bcst_rsp
4979 */
4980union cvmx_dtx_rad_bcst_rsp {
4981 u64 u64;
4982 struct cvmx_dtx_rad_bcst_rsp_s {
4983 u64 reserved_1_63 : 63;
4984 u64 ena : 1;
4985 } s;
4986 struct cvmx_dtx_rad_bcst_rsp_s cn73xx;
4987 struct cvmx_dtx_rad_bcst_rsp_s cn78xx;
4988 struct cvmx_dtx_rad_bcst_rsp_s cn78xxp1;
4989};
4990
4991typedef union cvmx_dtx_rad_bcst_rsp cvmx_dtx_rad_bcst_rsp_t;
4992
4993/**
4994 * cvmx_dtx_rad_ctl
4995 */
4996union cvmx_dtx_rad_ctl {
4997 u64 u64;
4998 struct cvmx_dtx_rad_ctl_s {
4999 u64 reserved_5_63 : 59;
5000 u64 active : 1;
5001 u64 reserved_2_3 : 2;
5002 u64 echoen : 1;
5003 u64 swap : 1;
5004 } s;
5005 struct cvmx_dtx_rad_ctl_s cn73xx;
5006 struct cvmx_dtx_rad_ctl_s cn78xx;
5007 struct cvmx_dtx_rad_ctl_s cn78xxp1;
5008};
5009
5010typedef union cvmx_dtx_rad_ctl cvmx_dtx_rad_ctl_t;
5011
5012/**
5013 * cvmx_dtx_rad_dat#
5014 */
5015union cvmx_dtx_rad_datx {
5016 u64 u64;
5017 struct cvmx_dtx_rad_datx_s {
5018 u64 reserved_36_63 : 28;
5019 u64 raw : 36;
5020 } s;
5021 struct cvmx_dtx_rad_datx_s cn73xx;
5022 struct cvmx_dtx_rad_datx_s cn78xx;
5023 struct cvmx_dtx_rad_datx_s cn78xxp1;
5024};
5025
5026typedef union cvmx_dtx_rad_datx cvmx_dtx_rad_datx_t;
5027
5028/**
5029 * cvmx_dtx_rad_ena#
5030 */
5031union cvmx_dtx_rad_enax {
5032 u64 u64;
5033 struct cvmx_dtx_rad_enax_s {
5034 u64 reserved_36_63 : 28;
5035 u64 ena : 36;
5036 } s;
5037 struct cvmx_dtx_rad_enax_s cn73xx;
5038 struct cvmx_dtx_rad_enax_s cn78xx;
5039 struct cvmx_dtx_rad_enax_s cn78xxp1;
5040};
5041
5042typedef union cvmx_dtx_rad_enax cvmx_dtx_rad_enax_t;
5043
5044/**
5045 * cvmx_dtx_rad_sel#
5046 */
5047union cvmx_dtx_rad_selx {
5048 u64 u64;
5049 struct cvmx_dtx_rad_selx_s {
5050 u64 reserved_24_63 : 40;
5051 u64 value : 24;
5052 } s;
5053 struct cvmx_dtx_rad_selx_s cn73xx;
5054 struct cvmx_dtx_rad_selx_s cn78xx;
5055 struct cvmx_dtx_rad_selx_s cn78xxp1;
5056};
5057
5058typedef union cvmx_dtx_rad_selx cvmx_dtx_rad_selx_t;
5059
5060/**
5061 * cvmx_dtx_rdec_bcst_rsp
5062 */
5063union cvmx_dtx_rdec_bcst_rsp {
5064 u64 u64;
5065 struct cvmx_dtx_rdec_bcst_rsp_s {
5066 u64 reserved_1_63 : 63;
5067 u64 ena : 1;
5068 } s;
5069 struct cvmx_dtx_rdec_bcst_rsp_s cnf75xx;
5070};
5071
5072typedef union cvmx_dtx_rdec_bcst_rsp cvmx_dtx_rdec_bcst_rsp_t;
5073
5074/**
5075 * cvmx_dtx_rdec_ctl
5076 */
5077union cvmx_dtx_rdec_ctl {
5078 u64 u64;
5079 struct cvmx_dtx_rdec_ctl_s {
5080 u64 reserved_5_63 : 59;
5081 u64 active : 1;
5082 u64 reserved_2_3 : 2;
5083 u64 echoen : 1;
5084 u64 swap : 1;
5085 } s;
5086 struct cvmx_dtx_rdec_ctl_s cnf75xx;
5087};
5088
5089typedef union cvmx_dtx_rdec_ctl cvmx_dtx_rdec_ctl_t;
5090
5091/**
5092 * cvmx_dtx_rdec_dat#
5093 */
5094union cvmx_dtx_rdec_datx {
5095 u64 u64;
5096 struct cvmx_dtx_rdec_datx_s {
5097 u64 reserved_36_63 : 28;
5098 u64 raw : 36;
5099 } s;
5100 struct cvmx_dtx_rdec_datx_s cnf75xx;
5101};
5102
5103typedef union cvmx_dtx_rdec_datx cvmx_dtx_rdec_datx_t;
5104
5105/**
5106 * cvmx_dtx_rdec_ena#
5107 */
5108union cvmx_dtx_rdec_enax {
5109 u64 u64;
5110 struct cvmx_dtx_rdec_enax_s {
5111 u64 reserved_36_63 : 28;
5112 u64 ena : 36;
5113 } s;
5114 struct cvmx_dtx_rdec_enax_s cnf75xx;
5115};
5116
5117typedef union cvmx_dtx_rdec_enax cvmx_dtx_rdec_enax_t;
5118
5119/**
5120 * cvmx_dtx_rdec_sel#
5121 */
5122union cvmx_dtx_rdec_selx {
5123 u64 u64;
5124 struct cvmx_dtx_rdec_selx_s {
5125 u64 reserved_24_63 : 40;
5126 u64 value : 24;
5127 } s;
5128 struct cvmx_dtx_rdec_selx_s cnf75xx;
5129};
5130
5131typedef union cvmx_dtx_rdec_selx cvmx_dtx_rdec_selx_t;
5132
5133/**
5134 * cvmx_dtx_rfif_bcst_rsp
5135 */
5136union cvmx_dtx_rfif_bcst_rsp {
5137 u64 u64;
5138 struct cvmx_dtx_rfif_bcst_rsp_s {
5139 u64 reserved_1_63 : 63;
5140 u64 ena : 1;
5141 } s;
5142 struct cvmx_dtx_rfif_bcst_rsp_s cnf75xx;
5143};
5144
5145typedef union cvmx_dtx_rfif_bcst_rsp cvmx_dtx_rfif_bcst_rsp_t;
5146
5147/**
5148 * cvmx_dtx_rfif_ctl
5149 */
5150union cvmx_dtx_rfif_ctl {
5151 u64 u64;
5152 struct cvmx_dtx_rfif_ctl_s {
5153 u64 reserved_5_63 : 59;
5154 u64 active : 1;
5155 u64 reserved_2_3 : 2;
5156 u64 echoen : 1;
5157 u64 swap : 1;
5158 } s;
5159 struct cvmx_dtx_rfif_ctl_s cnf75xx;
5160};
5161
5162typedef union cvmx_dtx_rfif_ctl cvmx_dtx_rfif_ctl_t;
5163
5164/**
5165 * cvmx_dtx_rfif_dat#
5166 */
5167union cvmx_dtx_rfif_datx {
5168 u64 u64;
5169 struct cvmx_dtx_rfif_datx_s {
5170 u64 reserved_36_63 : 28;
5171 u64 raw : 36;
5172 } s;
5173 struct cvmx_dtx_rfif_datx_s cnf75xx;
5174};
5175
5176typedef union cvmx_dtx_rfif_datx cvmx_dtx_rfif_datx_t;
5177
5178/**
5179 * cvmx_dtx_rfif_ena#
5180 */
5181union cvmx_dtx_rfif_enax {
5182 u64 u64;
5183 struct cvmx_dtx_rfif_enax_s {
5184 u64 reserved_36_63 : 28;
5185 u64 ena : 36;
5186 } s;
5187 struct cvmx_dtx_rfif_enax_s cnf75xx;
5188};
5189
5190typedef union cvmx_dtx_rfif_enax cvmx_dtx_rfif_enax_t;
5191
5192/**
5193 * cvmx_dtx_rfif_sel#
5194 */
5195union cvmx_dtx_rfif_selx {
5196 u64 u64;
5197 struct cvmx_dtx_rfif_selx_s {
5198 u64 reserved_24_63 : 40;
5199 u64 value : 24;
5200 } s;
5201 struct cvmx_dtx_rfif_selx_s cnf75xx;
5202};
5203
5204typedef union cvmx_dtx_rfif_selx cvmx_dtx_rfif_selx_t;
5205
5206/**
5207 * cvmx_dtx_rmap_bcst_rsp
5208 */
5209union cvmx_dtx_rmap_bcst_rsp {
5210 u64 u64;
5211 struct cvmx_dtx_rmap_bcst_rsp_s {
5212 u64 reserved_1_63 : 63;
5213 u64 ena : 1;
5214 } s;
5215 struct cvmx_dtx_rmap_bcst_rsp_s cnf75xx;
5216};
5217
5218typedef union cvmx_dtx_rmap_bcst_rsp cvmx_dtx_rmap_bcst_rsp_t;
5219
5220/**
5221 * cvmx_dtx_rmap_ctl
5222 */
5223union cvmx_dtx_rmap_ctl {
5224 u64 u64;
5225 struct cvmx_dtx_rmap_ctl_s {
5226 u64 reserved_5_63 : 59;
5227 u64 active : 1;
5228 u64 reserved_2_3 : 2;
5229 u64 echoen : 1;
5230 u64 swap : 1;
5231 } s;
5232 struct cvmx_dtx_rmap_ctl_s cnf75xx;
5233};
5234
5235typedef union cvmx_dtx_rmap_ctl cvmx_dtx_rmap_ctl_t;
5236
5237/**
5238 * cvmx_dtx_rmap_dat#
5239 */
5240union cvmx_dtx_rmap_datx {
5241 u64 u64;
5242 struct cvmx_dtx_rmap_datx_s {
5243 u64 reserved_36_63 : 28;
5244 u64 raw : 36;
5245 } s;
5246 struct cvmx_dtx_rmap_datx_s cnf75xx;
5247};
5248
5249typedef union cvmx_dtx_rmap_datx cvmx_dtx_rmap_datx_t;
5250
5251/**
5252 * cvmx_dtx_rmap_ena#
5253 */
5254union cvmx_dtx_rmap_enax {
5255 u64 u64;
5256 struct cvmx_dtx_rmap_enax_s {
5257 u64 reserved_36_63 : 28;
5258 u64 ena : 36;
5259 } s;
5260 struct cvmx_dtx_rmap_enax_s cnf75xx;
5261};
5262
5263typedef union cvmx_dtx_rmap_enax cvmx_dtx_rmap_enax_t;
5264
5265/**
5266 * cvmx_dtx_rmap_sel#
5267 */
5268union cvmx_dtx_rmap_selx {
5269 u64 u64;
5270 struct cvmx_dtx_rmap_selx_s {
5271 u64 reserved_24_63 : 40;
5272 u64 value : 24;
5273 } s;
5274 struct cvmx_dtx_rmap_selx_s cnf75xx;
5275};
5276
5277typedef union cvmx_dtx_rmap_selx cvmx_dtx_rmap_selx_t;
5278
5279/**
5280 * cvmx_dtx_rnm_bcst_rsp
5281 */
5282union cvmx_dtx_rnm_bcst_rsp {
5283 u64 u64;
5284 struct cvmx_dtx_rnm_bcst_rsp_s {
5285 u64 reserved_1_63 : 63;
5286 u64 ena : 1;
5287 } s;
5288 struct cvmx_dtx_rnm_bcst_rsp_s cn73xx;
5289 struct cvmx_dtx_rnm_bcst_rsp_s cn78xx;
5290 struct cvmx_dtx_rnm_bcst_rsp_s cn78xxp1;
5291 struct cvmx_dtx_rnm_bcst_rsp_s cnf75xx;
5292};
5293
5294typedef union cvmx_dtx_rnm_bcst_rsp cvmx_dtx_rnm_bcst_rsp_t;
5295
5296/**
5297 * cvmx_dtx_rnm_ctl
5298 */
5299union cvmx_dtx_rnm_ctl {
5300 u64 u64;
5301 struct cvmx_dtx_rnm_ctl_s {
5302 u64 reserved_5_63 : 59;
5303 u64 active : 1;
5304 u64 reserved_2_3 : 2;
5305 u64 echoen : 1;
5306 u64 swap : 1;
5307 } s;
5308 struct cvmx_dtx_rnm_ctl_s cn73xx;
5309 struct cvmx_dtx_rnm_ctl_s cn78xx;
5310 struct cvmx_dtx_rnm_ctl_s cn78xxp1;
5311 struct cvmx_dtx_rnm_ctl_s cnf75xx;
5312};
5313
5314typedef union cvmx_dtx_rnm_ctl cvmx_dtx_rnm_ctl_t;
5315
5316/**
5317 * cvmx_dtx_rnm_dat#
5318 */
5319union cvmx_dtx_rnm_datx {
5320 u64 u64;
5321 struct cvmx_dtx_rnm_datx_s {
5322 u64 reserved_36_63 : 28;
5323 u64 raw : 36;
5324 } s;
5325 struct cvmx_dtx_rnm_datx_s cn73xx;
5326 struct cvmx_dtx_rnm_datx_s cn78xx;
5327 struct cvmx_dtx_rnm_datx_s cn78xxp1;
5328 struct cvmx_dtx_rnm_datx_s cnf75xx;
5329};
5330
5331typedef union cvmx_dtx_rnm_datx cvmx_dtx_rnm_datx_t;
5332
5333/**
5334 * cvmx_dtx_rnm_ena#
5335 */
5336union cvmx_dtx_rnm_enax {
5337 u64 u64;
5338 struct cvmx_dtx_rnm_enax_s {
5339 u64 reserved_36_63 : 28;
5340 u64 ena : 36;
5341 } s;
5342 struct cvmx_dtx_rnm_enax_s cn73xx;
5343 struct cvmx_dtx_rnm_enax_s cn78xx;
5344 struct cvmx_dtx_rnm_enax_s cn78xxp1;
5345 struct cvmx_dtx_rnm_enax_s cnf75xx;
5346};
5347
5348typedef union cvmx_dtx_rnm_enax cvmx_dtx_rnm_enax_t;
5349
5350/**
5351 * cvmx_dtx_rnm_sel#
5352 */
5353union cvmx_dtx_rnm_selx {
5354 u64 u64;
5355 struct cvmx_dtx_rnm_selx_s {
5356 u64 reserved_24_63 : 40;
5357 u64 value : 24;
5358 } s;
5359 struct cvmx_dtx_rnm_selx_s cn73xx;
5360 struct cvmx_dtx_rnm_selx_s cn78xx;
5361 struct cvmx_dtx_rnm_selx_s cn78xxp1;
5362 struct cvmx_dtx_rnm_selx_s cnf75xx;
5363};
5364
5365typedef union cvmx_dtx_rnm_selx cvmx_dtx_rnm_selx_t;
5366
5367/**
5368 * cvmx_dtx_rst_bcst_rsp
5369 */
5370union cvmx_dtx_rst_bcst_rsp {
5371 u64 u64;
5372 struct cvmx_dtx_rst_bcst_rsp_s {
5373 u64 reserved_1_63 : 63;
5374 u64 ena : 1;
5375 } s;
5376 struct cvmx_dtx_rst_bcst_rsp_s cn70xx;
5377 struct cvmx_dtx_rst_bcst_rsp_s cn70xxp1;
5378 struct cvmx_dtx_rst_bcst_rsp_s cn73xx;
5379 struct cvmx_dtx_rst_bcst_rsp_s cn78xx;
5380 struct cvmx_dtx_rst_bcst_rsp_s cn78xxp1;
5381 struct cvmx_dtx_rst_bcst_rsp_s cnf75xx;
5382};
5383
5384typedef union cvmx_dtx_rst_bcst_rsp cvmx_dtx_rst_bcst_rsp_t;
5385
5386/**
5387 * cvmx_dtx_rst_ctl
5388 */
5389union cvmx_dtx_rst_ctl {
5390 u64 u64;
5391 struct cvmx_dtx_rst_ctl_s {
5392 u64 reserved_5_63 : 59;
5393 u64 active : 1;
5394 u64 reserved_2_3 : 2;
5395 u64 echoen : 1;
5396 u64 swap : 1;
5397 } s;
5398 struct cvmx_dtx_rst_ctl_s cn70xx;
5399 struct cvmx_dtx_rst_ctl_s cn70xxp1;
5400 struct cvmx_dtx_rst_ctl_s cn73xx;
5401 struct cvmx_dtx_rst_ctl_s cn78xx;
5402 struct cvmx_dtx_rst_ctl_s cn78xxp1;
5403 struct cvmx_dtx_rst_ctl_s cnf75xx;
5404};
5405
5406typedef union cvmx_dtx_rst_ctl cvmx_dtx_rst_ctl_t;
5407
5408/**
5409 * cvmx_dtx_rst_dat#
5410 */
5411union cvmx_dtx_rst_datx {
5412 u64 u64;
5413 struct cvmx_dtx_rst_datx_s {
5414 u64 reserved_36_63 : 28;
5415 u64 raw : 36;
5416 } s;
5417 struct cvmx_dtx_rst_datx_s cn70xx;
5418 struct cvmx_dtx_rst_datx_s cn70xxp1;
5419 struct cvmx_dtx_rst_datx_s cn73xx;
5420 struct cvmx_dtx_rst_datx_s cn78xx;
5421 struct cvmx_dtx_rst_datx_s cn78xxp1;
5422 struct cvmx_dtx_rst_datx_s cnf75xx;
5423};
5424
5425typedef union cvmx_dtx_rst_datx cvmx_dtx_rst_datx_t;
5426
5427/**
5428 * cvmx_dtx_rst_ena#
5429 */
5430union cvmx_dtx_rst_enax {
5431 u64 u64;
5432 struct cvmx_dtx_rst_enax_s {
5433 u64 reserved_36_63 : 28;
5434 u64 ena : 36;
5435 } s;
5436 struct cvmx_dtx_rst_enax_s cn70xx;
5437 struct cvmx_dtx_rst_enax_s cn70xxp1;
5438 struct cvmx_dtx_rst_enax_s cn73xx;
5439 struct cvmx_dtx_rst_enax_s cn78xx;
5440 struct cvmx_dtx_rst_enax_s cn78xxp1;
5441 struct cvmx_dtx_rst_enax_s cnf75xx;
5442};
5443
5444typedef union cvmx_dtx_rst_enax cvmx_dtx_rst_enax_t;
5445
5446/**
5447 * cvmx_dtx_rst_sel#
5448 */
5449union cvmx_dtx_rst_selx {
5450 u64 u64;
5451 struct cvmx_dtx_rst_selx_s {
5452 u64 reserved_24_63 : 40;
5453 u64 value : 24;
5454 } s;
5455 struct cvmx_dtx_rst_selx_s cn70xx;
5456 struct cvmx_dtx_rst_selx_s cn70xxp1;
5457 struct cvmx_dtx_rst_selx_s cn73xx;
5458 struct cvmx_dtx_rst_selx_s cn78xx;
5459 struct cvmx_dtx_rst_selx_s cn78xxp1;
5460 struct cvmx_dtx_rst_selx_s cnf75xx;
5461};
5462
5463typedef union cvmx_dtx_rst_selx cvmx_dtx_rst_selx_t;
5464
5465/**
5466 * cvmx_dtx_sata_bcst_rsp
5467 */
5468union cvmx_dtx_sata_bcst_rsp {
5469 u64 u64;
5470 struct cvmx_dtx_sata_bcst_rsp_s {
5471 u64 reserved_1_63 : 63;
5472 u64 ena : 1;
5473 } s;
5474 struct cvmx_dtx_sata_bcst_rsp_s cn70xx;
5475 struct cvmx_dtx_sata_bcst_rsp_s cn70xxp1;
5476 struct cvmx_dtx_sata_bcst_rsp_s cn73xx;
5477};
5478
5479typedef union cvmx_dtx_sata_bcst_rsp cvmx_dtx_sata_bcst_rsp_t;
5480
5481/**
5482 * cvmx_dtx_sata_ctl
5483 */
5484union cvmx_dtx_sata_ctl {
5485 u64 u64;
5486 struct cvmx_dtx_sata_ctl_s {
5487 u64 reserved_5_63 : 59;
5488 u64 active : 1;
5489 u64 reserved_2_3 : 2;
5490 u64 echoen : 1;
5491 u64 swap : 1;
5492 } s;
5493 struct cvmx_dtx_sata_ctl_s cn70xx;
5494 struct cvmx_dtx_sata_ctl_s cn70xxp1;
5495 struct cvmx_dtx_sata_ctl_s cn73xx;
5496};
5497
5498typedef union cvmx_dtx_sata_ctl cvmx_dtx_sata_ctl_t;
5499
5500/**
5501 * cvmx_dtx_sata_dat#
5502 */
5503union cvmx_dtx_sata_datx {
5504 u64 u64;
5505 struct cvmx_dtx_sata_datx_s {
5506 u64 reserved_36_63 : 28;
5507 u64 raw : 36;
5508 } s;
5509 struct cvmx_dtx_sata_datx_s cn70xx;
5510 struct cvmx_dtx_sata_datx_s cn70xxp1;
5511 struct cvmx_dtx_sata_datx_s cn73xx;
5512};
5513
5514typedef union cvmx_dtx_sata_datx cvmx_dtx_sata_datx_t;
5515
5516/**
5517 * cvmx_dtx_sata_ena#
5518 */
5519union cvmx_dtx_sata_enax {
5520 u64 u64;
5521 struct cvmx_dtx_sata_enax_s {
5522 u64 reserved_36_63 : 28;
5523 u64 ena : 36;
5524 } s;
5525 struct cvmx_dtx_sata_enax_s cn70xx;
5526 struct cvmx_dtx_sata_enax_s cn70xxp1;
5527 struct cvmx_dtx_sata_enax_s cn73xx;
5528};
5529
5530typedef union cvmx_dtx_sata_enax cvmx_dtx_sata_enax_t;
5531
5532/**
5533 * cvmx_dtx_sata_sel#
5534 */
5535union cvmx_dtx_sata_selx {
5536 u64 u64;
5537 struct cvmx_dtx_sata_selx_s {
5538 u64 reserved_24_63 : 40;
5539 u64 value : 24;
5540 } s;
5541 struct cvmx_dtx_sata_selx_s cn70xx;
5542 struct cvmx_dtx_sata_selx_s cn70xxp1;
5543 struct cvmx_dtx_sata_selx_s cn73xx;
5544};
5545
5546typedef union cvmx_dtx_sata_selx cvmx_dtx_sata_selx_t;
5547
5548/**
5549 * cvmx_dtx_sli_bcst_rsp
5550 */
5551union cvmx_dtx_sli_bcst_rsp {
5552 u64 u64;
5553 struct cvmx_dtx_sli_bcst_rsp_s {
5554 u64 reserved_1_63 : 63;
5555 u64 ena : 1;
5556 } s;
5557 struct cvmx_dtx_sli_bcst_rsp_s cn70xx;
5558 struct cvmx_dtx_sli_bcst_rsp_s cn70xxp1;
5559 struct cvmx_dtx_sli_bcst_rsp_s cn73xx;
5560 struct cvmx_dtx_sli_bcst_rsp_s cn78xx;
5561 struct cvmx_dtx_sli_bcst_rsp_s cn78xxp1;
5562 struct cvmx_dtx_sli_bcst_rsp_s cnf75xx;
5563};
5564
5565typedef union cvmx_dtx_sli_bcst_rsp cvmx_dtx_sli_bcst_rsp_t;
5566
5567/**
5568 * cvmx_dtx_sli_ctl
5569 */
5570union cvmx_dtx_sli_ctl {
5571 u64 u64;
5572 struct cvmx_dtx_sli_ctl_s {
5573 u64 reserved_5_63 : 59;
5574 u64 active : 1;
5575 u64 reserved_2_3 : 2;
5576 u64 echoen : 1;
5577 u64 swap : 1;
5578 } s;
5579 struct cvmx_dtx_sli_ctl_s cn70xx;
5580 struct cvmx_dtx_sli_ctl_s cn70xxp1;
5581 struct cvmx_dtx_sli_ctl_s cn73xx;
5582 struct cvmx_dtx_sli_ctl_s cn78xx;
5583 struct cvmx_dtx_sli_ctl_s cn78xxp1;
5584 struct cvmx_dtx_sli_ctl_s cnf75xx;
5585};
5586
5587typedef union cvmx_dtx_sli_ctl cvmx_dtx_sli_ctl_t;
5588
5589/**
5590 * cvmx_dtx_sli_dat#
5591 */
5592union cvmx_dtx_sli_datx {
5593 u64 u64;
5594 struct cvmx_dtx_sli_datx_s {
5595 u64 reserved_36_63 : 28;
5596 u64 raw : 36;
5597 } s;
5598 struct cvmx_dtx_sli_datx_s cn70xx;
5599 struct cvmx_dtx_sli_datx_s cn70xxp1;
5600 struct cvmx_dtx_sli_datx_s cn73xx;
5601 struct cvmx_dtx_sli_datx_s cn78xx;
5602 struct cvmx_dtx_sli_datx_s cn78xxp1;
5603 struct cvmx_dtx_sli_datx_s cnf75xx;
5604};
5605
5606typedef union cvmx_dtx_sli_datx cvmx_dtx_sli_datx_t;
5607
5608/**
5609 * cvmx_dtx_sli_ena#
5610 */
5611union cvmx_dtx_sli_enax {
5612 u64 u64;
5613 struct cvmx_dtx_sli_enax_s {
5614 u64 reserved_36_63 : 28;
5615 u64 ena : 36;
5616 } s;
5617 struct cvmx_dtx_sli_enax_s cn70xx;
5618 struct cvmx_dtx_sli_enax_s cn70xxp1;
5619 struct cvmx_dtx_sli_enax_s cn73xx;
5620 struct cvmx_dtx_sli_enax_s cn78xx;
5621 struct cvmx_dtx_sli_enax_s cn78xxp1;
5622 struct cvmx_dtx_sli_enax_s cnf75xx;
5623};
5624
5625typedef union cvmx_dtx_sli_enax cvmx_dtx_sli_enax_t;
5626
5627/**
5628 * cvmx_dtx_sli_sel#
5629 */
5630union cvmx_dtx_sli_selx {
5631 u64 u64;
5632 struct cvmx_dtx_sli_selx_s {
5633 u64 reserved_24_63 : 40;
5634 u64 value : 24;
5635 } s;
5636 struct cvmx_dtx_sli_selx_s cn70xx;
5637 struct cvmx_dtx_sli_selx_s cn70xxp1;
5638 struct cvmx_dtx_sli_selx_s cn73xx;
5639 struct cvmx_dtx_sli_selx_s cn78xx;
5640 struct cvmx_dtx_sli_selx_s cn78xxp1;
5641 struct cvmx_dtx_sli_selx_s cnf75xx;
5642};
5643
5644typedef union cvmx_dtx_sli_selx cvmx_dtx_sli_selx_t;
5645
5646/**
5647 * cvmx_dtx_spem_bcst_rsp
5648 */
5649union cvmx_dtx_spem_bcst_rsp {
5650 u64 u64;
5651 struct cvmx_dtx_spem_bcst_rsp_s {
5652 u64 reserved_1_63 : 63;
5653 u64 ena : 1;
5654 } s;
5655 struct cvmx_dtx_spem_bcst_rsp_s cn73xx;
5656};
5657
5658typedef union cvmx_dtx_spem_bcst_rsp cvmx_dtx_spem_bcst_rsp_t;
5659
5660/**
5661 * cvmx_dtx_spem_ctl
5662 */
5663union cvmx_dtx_spem_ctl {
5664 u64 u64;
5665 struct cvmx_dtx_spem_ctl_s {
5666 u64 reserved_5_63 : 59;
5667 u64 active : 1;
5668 u64 reserved_2_3 : 2;
5669 u64 echoen : 1;
5670 u64 swap : 1;
5671 } s;
5672 struct cvmx_dtx_spem_ctl_s cn73xx;
5673};
5674
5675typedef union cvmx_dtx_spem_ctl cvmx_dtx_spem_ctl_t;
5676
5677/**
5678 * cvmx_dtx_spem_dat#
5679 */
5680union cvmx_dtx_spem_datx {
5681 u64 u64;
5682 struct cvmx_dtx_spem_datx_s {
5683 u64 reserved_36_63 : 28;
5684 u64 raw : 36;
5685 } s;
5686 struct cvmx_dtx_spem_datx_s cn73xx;
5687};
5688
5689typedef union cvmx_dtx_spem_datx cvmx_dtx_spem_datx_t;
5690
5691/**
5692 * cvmx_dtx_spem_ena#
5693 */
5694union cvmx_dtx_spem_enax {
5695 u64 u64;
5696 struct cvmx_dtx_spem_enax_s {
5697 u64 reserved_36_63 : 28;
5698 u64 ena : 36;
5699 } s;
5700 struct cvmx_dtx_spem_enax_s cn73xx;
5701};
5702
5703typedef union cvmx_dtx_spem_enax cvmx_dtx_spem_enax_t;
5704
5705/**
5706 * cvmx_dtx_spem_sel#
5707 */
5708union cvmx_dtx_spem_selx {
5709 u64 u64;
5710 struct cvmx_dtx_spem_selx_s {
5711 u64 reserved_24_63 : 40;
5712 u64 value : 24;
5713 } s;
5714 struct cvmx_dtx_spem_selx_s cn73xx;
5715};
5716
5717typedef union cvmx_dtx_spem_selx cvmx_dtx_spem_selx_t;
5718
5719/**
5720 * cvmx_dtx_srio#_bcst_rsp
5721 */
5722union cvmx_dtx_sriox_bcst_rsp {
5723 u64 u64;
5724 struct cvmx_dtx_sriox_bcst_rsp_s {
5725 u64 reserved_1_63 : 63;
5726 u64 ena : 1;
5727 } s;
5728 struct cvmx_dtx_sriox_bcst_rsp_s cnf75xx;
5729};
5730
5731typedef union cvmx_dtx_sriox_bcst_rsp cvmx_dtx_sriox_bcst_rsp_t;
5732
5733/**
5734 * cvmx_dtx_srio#_ctl
5735 */
5736union cvmx_dtx_sriox_ctl {
5737 u64 u64;
5738 struct cvmx_dtx_sriox_ctl_s {
5739 u64 reserved_5_63 : 59;
5740 u64 active : 1;
5741 u64 reserved_2_3 : 2;
5742 u64 echoen : 1;
5743 u64 swap : 1;
5744 } s;
5745 struct cvmx_dtx_sriox_ctl_s cnf75xx;
5746};
5747
5748typedef union cvmx_dtx_sriox_ctl cvmx_dtx_sriox_ctl_t;
5749
5750/**
5751 * cvmx_dtx_srio#_dat#
5752 */
5753union cvmx_dtx_sriox_datx {
5754 u64 u64;
5755 struct cvmx_dtx_sriox_datx_s {
5756 u64 reserved_36_63 : 28;
5757 u64 raw : 36;
5758 } s;
5759 struct cvmx_dtx_sriox_datx_s cnf75xx;
5760};
5761
5762typedef union cvmx_dtx_sriox_datx cvmx_dtx_sriox_datx_t;
5763
5764/**
5765 * cvmx_dtx_srio#_ena#
5766 */
5767union cvmx_dtx_sriox_enax {
5768 u64 u64;
5769 struct cvmx_dtx_sriox_enax_s {
5770 u64 reserved_36_63 : 28;
5771 u64 ena : 36;
5772 } s;
5773 struct cvmx_dtx_sriox_enax_s cnf75xx;
5774};
5775
5776typedef union cvmx_dtx_sriox_enax cvmx_dtx_sriox_enax_t;
5777
5778/**
5779 * cvmx_dtx_srio#_sel#
5780 */
5781union cvmx_dtx_sriox_selx {
5782 u64 u64;
5783 struct cvmx_dtx_sriox_selx_s {
5784 u64 reserved_24_63 : 40;
5785 u64 value : 24;
5786 } s;
5787 struct cvmx_dtx_sriox_selx_s cnf75xx;
5788};
5789
5790typedef union cvmx_dtx_sriox_selx cvmx_dtx_sriox_selx_t;
5791
5792/**
5793 * cvmx_dtx_sso_bcst_rsp
5794 */
5795union cvmx_dtx_sso_bcst_rsp {
5796 u64 u64;
5797 struct cvmx_dtx_sso_bcst_rsp_s {
5798 u64 reserved_1_63 : 63;
5799 u64 ena : 1;
5800 } s;
5801 struct cvmx_dtx_sso_bcst_rsp_s cn73xx;
5802 struct cvmx_dtx_sso_bcst_rsp_s cn78xx;
5803 struct cvmx_dtx_sso_bcst_rsp_s cn78xxp1;
5804 struct cvmx_dtx_sso_bcst_rsp_s cnf75xx;
5805};
5806
5807typedef union cvmx_dtx_sso_bcst_rsp cvmx_dtx_sso_bcst_rsp_t;
5808
5809/**
5810 * cvmx_dtx_sso_ctl
5811 */
5812union cvmx_dtx_sso_ctl {
5813 u64 u64;
5814 struct cvmx_dtx_sso_ctl_s {
5815 u64 reserved_5_63 : 59;
5816 u64 active : 1;
5817 u64 reserved_2_3 : 2;
5818 u64 echoen : 1;
5819 u64 swap : 1;
5820 } s;
5821 struct cvmx_dtx_sso_ctl_s cn73xx;
5822 struct cvmx_dtx_sso_ctl_s cn78xx;
5823 struct cvmx_dtx_sso_ctl_s cn78xxp1;
5824 struct cvmx_dtx_sso_ctl_s cnf75xx;
5825};
5826
5827typedef union cvmx_dtx_sso_ctl cvmx_dtx_sso_ctl_t;
5828
5829/**
5830 * cvmx_dtx_sso_dat#
5831 */
5832union cvmx_dtx_sso_datx {
5833 u64 u64;
5834 struct cvmx_dtx_sso_datx_s {
5835 u64 reserved_36_63 : 28;
5836 u64 raw : 36;
5837 } s;
5838 struct cvmx_dtx_sso_datx_s cn73xx;
5839 struct cvmx_dtx_sso_datx_s cn78xx;
5840 struct cvmx_dtx_sso_datx_s cn78xxp1;
5841 struct cvmx_dtx_sso_datx_s cnf75xx;
5842};
5843
5844typedef union cvmx_dtx_sso_datx cvmx_dtx_sso_datx_t;
5845
5846/**
5847 * cvmx_dtx_sso_ena#
5848 */
5849union cvmx_dtx_sso_enax {
5850 u64 u64;
5851 struct cvmx_dtx_sso_enax_s {
5852 u64 reserved_36_63 : 28;
5853 u64 ena : 36;
5854 } s;
5855 struct cvmx_dtx_sso_enax_s cn73xx;
5856 struct cvmx_dtx_sso_enax_s cn78xx;
5857 struct cvmx_dtx_sso_enax_s cn78xxp1;
5858 struct cvmx_dtx_sso_enax_s cnf75xx;
5859};
5860
5861typedef union cvmx_dtx_sso_enax cvmx_dtx_sso_enax_t;
5862
5863/**
5864 * cvmx_dtx_sso_sel#
5865 */
5866union cvmx_dtx_sso_selx {
5867 u64 u64;
5868 struct cvmx_dtx_sso_selx_s {
5869 u64 reserved_24_63 : 40;
5870 u64 value : 24;
5871 } s;
5872 struct cvmx_dtx_sso_selx_s cn73xx;
5873 struct cvmx_dtx_sso_selx_s cn78xx;
5874 struct cvmx_dtx_sso_selx_s cn78xxp1;
5875 struct cvmx_dtx_sso_selx_s cnf75xx;
5876};
5877
5878typedef union cvmx_dtx_sso_selx cvmx_dtx_sso_selx_t;
5879
5880/**
5881 * cvmx_dtx_tdec_bcst_rsp
5882 */
5883union cvmx_dtx_tdec_bcst_rsp {
5884 u64 u64;
5885 struct cvmx_dtx_tdec_bcst_rsp_s {
5886 u64 reserved_1_63 : 63;
5887 u64 ena : 1;
5888 } s;
5889 struct cvmx_dtx_tdec_bcst_rsp_s cnf75xx;
5890};
5891
5892typedef union cvmx_dtx_tdec_bcst_rsp cvmx_dtx_tdec_bcst_rsp_t;
5893
5894/**
5895 * cvmx_dtx_tdec_ctl
5896 */
5897union cvmx_dtx_tdec_ctl {
5898 u64 u64;
5899 struct cvmx_dtx_tdec_ctl_s {
5900 u64 reserved_5_63 : 59;
5901 u64 active : 1;
5902 u64 reserved_2_3 : 2;
5903 u64 echoen : 1;
5904 u64 swap : 1;
5905 } s;
5906 struct cvmx_dtx_tdec_ctl_s cnf75xx;
5907};
5908
5909typedef union cvmx_dtx_tdec_ctl cvmx_dtx_tdec_ctl_t;
5910
5911/**
5912 * cvmx_dtx_tdec_dat#
5913 */
5914union cvmx_dtx_tdec_datx {
5915 u64 u64;
5916 struct cvmx_dtx_tdec_datx_s {
5917 u64 reserved_36_63 : 28;
5918 u64 raw : 36;
5919 } s;
5920 struct cvmx_dtx_tdec_datx_s cnf75xx;
5921};
5922
5923typedef union cvmx_dtx_tdec_datx cvmx_dtx_tdec_datx_t;
5924
5925/**
5926 * cvmx_dtx_tdec_ena#
5927 */
5928union cvmx_dtx_tdec_enax {
5929 u64 u64;
5930 struct cvmx_dtx_tdec_enax_s {
5931 u64 reserved_36_63 : 28;
5932 u64 ena : 36;
5933 } s;
5934 struct cvmx_dtx_tdec_enax_s cnf75xx;
5935};
5936
5937typedef union cvmx_dtx_tdec_enax cvmx_dtx_tdec_enax_t;
5938
5939/**
5940 * cvmx_dtx_tdec_sel#
5941 */
5942union cvmx_dtx_tdec_selx {
5943 u64 u64;
5944 struct cvmx_dtx_tdec_selx_s {
5945 u64 reserved_24_63 : 40;
5946 u64 value : 24;
5947 } s;
5948 struct cvmx_dtx_tdec_selx_s cnf75xx;
5949};
5950
5951typedef union cvmx_dtx_tdec_selx cvmx_dtx_tdec_selx_t;
5952
5953/**
5954 * cvmx_dtx_tim_bcst_rsp
5955 */
5956union cvmx_dtx_tim_bcst_rsp {
5957 u64 u64;
5958 struct cvmx_dtx_tim_bcst_rsp_s {
5959 u64 reserved_1_63 : 63;
5960 u64 ena : 1;
5961 } s;
5962 struct cvmx_dtx_tim_bcst_rsp_s cn70xx;
5963 struct cvmx_dtx_tim_bcst_rsp_s cn70xxp1;
5964 struct cvmx_dtx_tim_bcst_rsp_s cn73xx;
5965 struct cvmx_dtx_tim_bcst_rsp_s cn78xx;
5966 struct cvmx_dtx_tim_bcst_rsp_s cn78xxp1;
5967 struct cvmx_dtx_tim_bcst_rsp_s cnf75xx;
5968};
5969
5970typedef union cvmx_dtx_tim_bcst_rsp cvmx_dtx_tim_bcst_rsp_t;
5971
5972/**
5973 * cvmx_dtx_tim_ctl
5974 */
5975union cvmx_dtx_tim_ctl {
5976 u64 u64;
5977 struct cvmx_dtx_tim_ctl_s {
5978 u64 reserved_5_63 : 59;
5979 u64 active : 1;
5980 u64 reserved_2_3 : 2;
5981 u64 echoen : 1;
5982 u64 swap : 1;
5983 } s;
5984 struct cvmx_dtx_tim_ctl_s cn70xx;
5985 struct cvmx_dtx_tim_ctl_s cn70xxp1;
5986 struct cvmx_dtx_tim_ctl_s cn73xx;
5987 struct cvmx_dtx_tim_ctl_s cn78xx;
5988 struct cvmx_dtx_tim_ctl_s cn78xxp1;
5989 struct cvmx_dtx_tim_ctl_s cnf75xx;
5990};
5991
5992typedef union cvmx_dtx_tim_ctl cvmx_dtx_tim_ctl_t;
5993
5994/**
5995 * cvmx_dtx_tim_dat#
5996 */
5997union cvmx_dtx_tim_datx {
5998 u64 u64;
5999 struct cvmx_dtx_tim_datx_s {
6000 u64 reserved_36_63 : 28;
6001 u64 raw : 36;
6002 } s;
6003 struct cvmx_dtx_tim_datx_s cn70xx;
6004 struct cvmx_dtx_tim_datx_s cn70xxp1;
6005 struct cvmx_dtx_tim_datx_s cn73xx;
6006 struct cvmx_dtx_tim_datx_s cn78xx;
6007 struct cvmx_dtx_tim_datx_s cn78xxp1;
6008 struct cvmx_dtx_tim_datx_s cnf75xx;
6009};
6010
6011typedef union cvmx_dtx_tim_datx cvmx_dtx_tim_datx_t;
6012
6013/**
6014 * cvmx_dtx_tim_ena#
6015 */
6016union cvmx_dtx_tim_enax {
6017 u64 u64;
6018 struct cvmx_dtx_tim_enax_s {
6019 u64 reserved_36_63 : 28;
6020 u64 ena : 36;
6021 } s;
6022 struct cvmx_dtx_tim_enax_s cn70xx;
6023 struct cvmx_dtx_tim_enax_s cn70xxp1;
6024 struct cvmx_dtx_tim_enax_s cn73xx;
6025 struct cvmx_dtx_tim_enax_s cn78xx;
6026 struct cvmx_dtx_tim_enax_s cn78xxp1;
6027 struct cvmx_dtx_tim_enax_s cnf75xx;
6028};
6029
6030typedef union cvmx_dtx_tim_enax cvmx_dtx_tim_enax_t;
6031
6032/**
6033 * cvmx_dtx_tim_sel#
6034 */
6035union cvmx_dtx_tim_selx {
6036 u64 u64;
6037 struct cvmx_dtx_tim_selx_s {
6038 u64 reserved_24_63 : 40;
6039 u64 value : 24;
6040 } s;
6041 struct cvmx_dtx_tim_selx_s cn70xx;
6042 struct cvmx_dtx_tim_selx_s cn70xxp1;
6043 struct cvmx_dtx_tim_selx_s cn73xx;
6044 struct cvmx_dtx_tim_selx_s cn78xx;
6045 struct cvmx_dtx_tim_selx_s cn78xxp1;
6046 struct cvmx_dtx_tim_selx_s cnf75xx;
6047};
6048
6049typedef union cvmx_dtx_tim_selx cvmx_dtx_tim_selx_t;
6050
6051/**
6052 * cvmx_dtx_ulfe_bcst_rsp
6053 */
6054union cvmx_dtx_ulfe_bcst_rsp {
6055 u64 u64;
6056 struct cvmx_dtx_ulfe_bcst_rsp_s {
6057 u64 reserved_1_63 : 63;
6058 u64 ena : 1;
6059 } s;
6060 struct cvmx_dtx_ulfe_bcst_rsp_s cnf75xx;
6061};
6062
6063typedef union cvmx_dtx_ulfe_bcst_rsp cvmx_dtx_ulfe_bcst_rsp_t;
6064
6065/**
6066 * cvmx_dtx_ulfe_ctl
6067 */
6068union cvmx_dtx_ulfe_ctl {
6069 u64 u64;
6070 struct cvmx_dtx_ulfe_ctl_s {
6071 u64 reserved_5_63 : 59;
6072 u64 active : 1;
6073 u64 reserved_2_3 : 2;
6074 u64 echoen : 1;
6075 u64 swap : 1;
6076 } s;
6077 struct cvmx_dtx_ulfe_ctl_s cnf75xx;
6078};
6079
6080typedef union cvmx_dtx_ulfe_ctl cvmx_dtx_ulfe_ctl_t;
6081
6082/**
6083 * cvmx_dtx_ulfe_dat#
6084 */
6085union cvmx_dtx_ulfe_datx {
6086 u64 u64;
6087 struct cvmx_dtx_ulfe_datx_s {
6088 u64 reserved_36_63 : 28;
6089 u64 raw : 36;
6090 } s;
6091 struct cvmx_dtx_ulfe_datx_s cnf75xx;
6092};
6093
6094typedef union cvmx_dtx_ulfe_datx cvmx_dtx_ulfe_datx_t;
6095
6096/**
6097 * cvmx_dtx_ulfe_ena#
6098 */
6099union cvmx_dtx_ulfe_enax {
6100 u64 u64;
6101 struct cvmx_dtx_ulfe_enax_s {
6102 u64 reserved_36_63 : 28;
6103 u64 ena : 36;
6104 } s;
6105 struct cvmx_dtx_ulfe_enax_s cnf75xx;
6106};
6107
6108typedef union cvmx_dtx_ulfe_enax cvmx_dtx_ulfe_enax_t;
6109
6110/**
6111 * cvmx_dtx_ulfe_sel#
6112 */
6113union cvmx_dtx_ulfe_selx {
6114 u64 u64;
6115 struct cvmx_dtx_ulfe_selx_s {
6116 u64 reserved_24_63 : 40;
6117 u64 value : 24;
6118 } s;
6119 struct cvmx_dtx_ulfe_selx_s cnf75xx;
6120};
6121
6122typedef union cvmx_dtx_ulfe_selx cvmx_dtx_ulfe_selx_t;
6123
6124/**
6125 * cvmx_dtx_usbdrd#_bcst_rsp
6126 */
6127union cvmx_dtx_usbdrdx_bcst_rsp {
6128 u64 u64;
6129 struct cvmx_dtx_usbdrdx_bcst_rsp_s {
6130 u64 reserved_1_63 : 63;
6131 u64 ena : 1;
6132 } s;
6133 struct cvmx_dtx_usbdrdx_bcst_rsp_s cn70xx;
6134 struct cvmx_dtx_usbdrdx_bcst_rsp_s cn70xxp1;
6135 struct cvmx_dtx_usbdrdx_bcst_rsp_s cn73xx;
6136 struct cvmx_dtx_usbdrdx_bcst_rsp_s cnf75xx;
6137};
6138
6139typedef union cvmx_dtx_usbdrdx_bcst_rsp cvmx_dtx_usbdrdx_bcst_rsp_t;
6140
6141/**
6142 * cvmx_dtx_usbdrd#_ctl
6143 */
6144union cvmx_dtx_usbdrdx_ctl {
6145 u64 u64;
6146 struct cvmx_dtx_usbdrdx_ctl_s {
6147 u64 reserved_5_63 : 59;
6148 u64 active : 1;
6149 u64 reserved_2_3 : 2;
6150 u64 echoen : 1;
6151 u64 swap : 1;
6152 } s;
6153 struct cvmx_dtx_usbdrdx_ctl_s cn70xx;
6154 struct cvmx_dtx_usbdrdx_ctl_s cn70xxp1;
6155 struct cvmx_dtx_usbdrdx_ctl_s cn73xx;
6156 struct cvmx_dtx_usbdrdx_ctl_s cnf75xx;
6157};
6158
6159typedef union cvmx_dtx_usbdrdx_ctl cvmx_dtx_usbdrdx_ctl_t;
6160
6161/**
6162 * cvmx_dtx_usbdrd#_dat#
6163 */
6164union cvmx_dtx_usbdrdx_datx {
6165 u64 u64;
6166 struct cvmx_dtx_usbdrdx_datx_s {
6167 u64 reserved_36_63 : 28;
6168 u64 raw : 36;
6169 } s;
6170 struct cvmx_dtx_usbdrdx_datx_s cn70xx;
6171 struct cvmx_dtx_usbdrdx_datx_s cn70xxp1;
6172 struct cvmx_dtx_usbdrdx_datx_s cn73xx;
6173 struct cvmx_dtx_usbdrdx_datx_s cnf75xx;
6174};
6175
6176typedef union cvmx_dtx_usbdrdx_datx cvmx_dtx_usbdrdx_datx_t;
6177
6178/**
6179 * cvmx_dtx_usbdrd#_ena#
6180 */
6181union cvmx_dtx_usbdrdx_enax {
6182 u64 u64;
6183 struct cvmx_dtx_usbdrdx_enax_s {
6184 u64 reserved_36_63 : 28;
6185 u64 ena : 36;
6186 } s;
6187 struct cvmx_dtx_usbdrdx_enax_s cn70xx;
6188 struct cvmx_dtx_usbdrdx_enax_s cn70xxp1;
6189 struct cvmx_dtx_usbdrdx_enax_s cn73xx;
6190 struct cvmx_dtx_usbdrdx_enax_s cnf75xx;
6191};
6192
6193typedef union cvmx_dtx_usbdrdx_enax cvmx_dtx_usbdrdx_enax_t;
6194
6195/**
6196 * cvmx_dtx_usbdrd#_sel#
6197 */
6198union cvmx_dtx_usbdrdx_selx {
6199 u64 u64;
6200 struct cvmx_dtx_usbdrdx_selx_s {
6201 u64 reserved_24_63 : 40;
6202 u64 value : 24;
6203 } s;
6204 struct cvmx_dtx_usbdrdx_selx_s cn70xx;
6205 struct cvmx_dtx_usbdrdx_selx_s cn70xxp1;
6206 struct cvmx_dtx_usbdrdx_selx_s cn73xx;
6207 struct cvmx_dtx_usbdrdx_selx_s cnf75xx;
6208};
6209
6210typedef union cvmx_dtx_usbdrdx_selx cvmx_dtx_usbdrdx_selx_t;
6211
6212/**
6213 * cvmx_dtx_usbh#_bcst_rsp
6214 */
6215union cvmx_dtx_usbhx_bcst_rsp {
6216 u64 u64;
6217 struct cvmx_dtx_usbhx_bcst_rsp_s {
6218 u64 reserved_1_63 : 63;
6219 u64 ena : 1;
6220 } s;
6221 struct cvmx_dtx_usbhx_bcst_rsp_s cn78xx;
6222 struct cvmx_dtx_usbhx_bcst_rsp_s cn78xxp1;
6223};
6224
6225typedef union cvmx_dtx_usbhx_bcst_rsp cvmx_dtx_usbhx_bcst_rsp_t;
6226
6227/**
6228 * cvmx_dtx_usbh#_ctl
6229 */
6230union cvmx_dtx_usbhx_ctl {
6231 u64 u64;
6232 struct cvmx_dtx_usbhx_ctl_s {
6233 u64 reserved_5_63 : 59;
6234 u64 active : 1;
6235 u64 reserved_2_3 : 2;
6236 u64 echoen : 1;
6237 u64 swap : 1;
6238 } s;
6239 struct cvmx_dtx_usbhx_ctl_s cn78xx;
6240 struct cvmx_dtx_usbhx_ctl_s cn78xxp1;
6241};
6242
6243typedef union cvmx_dtx_usbhx_ctl cvmx_dtx_usbhx_ctl_t;
6244
6245/**
6246 * cvmx_dtx_usbh#_dat#
6247 */
6248union cvmx_dtx_usbhx_datx {
6249 u64 u64;
6250 struct cvmx_dtx_usbhx_datx_s {
6251 u64 reserved_36_63 : 28;
6252 u64 raw : 36;
6253 } s;
6254 struct cvmx_dtx_usbhx_datx_s cn78xx;
6255 struct cvmx_dtx_usbhx_datx_s cn78xxp1;
6256};
6257
6258typedef union cvmx_dtx_usbhx_datx cvmx_dtx_usbhx_datx_t;
6259
6260/**
6261 * cvmx_dtx_usbh#_ena#
6262 */
6263union cvmx_dtx_usbhx_enax {
6264 u64 u64;
6265 struct cvmx_dtx_usbhx_enax_s {
6266 u64 reserved_36_63 : 28;
6267 u64 ena : 36;
6268 } s;
6269 struct cvmx_dtx_usbhx_enax_s cn78xx;
6270 struct cvmx_dtx_usbhx_enax_s cn78xxp1;
6271};
6272
6273typedef union cvmx_dtx_usbhx_enax cvmx_dtx_usbhx_enax_t;
6274
6275/**
6276 * cvmx_dtx_usbh#_sel#
6277 */
6278union cvmx_dtx_usbhx_selx {
6279 u64 u64;
6280 struct cvmx_dtx_usbhx_selx_s {
6281 u64 reserved_24_63 : 40;
6282 u64 value : 24;
6283 } s;
6284 struct cvmx_dtx_usbhx_selx_s cn78xx;
6285 struct cvmx_dtx_usbhx_selx_s cn78xxp1;
6286};
6287
6288typedef union cvmx_dtx_usbhx_selx cvmx_dtx_usbhx_selx_t;
6289
6290/**
6291 * cvmx_dtx_vdec_bcst_rsp
6292 */
6293union cvmx_dtx_vdec_bcst_rsp {
6294 u64 u64;
6295 struct cvmx_dtx_vdec_bcst_rsp_s {
6296 u64 reserved_1_63 : 63;
6297 u64 ena : 1;
6298 } s;
6299 struct cvmx_dtx_vdec_bcst_rsp_s cnf75xx;
6300};
6301
6302typedef union cvmx_dtx_vdec_bcst_rsp cvmx_dtx_vdec_bcst_rsp_t;
6303
6304/**
6305 * cvmx_dtx_vdec_ctl
6306 */
6307union cvmx_dtx_vdec_ctl {
6308 u64 u64;
6309 struct cvmx_dtx_vdec_ctl_s {
6310 u64 reserved_5_63 : 59;
6311 u64 active : 1;
6312 u64 reserved_2_3 : 2;
6313 u64 echoen : 1;
6314 u64 swap : 1;
6315 } s;
6316 struct cvmx_dtx_vdec_ctl_s cnf75xx;
6317};
6318
6319typedef union cvmx_dtx_vdec_ctl cvmx_dtx_vdec_ctl_t;
6320
6321/**
6322 * cvmx_dtx_vdec_dat#
6323 */
6324union cvmx_dtx_vdec_datx {
6325 u64 u64;
6326 struct cvmx_dtx_vdec_datx_s {
6327 u64 reserved_36_63 : 28;
6328 u64 raw : 36;
6329 } s;
6330 struct cvmx_dtx_vdec_datx_s cnf75xx;
6331};
6332
6333typedef union cvmx_dtx_vdec_datx cvmx_dtx_vdec_datx_t;
6334
6335/**
6336 * cvmx_dtx_vdec_ena#
6337 */
6338union cvmx_dtx_vdec_enax {
6339 u64 u64;
6340 struct cvmx_dtx_vdec_enax_s {
6341 u64 reserved_36_63 : 28;
6342 u64 ena : 36;
6343 } s;
6344 struct cvmx_dtx_vdec_enax_s cnf75xx;
6345};
6346
6347typedef union cvmx_dtx_vdec_enax cvmx_dtx_vdec_enax_t;
6348
6349/**
6350 * cvmx_dtx_vdec_sel#
6351 */
6352union cvmx_dtx_vdec_selx {
6353 u64 u64;
6354 struct cvmx_dtx_vdec_selx_s {
6355 u64 reserved_24_63 : 40;
6356 u64 value : 24;
6357 } s;
6358 struct cvmx_dtx_vdec_selx_s cnf75xx;
6359};
6360
6361typedef union cvmx_dtx_vdec_selx cvmx_dtx_vdec_selx_t;
6362
6363/**
6364 * cvmx_dtx_wpse_bcst_rsp
6365 */
6366union cvmx_dtx_wpse_bcst_rsp {
6367 u64 u64;
6368 struct cvmx_dtx_wpse_bcst_rsp_s {
6369 u64 reserved_1_63 : 63;
6370 u64 ena : 1;
6371 } s;
6372 struct cvmx_dtx_wpse_bcst_rsp_s cnf75xx;
6373};
6374
6375typedef union cvmx_dtx_wpse_bcst_rsp cvmx_dtx_wpse_bcst_rsp_t;
6376
6377/**
6378 * cvmx_dtx_wpse_ctl
6379 */
6380union cvmx_dtx_wpse_ctl {
6381 u64 u64;
6382 struct cvmx_dtx_wpse_ctl_s {
6383 u64 reserved_5_63 : 59;
6384 u64 active : 1;
6385 u64 reserved_2_3 : 2;
6386 u64 echoen : 1;
6387 u64 swap : 1;
6388 } s;
6389 struct cvmx_dtx_wpse_ctl_s cnf75xx;
6390};
6391
6392typedef union cvmx_dtx_wpse_ctl cvmx_dtx_wpse_ctl_t;
6393
6394/**
6395 * cvmx_dtx_wpse_dat#
6396 */
6397union cvmx_dtx_wpse_datx {
6398 u64 u64;
6399 struct cvmx_dtx_wpse_datx_s {
6400 u64 reserved_36_63 : 28;
6401 u64 raw : 36;
6402 } s;
6403 struct cvmx_dtx_wpse_datx_s cnf75xx;
6404};
6405
6406typedef union cvmx_dtx_wpse_datx cvmx_dtx_wpse_datx_t;
6407
6408/**
6409 * cvmx_dtx_wpse_ena#
6410 */
6411union cvmx_dtx_wpse_enax {
6412 u64 u64;
6413 struct cvmx_dtx_wpse_enax_s {
6414 u64 reserved_36_63 : 28;
6415 u64 ena : 36;
6416 } s;
6417 struct cvmx_dtx_wpse_enax_s cnf75xx;
6418};
6419
6420typedef union cvmx_dtx_wpse_enax cvmx_dtx_wpse_enax_t;
6421
6422/**
6423 * cvmx_dtx_wpse_sel#
6424 */
6425union cvmx_dtx_wpse_selx {
6426 u64 u64;
6427 struct cvmx_dtx_wpse_selx_s {
6428 u64 reserved_24_63 : 40;
6429 u64 value : 24;
6430 } s;
6431 struct cvmx_dtx_wpse_selx_s cnf75xx;
6432};
6433
6434typedef union cvmx_dtx_wpse_selx cvmx_dtx_wpse_selx_t;
6435
6436/**
6437 * cvmx_dtx_wrce_bcst_rsp
6438 */
6439union cvmx_dtx_wrce_bcst_rsp {
6440 u64 u64;
6441 struct cvmx_dtx_wrce_bcst_rsp_s {
6442 u64 reserved_1_63 : 63;
6443 u64 ena : 1;
6444 } s;
6445 struct cvmx_dtx_wrce_bcst_rsp_s cnf75xx;
6446};
6447
6448typedef union cvmx_dtx_wrce_bcst_rsp cvmx_dtx_wrce_bcst_rsp_t;
6449
6450/**
6451 * cvmx_dtx_wrce_ctl
6452 */
6453union cvmx_dtx_wrce_ctl {
6454 u64 u64;
6455 struct cvmx_dtx_wrce_ctl_s {
6456 u64 reserved_5_63 : 59;
6457 u64 active : 1;
6458 u64 reserved_2_3 : 2;
6459 u64 echoen : 1;
6460 u64 swap : 1;
6461 } s;
6462 struct cvmx_dtx_wrce_ctl_s cnf75xx;
6463};
6464
6465typedef union cvmx_dtx_wrce_ctl cvmx_dtx_wrce_ctl_t;
6466
6467/**
6468 * cvmx_dtx_wrce_dat#
6469 */
6470union cvmx_dtx_wrce_datx {
6471 u64 u64;
6472 struct cvmx_dtx_wrce_datx_s {
6473 u64 reserved_36_63 : 28;
6474 u64 raw : 36;
6475 } s;
6476 struct cvmx_dtx_wrce_datx_s cnf75xx;
6477};
6478
6479typedef union cvmx_dtx_wrce_datx cvmx_dtx_wrce_datx_t;
6480
6481/**
6482 * cvmx_dtx_wrce_ena#
6483 */
6484union cvmx_dtx_wrce_enax {
6485 u64 u64;
6486 struct cvmx_dtx_wrce_enax_s {
6487 u64 reserved_36_63 : 28;
6488 u64 ena : 36;
6489 } s;
6490 struct cvmx_dtx_wrce_enax_s cnf75xx;
6491};
6492
6493typedef union cvmx_dtx_wrce_enax cvmx_dtx_wrce_enax_t;
6494
6495/**
6496 * cvmx_dtx_wrce_sel#
6497 */
6498union cvmx_dtx_wrce_selx {
6499 u64 u64;
6500 struct cvmx_dtx_wrce_selx_s {
6501 u64 reserved_24_63 : 40;
6502 u64 value : 24;
6503 } s;
6504 struct cvmx_dtx_wrce_selx_s cnf75xx;
6505};
6506
6507typedef union cvmx_dtx_wrce_selx cvmx_dtx_wrce_selx_t;
6508
6509/**
6510 * cvmx_dtx_wrde_bcst_rsp
6511 */
6512union cvmx_dtx_wrde_bcst_rsp {
6513 u64 u64;
6514 struct cvmx_dtx_wrde_bcst_rsp_s {
6515 u64 reserved_1_63 : 63;
6516 u64 ena : 1;
6517 } s;
6518 struct cvmx_dtx_wrde_bcst_rsp_s cnf75xx;
6519};
6520
6521typedef union cvmx_dtx_wrde_bcst_rsp cvmx_dtx_wrde_bcst_rsp_t;
6522
6523/**
6524 * cvmx_dtx_wrde_ctl
6525 */
6526union cvmx_dtx_wrde_ctl {
6527 u64 u64;
6528 struct cvmx_dtx_wrde_ctl_s {
6529 u64 reserved_5_63 : 59;
6530 u64 active : 1;
6531 u64 reserved_2_3 : 2;
6532 u64 echoen : 1;
6533 u64 swap : 1;
6534 } s;
6535 struct cvmx_dtx_wrde_ctl_s cnf75xx;
6536};
6537
6538typedef union cvmx_dtx_wrde_ctl cvmx_dtx_wrde_ctl_t;
6539
6540/**
6541 * cvmx_dtx_wrde_dat#
6542 */
6543union cvmx_dtx_wrde_datx {
6544 u64 u64;
6545 struct cvmx_dtx_wrde_datx_s {
6546 u64 reserved_36_63 : 28;
6547 u64 raw : 36;
6548 } s;
6549 struct cvmx_dtx_wrde_datx_s cnf75xx;
6550};
6551
6552typedef union cvmx_dtx_wrde_datx cvmx_dtx_wrde_datx_t;
6553
6554/**
6555 * cvmx_dtx_wrde_ena#
6556 */
6557union cvmx_dtx_wrde_enax {
6558 u64 u64;
6559 struct cvmx_dtx_wrde_enax_s {
6560 u64 reserved_36_63 : 28;
6561 u64 ena : 36;
6562 } s;
6563 struct cvmx_dtx_wrde_enax_s cnf75xx;
6564};
6565
6566typedef union cvmx_dtx_wrde_enax cvmx_dtx_wrde_enax_t;
6567
6568/**
6569 * cvmx_dtx_wrde_sel#
6570 */
6571union cvmx_dtx_wrde_selx {
6572 u64 u64;
6573 struct cvmx_dtx_wrde_selx_s {
6574 u64 reserved_24_63 : 40;
6575 u64 value : 24;
6576 } s;
6577 struct cvmx_dtx_wrde_selx_s cnf75xx;
6578};
6579
6580typedef union cvmx_dtx_wrde_selx cvmx_dtx_wrde_selx_t;
6581
6582/**
6583 * cvmx_dtx_wrse_bcst_rsp
6584 */
6585union cvmx_dtx_wrse_bcst_rsp {
6586 u64 u64;
6587 struct cvmx_dtx_wrse_bcst_rsp_s {
6588 u64 reserved_1_63 : 63;
6589 u64 ena : 1;
6590 } s;
6591 struct cvmx_dtx_wrse_bcst_rsp_s cnf75xx;
6592};
6593
6594typedef union cvmx_dtx_wrse_bcst_rsp cvmx_dtx_wrse_bcst_rsp_t;
6595
6596/**
6597 * cvmx_dtx_wrse_ctl
6598 */
6599union cvmx_dtx_wrse_ctl {
6600 u64 u64;
6601 struct cvmx_dtx_wrse_ctl_s {
6602 u64 reserved_5_63 : 59;
6603 u64 active : 1;
6604 u64 reserved_2_3 : 2;
6605 u64 echoen : 1;
6606 u64 swap : 1;
6607 } s;
6608 struct cvmx_dtx_wrse_ctl_s cnf75xx;
6609};
6610
6611typedef union cvmx_dtx_wrse_ctl cvmx_dtx_wrse_ctl_t;
6612
6613/**
6614 * cvmx_dtx_wrse_dat#
6615 */
6616union cvmx_dtx_wrse_datx {
6617 u64 u64;
6618 struct cvmx_dtx_wrse_datx_s {
6619 u64 reserved_36_63 : 28;
6620 u64 raw : 36;
6621 } s;
6622 struct cvmx_dtx_wrse_datx_s cnf75xx;
6623};
6624
6625typedef union cvmx_dtx_wrse_datx cvmx_dtx_wrse_datx_t;
6626
6627/**
6628 * cvmx_dtx_wrse_ena#
6629 */
6630union cvmx_dtx_wrse_enax {
6631 u64 u64;
6632 struct cvmx_dtx_wrse_enax_s {
6633 u64 reserved_36_63 : 28;
6634 u64 ena : 36;
6635 } s;
6636 struct cvmx_dtx_wrse_enax_s cnf75xx;
6637};
6638
6639typedef union cvmx_dtx_wrse_enax cvmx_dtx_wrse_enax_t;
6640
6641/**
6642 * cvmx_dtx_wrse_sel#
6643 */
6644union cvmx_dtx_wrse_selx {
6645 u64 u64;
6646 struct cvmx_dtx_wrse_selx_s {
6647 u64 reserved_24_63 : 40;
6648 u64 value : 24;
6649 } s;
6650 struct cvmx_dtx_wrse_selx_s cnf75xx;
6651};
6652
6653typedef union cvmx_dtx_wrse_selx cvmx_dtx_wrse_selx_t;
6654
6655/**
6656 * cvmx_dtx_wtxe_bcst_rsp
6657 */
6658union cvmx_dtx_wtxe_bcst_rsp {
6659 u64 u64;
6660 struct cvmx_dtx_wtxe_bcst_rsp_s {
6661 u64 reserved_1_63 : 63;
6662 u64 ena : 1;
6663 } s;
6664 struct cvmx_dtx_wtxe_bcst_rsp_s cnf75xx;
6665};
6666
6667typedef union cvmx_dtx_wtxe_bcst_rsp cvmx_dtx_wtxe_bcst_rsp_t;
6668
6669/**
6670 * cvmx_dtx_wtxe_ctl
6671 */
6672union cvmx_dtx_wtxe_ctl {
6673 u64 u64;
6674 struct cvmx_dtx_wtxe_ctl_s {
6675 u64 reserved_5_63 : 59;
6676 u64 active : 1;
6677 u64 reserved_2_3 : 2;
6678 u64 echoen : 1;
6679 u64 swap : 1;
6680 } s;
6681 struct cvmx_dtx_wtxe_ctl_s cnf75xx;
6682};
6683
6684typedef union cvmx_dtx_wtxe_ctl cvmx_dtx_wtxe_ctl_t;
6685
6686/**
6687 * cvmx_dtx_wtxe_dat#
6688 */
6689union cvmx_dtx_wtxe_datx {
6690 u64 u64;
6691 struct cvmx_dtx_wtxe_datx_s {
6692 u64 reserved_36_63 : 28;
6693 u64 raw : 36;
6694 } s;
6695 struct cvmx_dtx_wtxe_datx_s cnf75xx;
6696};
6697
6698typedef union cvmx_dtx_wtxe_datx cvmx_dtx_wtxe_datx_t;
6699
6700/**
6701 * cvmx_dtx_wtxe_ena#
6702 */
6703union cvmx_dtx_wtxe_enax {
6704 u64 u64;
6705 struct cvmx_dtx_wtxe_enax_s {
6706 u64 reserved_36_63 : 28;
6707 u64 ena : 36;
6708 } s;
6709 struct cvmx_dtx_wtxe_enax_s cnf75xx;
6710};
6711
6712typedef union cvmx_dtx_wtxe_enax cvmx_dtx_wtxe_enax_t;
6713
6714/**
6715 * cvmx_dtx_wtxe_sel#
6716 */
6717union cvmx_dtx_wtxe_selx {
6718 u64 u64;
6719 struct cvmx_dtx_wtxe_selx_s {
6720 u64 reserved_24_63 : 40;
6721 u64 value : 24;
6722 } s;
6723 struct cvmx_dtx_wtxe_selx_s cnf75xx;
6724};
6725
6726typedef union cvmx_dtx_wtxe_selx cvmx_dtx_wtxe_selx_t;
6727
6728/**
6729 * cvmx_dtx_xcv_bcst_rsp
6730 */
6731union cvmx_dtx_xcv_bcst_rsp {
6732 u64 u64;
6733 struct cvmx_dtx_xcv_bcst_rsp_s {
6734 u64 reserved_1_63 : 63;
6735 u64 ena : 1;
6736 } s;
6737 struct cvmx_dtx_xcv_bcst_rsp_s cn73xx;
6738 struct cvmx_dtx_xcv_bcst_rsp_s cnf75xx;
6739};
6740
6741typedef union cvmx_dtx_xcv_bcst_rsp cvmx_dtx_xcv_bcst_rsp_t;
6742
6743/**
6744 * cvmx_dtx_xcv_ctl
6745 */
6746union cvmx_dtx_xcv_ctl {
6747 u64 u64;
6748 struct cvmx_dtx_xcv_ctl_s {
6749 u64 reserved_5_63 : 59;
6750 u64 active : 1;
6751 u64 reserved_2_3 : 2;
6752 u64 echoen : 1;
6753 u64 swap : 1;
6754 } s;
6755 struct cvmx_dtx_xcv_ctl_s cn73xx;
6756 struct cvmx_dtx_xcv_ctl_s cnf75xx;
6757};
6758
6759typedef union cvmx_dtx_xcv_ctl cvmx_dtx_xcv_ctl_t;
6760
6761/**
6762 * cvmx_dtx_xcv_dat#
6763 */
6764union cvmx_dtx_xcv_datx {
6765 u64 u64;
6766 struct cvmx_dtx_xcv_datx_s {
6767 u64 reserved_36_63 : 28;
6768 u64 raw : 36;
6769 } s;
6770 struct cvmx_dtx_xcv_datx_s cn73xx;
6771 struct cvmx_dtx_xcv_datx_s cnf75xx;
6772};
6773
6774typedef union cvmx_dtx_xcv_datx cvmx_dtx_xcv_datx_t;
6775
6776/**
6777 * cvmx_dtx_xcv_ena#
6778 */
6779union cvmx_dtx_xcv_enax {
6780 u64 u64;
6781 struct cvmx_dtx_xcv_enax_s {
6782 u64 reserved_36_63 : 28;
6783 u64 ena : 36;
6784 } s;
6785 struct cvmx_dtx_xcv_enax_s cn73xx;
6786 struct cvmx_dtx_xcv_enax_s cnf75xx;
6787};
6788
6789typedef union cvmx_dtx_xcv_enax cvmx_dtx_xcv_enax_t;
6790
6791/**
6792 * cvmx_dtx_xcv_sel#
6793 */
6794union cvmx_dtx_xcv_selx {
6795 u64 u64;
6796 struct cvmx_dtx_xcv_selx_s {
6797 u64 reserved_24_63 : 40;
6798 u64 value : 24;
6799 } s;
6800 struct cvmx_dtx_xcv_selx_s cn73xx;
6801 struct cvmx_dtx_xcv_selx_s cnf75xx;
6802};
6803
6804typedef union cvmx_dtx_xcv_selx cvmx_dtx_xcv_selx_t;
6805
6806/**
6807 * cvmx_dtx_xsx_bcst_rsp
6808 */
6809union cvmx_dtx_xsx_bcst_rsp {
6810 u64 u64;
6811 struct cvmx_dtx_xsx_bcst_rsp_s {
6812 u64 reserved_1_63 : 63;
6813 u64 ena : 1;
6814 } s;
6815 struct cvmx_dtx_xsx_bcst_rsp_s cnf75xx;
6816};
6817
6818typedef union cvmx_dtx_xsx_bcst_rsp cvmx_dtx_xsx_bcst_rsp_t;
6819
6820/**
6821 * cvmx_dtx_xsx_ctl
6822 */
6823union cvmx_dtx_xsx_ctl {
6824 u64 u64;
6825 struct cvmx_dtx_xsx_ctl_s {
6826 u64 reserved_5_63 : 59;
6827 u64 active : 1;
6828 u64 reserved_2_3 : 2;
6829 u64 echoen : 1;
6830 u64 swap : 1;
6831 } s;
6832 struct cvmx_dtx_xsx_ctl_s cnf75xx;
6833};
6834
6835typedef union cvmx_dtx_xsx_ctl cvmx_dtx_xsx_ctl_t;
6836
6837/**
6838 * cvmx_dtx_xsx_dat#
6839 */
6840union cvmx_dtx_xsx_datx {
6841 u64 u64;
6842 struct cvmx_dtx_xsx_datx_s {
6843 u64 reserved_36_63 : 28;
6844 u64 raw : 36;
6845 } s;
6846 struct cvmx_dtx_xsx_datx_s cnf75xx;
6847};
6848
6849typedef union cvmx_dtx_xsx_datx cvmx_dtx_xsx_datx_t;
6850
6851/**
6852 * cvmx_dtx_xsx_ena#
6853 */
6854union cvmx_dtx_xsx_enax {
6855 u64 u64;
6856 struct cvmx_dtx_xsx_enax_s {
6857 u64 reserved_36_63 : 28;
6858 u64 ena : 36;
6859 } s;
6860 struct cvmx_dtx_xsx_enax_s cnf75xx;
6861};
6862
6863typedef union cvmx_dtx_xsx_enax cvmx_dtx_xsx_enax_t;
6864
6865/**
6866 * cvmx_dtx_xsx_sel#
6867 */
6868union cvmx_dtx_xsx_selx {
6869 u64 u64;
6870 struct cvmx_dtx_xsx_selx_s {
6871 u64 reserved_24_63 : 40;
6872 u64 value : 24;
6873 } s;
6874 struct cvmx_dtx_xsx_selx_s cnf75xx;
6875};
6876
6877typedef union cvmx_dtx_xsx_selx cvmx_dtx_xsx_selx_t;
6878
6879/**
6880 * cvmx_dtx_zip_bcst_rsp
6881 */
6882union cvmx_dtx_zip_bcst_rsp {
6883 u64 u64;
6884 struct cvmx_dtx_zip_bcst_rsp_s {
6885 u64 reserved_1_63 : 63;
6886 u64 ena : 1;
6887 } s;
6888 struct cvmx_dtx_zip_bcst_rsp_s cn73xx;
6889 struct cvmx_dtx_zip_bcst_rsp_s cn78xx;
6890 struct cvmx_dtx_zip_bcst_rsp_s cn78xxp1;
6891};
6892
6893typedef union cvmx_dtx_zip_bcst_rsp cvmx_dtx_zip_bcst_rsp_t;
6894
6895/**
6896 * cvmx_dtx_zip_ctl
6897 */
6898union cvmx_dtx_zip_ctl {
6899 u64 u64;
6900 struct cvmx_dtx_zip_ctl_s {
6901 u64 reserved_5_63 : 59;
6902 u64 active : 1;
6903 u64 reserved_2_3 : 2;
6904 u64 echoen : 1;
6905 u64 swap : 1;
6906 } s;
6907 struct cvmx_dtx_zip_ctl_s cn73xx;
6908 struct cvmx_dtx_zip_ctl_s cn78xx;
6909 struct cvmx_dtx_zip_ctl_s cn78xxp1;
6910};
6911
6912typedef union cvmx_dtx_zip_ctl cvmx_dtx_zip_ctl_t;
6913
6914/**
6915 * cvmx_dtx_zip_dat#
6916 */
6917union cvmx_dtx_zip_datx {
6918 u64 u64;
6919 struct cvmx_dtx_zip_datx_s {
6920 u64 reserved_36_63 : 28;
6921 u64 raw : 36;
6922 } s;
6923 struct cvmx_dtx_zip_datx_s cn73xx;
6924 struct cvmx_dtx_zip_datx_s cn78xx;
6925 struct cvmx_dtx_zip_datx_s cn78xxp1;
6926};
6927
6928typedef union cvmx_dtx_zip_datx cvmx_dtx_zip_datx_t;
6929
6930/**
6931 * cvmx_dtx_zip_ena#
6932 */
6933union cvmx_dtx_zip_enax {
6934 u64 u64;
6935 struct cvmx_dtx_zip_enax_s {
6936 u64 reserved_36_63 : 28;
6937 u64 ena : 36;
6938 } s;
6939 struct cvmx_dtx_zip_enax_s cn73xx;
6940 struct cvmx_dtx_zip_enax_s cn78xx;
6941 struct cvmx_dtx_zip_enax_s cn78xxp1;
6942};
6943
6944typedef union cvmx_dtx_zip_enax cvmx_dtx_zip_enax_t;
6945
6946/**
6947 * cvmx_dtx_zip_sel#
6948 */
6949union cvmx_dtx_zip_selx {
6950 u64 u64;
6951 struct cvmx_dtx_zip_selx_s {
6952 u64 reserved_24_63 : 40;
6953 u64 value : 24;
6954 } s;
6955 struct cvmx_dtx_zip_selx_s cn73xx;
6956 struct cvmx_dtx_zip_selx_s cn78xx;
6957 struct cvmx_dtx_zip_selx_s cn78xxp1;
6958};
6959
6960typedef union cvmx_dtx_zip_selx cvmx_dtx_zip_selx_t;
6961
6962#endif