developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 MediaTek Inc. |
| 4 | * Author: Ryder Lee <ryder.lee@mediatek.com> |
| 5 | */ |
developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 6 | #ifndef __PINCTRL_MEDIATEK_H__ |
| 7 | #define __PINCTRL_MEDIATEK_H__ |
| 8 | |
developer | 74d6901 | 2020-01-10 16:30:28 +0800 | [diff] [blame] | 9 | #define MTK_PINCTRL_V0 0x0 |
| 10 | #define MTK_PINCTRL_V1 0x1 |
| 11 | |
developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 12 | #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } |
| 13 | #define MTK_PIN(_number, _name, _drv_n) { \ |
| 14 | .number = _number, \ |
| 15 | .name = _name, \ |
| 16 | .drv_n = _drv_n, \ |
| 17 | } |
| 18 | |
| 19 | #define PINCTRL_PIN_GROUP(name, id) \ |
| 20 | { \ |
| 21 | name, \ |
| 22 | id##_pins, \ |
| 23 | ARRAY_SIZE(id##_pins), \ |
| 24 | id##_funcs, \ |
| 25 | } |
| 26 | |
| 27 | #define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ |
| 28 | _x_bits, _sz_reg, _fixed) { \ |
| 29 | .s_pin = _s_pin, \ |
| 30 | .e_pin = _e_pin, \ |
| 31 | .s_addr = _s_addr, \ |
| 32 | .x_addrs = _x_addrs, \ |
| 33 | .s_bit = _s_bit, \ |
| 34 | .x_bits = _x_bits, \ |
| 35 | .sz_reg = _sz_reg, \ |
| 36 | .fixed = _fixed, \ |
| 37 | } |
| 38 | |
| 39 | /* List these attributes which could be modified for the pin */ |
| 40 | enum { |
| 41 | PINCTRL_PIN_REG_MODE, |
| 42 | PINCTRL_PIN_REG_DIR, |
| 43 | PINCTRL_PIN_REG_DI, |
| 44 | PINCTRL_PIN_REG_DO, |
developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 45 | PINCTRL_PIN_REG_SMT, |
developer | 74d6901 | 2020-01-10 16:30:28 +0800 | [diff] [blame] | 46 | PINCTRL_PIN_REG_PD, |
| 47 | PINCTRL_PIN_REG_PU, |
| 48 | PINCTRL_PIN_REG_E4, |
| 49 | PINCTRL_PIN_REG_E8, |
| 50 | PINCTRL_PIN_REG_IES, |
developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 51 | PINCTRL_PIN_REG_PULLEN, |
| 52 | PINCTRL_PIN_REG_PULLSEL, |
| 53 | PINCTRL_PIN_REG_DRV, |
| 54 | PINCTRL_PIN_REG_MAX, |
| 55 | }; |
| 56 | |
| 57 | /* Group the pins by the driving current */ |
| 58 | enum { |
| 59 | DRV_FIXED, |
| 60 | DRV_GRP0, |
| 61 | DRV_GRP1, |
| 62 | DRV_GRP2, |
| 63 | DRV_GRP3, |
| 64 | DRV_GRP4, |
| 65 | }; |
| 66 | |
| 67 | /** |
| 68 | * struct mtk_pin_field - the structure that holds the information of the field |
| 69 | * used to describe the attribute for the pin |
| 70 | * @offset: the register offset relative to the base address |
| 71 | * @mask: the mask used to filter out the field from the register |
| 72 | * @bitpos: the start bit relative to the register |
| 73 | * @next: the indication that the field would be extended to the |
| 74 | next register |
| 75 | */ |
| 76 | struct mtk_pin_field { |
| 77 | u32 offset; |
| 78 | u32 mask; |
| 79 | u8 bitpos; |
| 80 | u8 next; |
| 81 | }; |
| 82 | |
| 83 | /** |
| 84 | * struct mtk_pin_field_calc - the structure that holds the range providing |
| 85 | * the guide used to look up the relevant field |
| 86 | * @s_pin: the start pin within the range |
| 87 | * @e_pin: the end pin within the range |
| 88 | * @s_addr: the start address for the range |
| 89 | * @x_addrs: the address distance between two consecutive registers |
| 90 | * within the range |
| 91 | * @s_bit: the start bit for the first register within the range |
| 92 | * @x_bits: the bit distance between two consecutive pins within |
| 93 | * the range |
| 94 | * @sz_reg: the size of bits in a register |
| 95 | * @fixed: the consecutive pins share the same bits with the 1st |
| 96 | * pin |
| 97 | */ |
| 98 | struct mtk_pin_field_calc { |
| 99 | u16 s_pin; |
| 100 | u16 e_pin; |
| 101 | u32 s_addr; |
| 102 | u8 x_addrs; |
| 103 | u8 s_bit; |
| 104 | u8 x_bits; |
| 105 | u8 sz_reg; |
| 106 | u8 fixed; |
| 107 | }; |
| 108 | |
| 109 | /** |
| 110 | * struct mtk_pin_reg_calc - the structure that holds all ranges used to |
| 111 | * determine which register the pin would make use of |
| 112 | * for certain pin attribute. |
| 113 | * @range: the start address for the range |
| 114 | * @nranges: the number of items in the range |
| 115 | */ |
| 116 | struct mtk_pin_reg_calc { |
| 117 | const struct mtk_pin_field_calc *range; |
| 118 | unsigned int nranges; |
| 119 | }; |
| 120 | |
| 121 | /** |
| 122 | * struct mtk_pin_desc - the structure that providing information |
| 123 | * for each pin of chips |
| 124 | * @number: unique pin number from the global pin number space |
| 125 | * @name: name for this pin |
| 126 | * @drv_n: the index with the driving group |
| 127 | */ |
| 128 | struct mtk_pin_desc { |
| 129 | unsigned int number; |
| 130 | const char *name; |
| 131 | u8 drv_n; |
| 132 | }; |
| 133 | |
| 134 | /** |
| 135 | * struct mtk_group_desc - generic pin group descriptor |
| 136 | * @name: name of the pin group |
| 137 | * @pins: array of pins that belong to the group |
| 138 | * @num_pins: number of pins in the group |
| 139 | * @data: pin controller driver specific data |
| 140 | */ |
| 141 | struct mtk_group_desc { |
| 142 | const char *name; |
| 143 | int *pins; |
| 144 | int num_pins; |
| 145 | void *data; |
| 146 | }; |
| 147 | |
| 148 | /** |
| 149 | * struct mtk_function_desc - generic function descriptor |
| 150 | * @name: name of the function |
| 151 | * @group_names: array of pin group names |
| 152 | * @num_group_names: number of pin group names |
| 153 | */ |
| 154 | struct mtk_function_desc { |
| 155 | const char *name; |
| 156 | const char * const *group_names; |
| 157 | int num_group_names; |
| 158 | }; |
| 159 | |
| 160 | /* struct mtk_pin_soc - the structure that holds SoC-specific data */ |
| 161 | struct mtk_pinctrl_soc { |
| 162 | const char *name; |
| 163 | const struct mtk_pin_reg_calc *reg_cal; |
| 164 | const struct mtk_pin_desc *pins; |
| 165 | int npins; |
| 166 | const struct mtk_group_desc *grps; |
| 167 | int ngrps; |
| 168 | const struct mtk_function_desc *funcs; |
| 169 | int nfuncs; |
developer | 74d6901 | 2020-01-10 16:30:28 +0800 | [diff] [blame] | 170 | int gpio_mode; |
| 171 | int rev; |
developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | /** |
| 175 | * struct mtk_pinctrl_priv - private data for MTK pinctrl driver |
| 176 | * |
| 177 | * @base: base address of the pinctrl device |
| 178 | * @soc: SoC specific data |
| 179 | */ |
| 180 | struct mtk_pinctrl_priv { |
| 181 | void __iomem *base; |
| 182 | struct mtk_pinctrl_soc *soc; |
| 183 | }; |
| 184 | |
| 185 | extern const struct pinctrl_ops mtk_pinctrl_ops; |
| 186 | |
developer | 5c1111c | 2018-11-15 10:07:59 +0800 | [diff] [blame] | 187 | /* A common read-modify-write helper for MediaTek chips */ |
| 188 | void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); |
developer | 84c7a63 | 2018-11-15 10:07:58 +0800 | [diff] [blame] | 189 | int mtk_pinctrl_common_probe(struct udevice *dev, |
| 190 | struct mtk_pinctrl_soc *soc); |
| 191 | |
| 192 | #endif /* __PINCTRL_MEDIATEK_H__ */ |