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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peter Howard9ed4f702015-03-23 09:19:56 +11002/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on da850evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Peter Howard9ed4f702015-03-23 09:19:56 +11009 */
10
11#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060012#include <env.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110013#include <i2c.h>
Simon Glass97589732020-05-10 11:40:02 -060014#include <init.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110015#include <net.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110016#include <asm/arch/hardware.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110018#include <asm/ti-common/davinci_nand.h>
19#include <asm/io.h>
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +020020#include <ns16550.h>
21#include <dm/platdata.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090022#include <linux/errno.h>
Simon Glass0ffb9d62017-05-31 19:47:48 -060023#include <asm/mach-types.h>
Peter Howard9ed4f702015-03-23 09:19:56 +110024#include <asm/arch/davinci_misc.h>
Masahiro Yamadab2c88682017-01-10 13:32:07 +090025#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +110026#include <mmc.h>
27#include <asm/arch/sdmmc_defs.h>
28#endif
29
30DECLARE_GLOBAL_DATA_PTR;
31
32#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
33
Masahiro Yamadab2c88682017-01-10 13:32:07 +090034#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +110035/* MMC0 pin muxer settings */
36const struct pinmux_config mmc0_pins[] = {
37 /* GP0[11] is required for SD to work on Rev 3 EVMs */
38 { pinmux(0), 8, 4 }, /* GP0[11] */
39 { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
40 { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
41 { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
42 { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
43 { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
44 { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
45 /* LCDK supports only 4-bit mode, remaining pins are not configured */
46};
47#endif
48
49/* UART pin muxer settings */
50static const struct pinmux_config uart_pins[] = {
51 { pinmux(0), 4, 6 },
52 { pinmux(0), 4, 7 },
53 { pinmux(4), 2, 4 },
54 { pinmux(4), 2, 5 }
55};
56
57#ifdef CONFIG_DRIVER_TI_EMAC
58static const struct pinmux_config emac_pins[] = {
59 { pinmux(2), 8, 1 },
60 { pinmux(2), 8, 2 },
61 { pinmux(2), 8, 3 },
62 { pinmux(2), 8, 4 },
63 { pinmux(2), 8, 5 },
64 { pinmux(2), 8, 6 },
65 { pinmux(2), 8, 7 },
66 { pinmux(3), 8, 0 },
67 { pinmux(3), 8, 1 },
68 { pinmux(3), 8, 2 },
69 { pinmux(3), 8, 3 },
70 { pinmux(3), 8, 4 },
71 { pinmux(3), 8, 5 },
72 { pinmux(3), 8, 6 },
73 { pinmux(3), 8, 7 },
74 { pinmux(4), 8, 0 },
75 { pinmux(4), 8, 1 }
76};
77#endif /* CONFIG_DRIVER_TI_EMAC */
78
79/* I2C pin muxer settings */
80static const struct pinmux_config i2c_pins[] = {
81 { pinmux(4), 2, 2 },
82 { pinmux(4), 2, 3 }
83};
84
85#ifdef CONFIG_NAND_DAVINCI
86const struct pinmux_config nand_pins[] = {
87 { pinmux(7), 1, 1 },
88 { pinmux(7), 1, 2 },
89 { pinmux(7), 1, 4 },
90 { pinmux(7), 1, 5 },
91 { pinmux(8), 1, 0 },
92 { pinmux(8), 1, 1 },
93 { pinmux(8), 1, 2 },
94 { pinmux(8), 1, 3 },
95 { pinmux(8), 1, 4 },
96 { pinmux(8), 1, 5 },
97 { pinmux(8), 1, 6 },
98 { pinmux(8), 1, 7 },
99 { pinmux(9), 1, 0 },
100 { pinmux(9), 1, 1 },
101 { pinmux(9), 1, 2 },
102 { pinmux(9), 1, 3 },
103 { pinmux(9), 1, 4 },
104 { pinmux(9), 1, 5 },
105 { pinmux(9), 1, 6 },
106 { pinmux(9), 1, 7 },
107 { pinmux(12), 1, 5 },
108 { pinmux(12), 1, 6 }
109};
110
111#endif
112
113#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
114#define HAS_RMII 1
115#else
116#define HAS_RMII 0
117#endif
118
119const struct pinmux_resource pinmuxes[] = {
120 PINMUX_ITEM(uart_pins),
121 PINMUX_ITEM(i2c_pins),
122#ifdef CONFIG_NAND_DAVINCI
123 PINMUX_ITEM(nand_pins),
124#endif
125};
126
127const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
128
129const struct lpsc_resource lpsc[] = {
130 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
131 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
132 { DAVINCI_LPSC_EMAC }, /* image download */
133 { DAVINCI_LPSC_UART2 }, /* console */
134 { DAVINCI_LPSC_GPIO },
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900135#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100136 { DAVINCI_LPSC_MMC_SD },
137#endif
138};
139
140const int lpsc_size = ARRAY_SIZE(lpsc);
141
142#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
143#define CONFIG_DA850_EVM_MAX_CPU_CLK 456000000
144#endif
145
146/*
147 * get_board_rev() - setup to pass kernel board revision information
148 * Returns:
149 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
150 * 0000b - 300 MHz
151 * 0001b - 372 MHz
152 * 0010b - 408 MHz
153 * 0011b - 456 MHz
154 */
155u32 get_board_rev(void)
156{
157 return 0;
158}
159
160int board_early_init_f(void)
161{
162 /*
163 * Power on required peripherals
164 * ARM does not have access by default to PSC0 and PSC1
165 * assuming here that the DSP bootloader has set the IOPU
166 * such that PSC access is available to ARM
167 */
168 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
169 return 1;
170
171 return 0;
172}
173
174int board_init(void)
175{
Peter Howard9ed4f702015-03-23 09:19:56 +1100176 irq_init();
Peter Howard9ed4f702015-03-23 09:19:56 +1100177
Tom Rini48157342017-01-25 20:42:35 -0500178 /* arch number of the board */
179 gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
180
Peter Howard9ed4f702015-03-23 09:19:56 +1100181 /* address of boot parameters */
182 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
183
184
185 /* setup the SUSPSRC for ARM to control emulation suspend */
186 writel(readl(&davinci_syscfg_regs->suspsrc) &
187 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
188 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
189 DAVINCI_SYSCFG_SUSPSRC_UART2),
190 &davinci_syscfg_regs->suspsrc);
191
192 /* configure pinmux settings */
193 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
194 return 1;
195
196#ifdef CONFIG_NAND_DAVINCI
197 /*
198 * NAND CS setup - cycle counts based on da850evm NAND timings in the
199 * Linux kernel @ 25MHz EMIFA
200 */
201 writel((DAVINCI_ABCR_WSETUP(15) |
202 DAVINCI_ABCR_WSTROBE(63) |
203 DAVINCI_ABCR_WHOLD(7) |
204 DAVINCI_ABCR_RSETUP(15) |
205 DAVINCI_ABCR_RSTROBE(63) |
206 DAVINCI_ABCR_RHOLD(7) |
207 DAVINCI_ABCR_TA(3) |
208 DAVINCI_ABCR_ASIZE_16BIT),
209 &davinci_emif_regs->ab2cr); /* CS3 */
210#endif
211
212
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900213#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100214 if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
215 return 1;
216#endif
217
218#ifdef CONFIG_DRIVER_TI_EMAC
219 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
220 return 1;
221 davinci_emac_mii_mode_sel(HAS_RMII);
222#endif /* CONFIG_DRIVER_TI_EMAC */
223
224 /* enable the console UART */
225 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
226 DAVINCI_UART_PWREMU_MGMT_UTRST),
227 &davinci_uart2_ctrl_regs->pwremu_mgmt);
228
229 return 0;
230}
231
Peter Howard9ed4f702015-03-23 09:19:56 +1100232#define CFG_MAC_ADDR_SPI_BUS 0
233#define CFG_MAC_ADDR_SPI_CS 0
234#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
235#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
236
237#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
238
Peter Howard9ed4f702015-03-23 09:19:56 +1100239void dsp_lpsc_on(unsigned domain, unsigned int id)
240{
241 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
242 struct davinci_psc_regs *psc_regs;
243
244 psc_regs = davinci_psc0_regs;
245 mdstat = &psc_regs->psc0.mdstat[id];
246 mdctl = &psc_regs->psc0.mdctl[id];
247 ptstat = &psc_regs->ptstat;
248 ptcmd = &psc_regs->ptcmd;
249
250 while (*ptstat & (0x1 << domain))
251 ;
252
253 if ((*mdstat & 0x1f) == 0x03)
254 return; /* Already on and enabled */
255
256 *mdctl |= 0x03;
257
258 *ptcmd = 0x1 << domain;
259
260 while (*ptstat & (0x1 << domain))
261 ;
262 while ((*mdstat & 0x1f) != 0x03)
263 ; /* Probably an overkill... */
264}
265
266static void dspwake(void)
267{
268 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
269
270 /* if the device is ARM only, return */
271 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10)
272 return;
273
Simon Glass64b723f2017-08-03 12:22:12 -0600274 if (!strcmp(env_get("dspwake"), "no"))
Peter Howard9ed4f702015-03-23 09:19:56 +1100275 return;
276
277 *resetvect++ = 0x1E000; /* DSP Idle */
278 /* clear out the next 10 words as NOP */
279 memset(resetvect, 0, sizeof(unsigned) * 10);
280
281 /* setup the DSP reset vector */
282 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE;
283
284 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
285 REG(PSC0_MDCTL + (15 * 4)) |= 0x100;
286}
287
288#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
289/**
290 * rmii_hw_init
291 *
292 */
293int rmii_hw_init(void)
294{
295 return 0;
296}
297#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
298
299int misc_init_r(void)
300{
Peter Howard9ed4f702015-03-23 09:19:56 +1100301#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
302 /* Select RMII fucntion through the expander */
303 if (rmii_hw_init())
304 printf("RMII hardware init failed!!!\n");
305#endif
306
307 dspwake();
308
309 return 0;
310}
311
Sekhar Norib8545762019-05-30 19:04:54 +0530312#if !CONFIG_IS_ENABLED(DM_MMC)
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900313#ifdef CONFIG_MMC_DAVINCI
Peter Howard9ed4f702015-03-23 09:19:56 +1100314static struct davinci_mmc mmc_sd0 = {
315 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
316 .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
317 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
Peter Howard9ed4f702015-03-23 09:19:56 +1100318};
319
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900320int board_mmc_init(struct bd_info *bis)
Peter Howard9ed4f702015-03-23 09:19:56 +1100321{
322 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
323
324 /* Add slot-0 to mmc subsystem */
325 return davinci_mmc_init(bis, &mmc_sd0);
326}
327#endif
Adam Fordd4df8142018-08-09 06:15:14 -0500328#endif
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200329
330#ifdef CONFIG_SPL_BUILD
Simon Glassb75b15b2020-12-03 16:55:23 -0700331static const struct ns16550_plat serial_pdata = {
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200332 .base = DAVINCI_UART2_BASE,
333 .reg_shift = 2,
334 .clock = 228000000,
335 .fcr = UART_FCR_DEFVAL,
336};
337
Simon Glass1d8364a2020-12-28 20:34:54 -0700338U_BOOT_DRVINFO(omapl138_uart) = {
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200339 .name = "ns16550_serial",
Simon Glass71fa5b42020-12-03 16:55:18 -0700340 .plat = &serial_pdata,
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200341};
Bartosz Golaszewskif1412ef2019-11-14 16:10:30 +0100342
Simon Glassb75b15b2020-12-03 16:55:23 -0700343static const struct davinci_mmc_plat mmc_plat = {
Faiz Abbasae01d762020-05-22 07:32:28 +0530344 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
345 .cfg = {
346 .f_min = 200000,
347 .f_max = 25000000,
348 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
349 .host_caps = MMC_MODE_4BIT,
350 .b_max = DAVINCI_MAX_BLOCKS,
351 .name = "da830-mmc",
352 },
353};
Simon Glass1d8364a2020-12-28 20:34:54 -0700354U_BOOT_DRVINFO(omapl138_mmc) = {
Walter Lozano2901ac62020-06-25 01:10:04 -0300355 .name = "ti_da830_mmc",
Simon Glassb75b15b2020-12-03 16:55:23 -0700356 .plat = &mmc_plat,
Bartosz Golaszewskif1412ef2019-11-14 16:10:30 +0100357};
358
359void spl_board_init(void)
360{
361 davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins));
362}
Bartosz Golaszewskicdba2152019-07-29 08:58:09 +0200363#endif