blob: d609262b67603512f7578cc6de604f458fb357ae [file] [log] [blame]
Yanhong Wang6a5a45d2023-03-29 11:42:17 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
5 */
6
7#include <common.h>
8#include <asm/io.h>
Yanhong Wang2b517432023-06-15 17:36:50 +08009#include <asm/sections.h>
Yanhong Wang6a5a45d2023-03-29 11:42:17 +080010#include <cpu_func.h>
Yanhong Wang2b517432023-06-15 17:36:50 +080011#include <dm.h>
Yanhong Wang6a5a45d2023-03-29 11:42:17 +080012#include <linux/bitops.h>
13
14#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000
15#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
16
17/* enable U74-mc hart1~hart4 prefetcher */
18static void enable_prefetcher(void)
19{
20 u8 hart;
21 u32 *reg;
22
23 /* JH7110 use U74MC CORE IP, it include five cores(one S7 and four U7),
24 * but only U7 cores support prefetcher configuration
25 */
26 for (hart = 1; hart < 5; hart++) {
27 reg = (void *)(u64)(JH7110_L2_PREFETCHER_BASE_ADDR
28 + hart * JH7110_L2_PREFETCHER_HART_OFFSET);
29
30 mb(); /* memory barrier */
31 setbits_le32(reg, 0x1);
32 mb(); /* memory barrier */
33 }
34}
35
36int board_init(void)
37{
38 enable_caches();
39 enable_prefetcher();
40
41 return 0;
42}
Yanhong Wang2b517432023-06-15 17:36:50 +080043
44void *board_fdt_blob_setup(int *err)
45{
46 *err = 0;
47 if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
48 if (gd->arch.firmware_fdt_addr)
49 return (ulong *)(uintptr_t)gd->arch.firmware_fdt_addr;
50 }
51
Shiji Yangeff11fa2023-08-03 09:47:17 +080052 return (ulong *)_end;
Yanhong Wang2b517432023-06-15 17:36:50 +080053}