blob: 4e1cf3a1e32bbcdb7cf0cae6524f29c60490ad9e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutc140e982011-11-08 23:18:08 +00002/*
Otavio Salvador90818622013-01-19 16:02:49 +00003 * Freescale i.MX23/i.MX28 clock setup code
Marek Vasutc140e982011-11-08 23:18:08 +00004 *
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
7 *
8 * Based on code from LTIB:
9 * Copyright (C) 2010 Freescale Semiconductor, Inc.
Marek Vasutc140e982011-11-08 23:18:08 +000010 */
11
12#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090014#include <linux/errno.h>
Marek Vasutc140e982011-11-08 23:18:08 +000015#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/imx-regs.h>
18
Otavio Salvador90818622013-01-19 16:02:49 +000019/*
20 * The PLL frequency is 480MHz and XTAL frequency is 24MHz
21 * iMX23: datasheet section 4.2
22 * iMX28: datasheet section 10.2
23 */
Marek Vasutc140e982011-11-08 23:18:08 +000024#define PLL_FREQ_KHZ 480000
25#define PLL_FREQ_COEF 18
Marek Vasutc140e982011-11-08 23:18:08 +000026#define XTAL_FREQ_KHZ 24000
27
28#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
29#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
30
Otavio Salvador90818622013-01-19 16:02:49 +000031#if defined(CONFIG_MX23)
32#define MXC_SSPCLK_MAX MXC_SSPCLK0
33#elif defined(CONFIG_MX28)
34#define MXC_SSPCLK_MAX MXC_SSPCLK3
35#endif
36
Otavio Salvador2906f942013-01-11 03:19:03 +000037static uint32_t mxs_get_pclk(void)
Marek Vasutc140e982011-11-08 23:18:08 +000038{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000039 struct mxs_clkctrl_regs *clkctrl_regs =
40 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +000041
Robert Deliendb5512c2012-02-26 12:15:07 +000042 uint32_t clkctrl, clkseq, div;
43 uint8_t clkfrac, frac;
Marek Vasutc140e982011-11-08 23:18:08 +000044
45 clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);
46
47 /* No support of fractional divider calculation */
48 if (clkctrl &
49 (CLKCTRL_CPU_DIV_XTAL_FRAC_EN | CLKCTRL_CPU_DIV_CPU_FRAC_EN)) {
50 return 0;
51 }
52
53 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
54
55 /* XTAL Path */
56 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_CPU) {
57 div = (clkctrl & CLKCTRL_CPU_DIV_XTAL_MASK) >>
58 CLKCTRL_CPU_DIV_XTAL_OFFSET;
59 return XTAL_FREQ_MHZ / div;
60 }
61
62 /* REF Path */
Robert Deliendb5512c2012-02-26 12:15:07 +000063 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
64 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
Marek Vasutc140e982011-11-08 23:18:08 +000065 div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
66 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
67}
68
Otavio Salvador2906f942013-01-11 03:19:03 +000069static uint32_t mxs_get_hclk(void)
Marek Vasutc140e982011-11-08 23:18:08 +000070{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000071 struct mxs_clkctrl_regs *clkctrl_regs =
72 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +000073
74 uint32_t div;
75 uint32_t clkctrl;
76
77 clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus);
78
79 /* No support of fractional divider calculation */
80 if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN)
81 return 0;
82
83 div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
Otavio Salvador2906f942013-01-11 03:19:03 +000084 return mxs_get_pclk() / div;
Marek Vasutc140e982011-11-08 23:18:08 +000085}
86
Otavio Salvador2906f942013-01-11 03:19:03 +000087static uint32_t mxs_get_emiclk(void)
Marek Vasutc140e982011-11-08 23:18:08 +000088{
Otavio Salvador22f4ff92012-08-05 09:05:31 +000089 struct mxs_clkctrl_regs *clkctrl_regs =
90 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +000091
Robert Deliendb5512c2012-02-26 12:15:07 +000092 uint32_t clkctrl, clkseq, div;
93 uint8_t clkfrac, frac;
Marek Vasutc140e982011-11-08 23:18:08 +000094
95 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
96 clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);
97
98 /* XTAL Path */
99 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_EMI) {
100 div = (clkctrl & CLKCTRL_EMI_DIV_XTAL_MASK) >>
101 CLKCTRL_EMI_DIV_XTAL_OFFSET;
102 return XTAL_FREQ_MHZ / div;
103 }
104
Marek Vasutc140e982011-11-08 23:18:08 +0000105 /* REF Path */
Robert Deliendb5512c2012-02-26 12:15:07 +0000106 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
107 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
Marek Vasutc140e982011-11-08 23:18:08 +0000108 div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
109 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
110}
111
Otavio Salvador2906f942013-01-11 03:19:03 +0000112static uint32_t mxs_get_gpmiclk(void)
Marek Vasutc140e982011-11-08 23:18:08 +0000113{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000114 struct mxs_clkctrl_regs *clkctrl_regs =
115 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Otavio Salvador90818622013-01-19 16:02:49 +0000116#if defined(CONFIG_MX23)
117 uint8_t *reg =
118 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
119#elif defined(CONFIG_MX28)
120 uint8_t *reg =
121 &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
122#endif
Robert Deliendb5512c2012-02-26 12:15:07 +0000123 uint32_t clkctrl, clkseq, div;
124 uint8_t clkfrac, frac;
Marek Vasutc140e982011-11-08 23:18:08 +0000125
126 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
127 clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
128
129 /* XTAL Path */
130 if (clkseq & CLKCTRL_CLKSEQ_BYPASS_GPMI) {
131 div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
132 return XTAL_FREQ_MHZ / div;
133 }
134
Marek Vasutc140e982011-11-08 23:18:08 +0000135 /* REF Path */
Otavio Salvador90818622013-01-19 16:02:49 +0000136 clkfrac = readb(reg);
Robert Deliendb5512c2012-02-26 12:15:07 +0000137 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
Marek Vasutc140e982011-11-08 23:18:08 +0000138 div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
139 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
140}
141
142/*
143 * Set IO clock frequency, in kHz
144 */
Otavio Salvador2906f942013-01-11 03:19:03 +0000145void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
Marek Vasutc140e982011-11-08 23:18:08 +0000146{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000147 struct mxs_clkctrl_regs *clkctrl_regs =
148 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +0000149 uint32_t div;
Robert Deliendb5512c2012-02-26 12:15:07 +0000150 int io_reg;
Marek Vasutc140e982011-11-08 23:18:08 +0000151
152 if (freq == 0)
153 return;
154
Robert Deliendb5512c2012-02-26 12:15:07 +0000155 if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
Marek Vasutc140e982011-11-08 23:18:08 +0000156 return;
157
158 div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;
159
160 if (div < 18)
161 div = 18;
162
163 if (div > 35)
164 div = 35;
165
Robert Deliendb5512c2012-02-26 12:15:07 +0000166 io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
167 writeb(CLKCTRL_FRAC_CLKGATE,
168 &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
169 writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
170 &clkctrl_regs->hw_clkctrl_frac0[io_reg]);
171 writeb(CLKCTRL_FRAC_CLKGATE,
172 &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
Marek Vasutc140e982011-11-08 23:18:08 +0000173}
174
175/*
176 * Get IO clock, returns IO clock in kHz
177 */
Otavio Salvador2906f942013-01-11 03:19:03 +0000178static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
Marek Vasutc140e982011-11-08 23:18:08 +0000179{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000180 struct mxs_clkctrl_regs *clkctrl_regs =
181 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Robert Deliendb5512c2012-02-26 12:15:07 +0000182 uint8_t ret;
183 int io_reg;
Marek Vasutc140e982011-11-08 23:18:08 +0000184
Robert Deliendb5512c2012-02-26 12:15:07 +0000185 if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
Marek Vasutc140e982011-11-08 23:18:08 +0000186 return 0;
187
Robert Deliendb5512c2012-02-26 12:15:07 +0000188 io_reg = CLKCTRL_FRAC0_IO0 - io; /* Register order is reversed */
Marek Vasutc140e982011-11-08 23:18:08 +0000189
Robert Deliendb5512c2012-02-26 12:15:07 +0000190 ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
191 CLKCTRL_FRAC_FRAC_MASK;
Marek Vasutc140e982011-11-08 23:18:08 +0000192
193 return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
194}
195
196/*
197 * Configure SSP clock frequency, in kHz
198 */
Otavio Salvador2906f942013-01-11 03:19:03 +0000199void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
Marek Vasutc140e982011-11-08 23:18:08 +0000200{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000201 struct mxs_clkctrl_regs *clkctrl_regs =
202 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +0000203 uint32_t clk, clkreg;
204
Otavio Salvador90818622013-01-19 16:02:49 +0000205 if (ssp > MXC_SSPCLK_MAX)
Marek Vasutc140e982011-11-08 23:18:08 +0000206 return;
207
208 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
Otavio Salvador5309b002012-08-05 09:05:30 +0000209 (ssp * sizeof(struct mxs_register_32));
Marek Vasutc140e982011-11-08 23:18:08 +0000210
211 clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
212 while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
213 ;
214
215 if (xtal)
216 clk = XTAL_FREQ_KHZ;
217 else
Otavio Salvador2906f942013-01-11 03:19:03 +0000218 clk = mxs_get_ioclk(ssp >> 1);
Marek Vasutc140e982011-11-08 23:18:08 +0000219
220 if (freq > clk)
221 return;
222
223 /* Calculate the divider and cap it if necessary */
224 clk /= freq;
225 if (clk > CLKCTRL_SSP_DIV_MASK)
226 clk = CLKCTRL_SSP_DIV_MASK;
227
228 clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
229 while (readl(clkreg) & CLKCTRL_SSP_BUSY)
230 ;
231
232 if (xtal)
233 writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
234 &clkctrl_regs->hw_clkctrl_clkseq_set);
235 else
236 writel(CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp,
237 &clkctrl_regs->hw_clkctrl_clkseq_clr);
238}
239
240/*
241 * Return SSP frequency, in kHz
242 */
Otavio Salvador2906f942013-01-11 03:19:03 +0000243static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
Marek Vasutc140e982011-11-08 23:18:08 +0000244{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000245 struct mxs_clkctrl_regs *clkctrl_regs =
246 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasutc140e982011-11-08 23:18:08 +0000247 uint32_t clkreg;
248 uint32_t clk, tmp;
249
Otavio Salvador90818622013-01-19 16:02:49 +0000250 if (ssp > MXC_SSPCLK_MAX)
Marek Vasutc140e982011-11-08 23:18:08 +0000251 return 0;
252
253 tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
254 if (tmp & (CLKCTRL_CLKSEQ_BYPASS_SSP0 << ssp))
255 return XTAL_FREQ_KHZ;
256
257 clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
Otavio Salvador5309b002012-08-05 09:05:30 +0000258 (ssp * sizeof(struct mxs_register_32));
Marek Vasutc140e982011-11-08 23:18:08 +0000259
260 tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
261
262 if (tmp == 0)
263 return 0;
264
Otavio Salvador2906f942013-01-11 03:19:03 +0000265 clk = mxs_get_ioclk(ssp >> 1);
Marek Vasutc140e982011-11-08 23:18:08 +0000266
267 return clk / tmp;
268}
269
270/*
271 * Set SSP/MMC bus frequency, in kHz)
272 */
Otavio Salvador2906f942013-01-11 03:19:03 +0000273void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
Marek Vasutc140e982011-11-08 23:18:08 +0000274{
Otavio Salvador22f4ff92012-08-05 09:05:31 +0000275 struct mxs_ssp_regs *ssp_regs;
Marek Vasuteadf3372013-02-23 02:42:58 +0000276 const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
277 const uint32_t sspclk = mxs_get_sspclk(clk);
Marek Vasutc140e982011-11-08 23:18:08 +0000278 uint32_t reg;
279 uint32_t divide, rate, tgtclk;
280
Marek Vasut96026612013-01-11 03:19:02 +0000281 ssp_regs = mxs_ssp_regs_by_bus(bus);
Marek Vasutc140e982011-11-08 23:18:08 +0000282
283 /*
284 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
285 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
286 * CLOCK_RATE could be any integer from 0 to 255.
287 */
288 for (divide = 2; divide < 254; divide += 2) {
289 rate = sspclk / freq / divide;
290 if (rate <= 256)
291 break;
292 }
293
294 tgtclk = sspclk / divide / rate;
295 while (tgtclk > freq) {
296 rate++;
297 tgtclk = sspclk / divide / rate;
298 }
299 if (rate > 256)
300 rate = 256;
301
302 /* Always set timeout the maximum */
303 reg = SSP_TIMING_TIMEOUT_MASK |
304 (divide << SSP_TIMING_CLOCK_DIVIDE_OFFSET) |
305 ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET);
306 writel(reg, &ssp_regs->hw_ssp_timing);
307
308 debug("SPI%d: Set freq rate to %d KHz (requested %d KHz)\n",
309 bus, tgtclk, freq);
310}
311
Peng Fan93320422015-10-29 15:54:39 +0800312void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq)
Marek Vasut5ace29c2013-04-28 09:20:01 +0000313{
314 struct mxs_clkctrl_regs *clkctrl_regs =
315 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
316 uint32_t fp, x, k_rest, k_best, x_best, tk;
317 int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
318
319 if (freq == 0)
320 return;
321
322#if defined(CONFIG_MX23)
323 writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
324#elif defined(CONFIG_MX28)
325 writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
326#endif
327
328 /*
329 * / 18 \ 1 1
330 * freq kHz = | 480000000 Hz * -- | * --- * ------
331 * \ x / k 1000
332 *
333 * 480000000 Hz 18
334 * ------------ * --
335 * freq kHz x
336 * k = -------------------
337 * 1000
338 */
339
340 fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
341
342 for (x = 18; x <= 35; x++) {
343 tk = fp / x;
344 if ((tk / 1000 == 0) || (tk / 1000 > 255))
345 continue;
346
347 k_rest = tk % 1000;
348
349 if (k_rest < (k_best_l % 1000)) {
350 k_best_l = tk;
351 x_best_l = x;
352 }
353
354 if (k_rest > (k_best_t % 1000)) {
355 k_best_t = tk;
356 x_best_t = x;
357 }
358 }
359
360 if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
361 k_best = k_best_l;
362 x_best = x_best_l;
363 } else {
364 k_best = k_best_t;
365 x_best = x_best_t;
366 }
367
368 k_best /= 1000;
369
370#if defined(CONFIG_MX23)
371 writeb(CLKCTRL_FRAC_CLKGATE,
372 &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
373 writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
374 &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
375 writeb(CLKCTRL_FRAC_CLKGATE,
376 &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
377
378 writel(CLKCTRL_PIX_CLKGATE,
379 &clkctrl_regs->hw_clkctrl_pix_set);
380 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
381 CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
382 k_best << CLKCTRL_PIX_DIV_OFFSET);
383
384 while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
385 ;
386#elif defined(CONFIG_MX28)
387 writeb(CLKCTRL_FRAC_CLKGATE,
388 &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
389 writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
390 &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
391 writeb(CLKCTRL_FRAC_CLKGATE,
392 &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
393
394 writel(CLKCTRL_DIS_LCDIF_CLKGATE,
395 &clkctrl_regs->hw_clkctrl_lcdif_set);
396 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
397 CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
398 k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
399
400 while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
401 ;
402#endif
403}
404
Marek Vasutc140e982011-11-08 23:18:08 +0000405uint32_t mxc_get_clock(enum mxc_clock clk)
406{
407 switch (clk) {
408 case MXC_ARM_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000409 return mxs_get_pclk() * 1000000;
Marek Vasutc140e982011-11-08 23:18:08 +0000410 case MXC_GPMI_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000411 return mxs_get_gpmiclk() * 1000000;
Marek Vasutc140e982011-11-08 23:18:08 +0000412 case MXC_AHB_CLK:
413 case MXC_IPG_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000414 return mxs_get_hclk() * 1000000;
Marek Vasutc140e982011-11-08 23:18:08 +0000415 case MXC_EMI_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000416 return mxs_get_emiclk();
Marek Vasutc140e982011-11-08 23:18:08 +0000417 case MXC_IO0_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000418 return mxs_get_ioclk(MXC_IOCLK0);
Marek Vasutc140e982011-11-08 23:18:08 +0000419 case MXC_IO1_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000420 return mxs_get_ioclk(MXC_IOCLK1);
Otavio Salvador90818622013-01-19 16:02:49 +0000421 case MXC_XTAL_CLK:
422 return XTAL_FREQ_KHZ * 1000;
Marek Vasutc140e982011-11-08 23:18:08 +0000423 case MXC_SSP0_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000424 return mxs_get_sspclk(MXC_SSPCLK0);
Otavio Salvador90818622013-01-19 16:02:49 +0000425#ifdef CONFIG_MX28
Marek Vasutc140e982011-11-08 23:18:08 +0000426 case MXC_SSP1_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000427 return mxs_get_sspclk(MXC_SSPCLK1);
Marek Vasutc140e982011-11-08 23:18:08 +0000428 case MXC_SSP2_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000429 return mxs_get_sspclk(MXC_SSPCLK2);
Marek Vasutc140e982011-11-08 23:18:08 +0000430 case MXC_SSP3_CLK:
Otavio Salvador2906f942013-01-11 03:19:03 +0000431 return mxs_get_sspclk(MXC_SSPCLK3);
Otavio Salvador90818622013-01-19 16:02:49 +0000432#endif
Marek Vasutc140e982011-11-08 23:18:08 +0000433 }
434
435 return 0;
436}