Blame - board/freescale/p1_p2_rdb_pc/Makefile - filogic/uboot

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Li Yang	5f99973	2011-07-26 09:50:46 -0500	[diff] [blame]	1	#
				2	# Copyright 2010-2011 Freescale Semiconductor, Inc.
				3	#
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	4	# SPDX-License-Identifier: GPL-2.0+
Li Yang	5f99973	2011-07-26 09:50:46 -0500	[diff] [blame]	5	#
				6
Scott Wood	c4f0d00	2012-09-20 19:05:12 -0500	[diff] [blame]	7	MINIMAL=
				8
				9	ifdef CONFIG_SPL_BUILD
				10	ifdef CONFIG_SPL_INIT_MINIMAL
				11	MINIMAL=y
				12	endif
				13	endif
				14
				15	ifdef MINIMAL
				16
Masahiro Yamada	c54b77e	2013-10-21 11:53:38 +0900	[diff] [blame]	17	obj-y += spl_minimal.o tlb.o law.o
Scott Wood	c4f0d00	2012-09-20 19:05:12 -0500	[diff] [blame]	18
				19	else
Ying Zhang	28027d7	2013-09-06 17:30:56 +0800	[diff] [blame]	20	ifdef CONFIG_SPL_BUILD
Masahiro Yamada	efe3dc0	2013-11-05 17:03:22 +0900	[diff] [blame^]	21	obj-y += spl.o
Ying Zhang	28027d7	2013-09-06 17:30:56 +0800	[diff] [blame]	22	endif
Scott Wood	c4f0d00	2012-09-20 19:05:12 -0500	[diff] [blame]	23
Masahiro Yamada	c54b77e	2013-10-21 11:53:38 +0900	[diff] [blame]	24	obj-y += p1_p2_rdb_pc.o
				25	obj-y += ddr.o
				26	obj-y += law.o
				27	obj-y += tlb.o
Li Yang	5f99973	2011-07-26 09:50:46 -0500	[diff] [blame]	28
Scott Wood	c4f0d00	2012-09-20 19:05:12 -0500	[diff] [blame]	29	endif