| Heiko Schocher | efe0419 | 2016-05-25 07:23:46 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
| 5 | * |
| 6 | * Licensed under GPLv2. |
| 7 | */ |
| 8 | |
| 9 | #include "at91sam9260.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "Atmel AT91SAM9G20 family SoC"; |
| 13 | compatible = "atmel,at91sam9g20"; |
| 14 | |
| 15 | memory { |
| 16 | reg = <0x20000000 0x08000000>; |
| 17 | }; |
| 18 | |
| 19 | sram0: sram@002ff000 { |
| 20 | status = "disabled"; |
| 21 | }; |
| 22 | |
| 23 | sram1: sram@002fc000 { |
| 24 | compatible = "mmio-sram"; |
| 25 | reg = <0x002fc000 0x8000>; |
| 26 | }; |
| 27 | |
| 28 | ahb { |
| 29 | apb { |
| 30 | i2c0: i2c@fffac000 { |
| 31 | compatible = "atmel,at91sam9g20-i2c"; |
| 32 | }; |
| 33 | |
| 34 | ssc0: ssc@fffbc000 { |
| 35 | compatible = "atmel,at91sam9rl-ssc"; |
| 36 | }; |
| 37 | |
| 38 | adc0: adc@fffe0000 { |
| 39 | atmel,adc-startup-time = <40>; |
| 40 | }; |
| 41 | |
| 42 | pmc: pmc@fffffc00 { |
| 43 | plla: pllack { |
| 44 | atmel,clk-input-range = <2000000 32000000>; |
| 45 | atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, |
| 46 | <695000000 750000000 1 0>, |
| 47 | <645000000 700000000 2 0>, |
| 48 | <595000000 650000000 3 0>, |
| 49 | <545000000 600000000 0 1>, |
| 50 | <495000000 550000000 1 1>, |
| 51 | <445000000 500000000 2 1>, |
| 52 | <400000000 450000000 3 1>; |
| 53 | }; |
| 54 | |
| 55 | pllb: pllbck { |
| 56 | compatible = "atmel,at91sam9g20-clk-pllb"; |
| 57 | atmel,clk-input-range = <2000000 32000000>; |
| 58 | atmel,pll-clk-output-ranges = <30000000 100000000 0 0>; |
| 59 | }; |
| 60 | |
| 61 | mck: masterck { |
| 62 | atmel,clk-output-range = <0 133000000>; |
| 63 | atmel,clk-divisors = <1 2 4 6>; |
| 64 | }; |
| 65 | }; |
| 66 | }; |
| 67 | }; |
| 68 | }; |