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git01.mediatek.com / filogic / uboot / efacd9f48be95ad68914709d2d5e1655568ddca6 / . / board / xilinx / versal / Makefile
blob: 2b812765ee2f0889164c043553dbf732b870e705 [file] [log] [blame]
Michal Simek4b066a12018-08-22 14:55:27 +0200[diff] [blame]1# SPDX-License-Identifier: GPL-2.0+
2#
3# (C) Copyright 2016 - 2018 Xilinx, Inc.
4# Michal Simek <michal.simek@xilinx.com>
5#
6
7obj-y := board.o