Prabhakar Kushwaha | 46c5198 | 2016-06-03 18:41:30 +0530 | [diff] [blame] | 1 | SoC overview |
| 2 | |
| 3 | 1. LS1043A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 4 | 2. LS1088A |
| 5 | 3. LS2080A |
| 6 | 4. LS1012A |
| 7 | 5. LS1046A |
| 8 | 6. LS2088A |
| 9 | 7. LS2081A |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame^] | 10 | 8. LX2160A |
Prabhakar Kushwaha | 46c5198 | 2016-06-03 18:41:30 +0530 | [diff] [blame] | 11 | |
| 12 | LS1043A |
| 13 | --------- |
| 14 | The LS1043A integrated multicore processor combines four ARM Cortex-A53 |
| 15 | processor cores with datapath acceleration optimized for L2/3 packet |
| 16 | processing, single pass security offload and robust traffic management |
| 17 | and quality of service. |
| 18 | |
| 19 | The LS1043A SoC includes the following function and features: |
| 20 | - Four 64-bit ARM Cortex-A53 CPUs |
| 21 | - 1 MB unified L2 Cache |
| 22 | - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving |
| 23 | support |
| 24 | - Data Path Acceleration Architecture (DPAA) incorporating acceleration the |
| 25 | the following functions: |
| 26 | - Packet parsing, classification, and distribution (FMan) |
| 27 | - Queue management for scheduling, packet sequencing, and congestion |
| 28 | management (QMan) |
| 29 | - Hardware buffer management for buffer allocation and de-allocation (BMan) |
| 30 | - Cryptography acceleration (SEC) |
| 31 | - Ethernet interfaces by FMan |
| 32 | - Up to 1 x XFI supporting 10G interface |
| 33 | - Up to 1 x QSGMII |
| 34 | - Up to 4 x SGMII supporting 1000Mbps |
| 35 | - Up to 2 x SGMII supporting 2500Mbps |
| 36 | - Up to 2 x RGMII supporting 1000Mbps |
| 37 | - High-speed peripheral interfaces |
| 38 | - Three PCIe 2.0 controllers, one supporting x4 operation |
| 39 | - One serial ATA (SATA 3.0) controllers |
| 40 | - Additional peripheral interfaces |
| 41 | - Three high-speed USB 3.0 controllers with integrated PHY |
| 42 | - Enhanced secure digital host controller (eSDXC/eMMC) |
| 43 | - Quad Serial Peripheral Interface (QSPI) Controller |
| 44 | - Serial peripheral interface (SPI) controller |
| 45 | - Four I2C controllers |
| 46 | - Two DUARTs |
| 47 | - Integrated flash controller supporting NAND and NOR flash |
| 48 | - QorIQ platform's trust architecture 2.1 |
| 49 | |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 50 | LS1088A |
| 51 | -------- |
| 52 | The QorIQ LS1088A processor is built on the Layerscape |
| 53 | architecture combining eight ARM A53 processor cores |
| 54 | with advanced, high-performance datapath acceleration |
| 55 | and networks, peripheral interfaces required for |
| 56 | networking, wireless infrastructure, and general-purpose |
| 57 | embedded applications. |
| 58 | |
| 59 | LS1088A is compliant with the Layerscape Chassis Generation 3. |
| 60 | |
| 61 | Features summary: |
| 62 | - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs |
| 63 | - Cores are in 2 cluster of 4-cores each |
| 64 | - 1MB L2 - Cache per cluster |
| 65 | - Cache coherent interconnect (CCI-400) |
| 66 | - 1 64-bit DDR4 SDRAM memory controller with ECC |
| 67 | - Data path acceleration architecture 2.0 (DPAA2) |
| 68 | - 4-Lane 10GHz SerDes comprising of WRIOP |
| 69 | - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART) |
| 70 | - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs |
| 71 | - QSPI, SPI, IFC2.0 supporting NAND, NOR flash |
| 72 | - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc |
| 73 | - 2 DUARTs |
| 74 | - 4 I2C, GPIO |
| 75 | - Thermal monitor unit(TMU) |
| 76 | - 4 Flextimers and 1 generic timer |
| 77 | - Support for hardware virtualization and partitioning enforcement |
| 78 | - QorIQ platform's trust architecture 3.0 |
| 79 | - Service processor (SP) provides pre-boot initialization and secure-boot |
| 80 | capabilities |
| 81 | |
Prabhakar Kushwaha | 46c5198 | 2016-06-03 18:41:30 +0530 | [diff] [blame] | 82 | LS2080A |
| 83 | -------- |
| 84 | The LS2080A integrated multicore processor combines eight ARM Cortex-A57 |
| 85 | processor cores with high-performance data path acceleration logic and network |
| 86 | and peripheral bus interfaces required for networking, telecom/datacom, |
| 87 | wireless infrastructure, and mil/aerospace applications. |
| 88 | |
| 89 | The LS2080A SoC includes the following function and features: |
| 90 | |
| 91 | - Eight 64-bit ARM Cortex-A57 CPUs |
| 92 | - 1 MB platform cache with ECC |
| 93 | - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support |
| 94 | - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by |
| 95 | the AIOP |
| 96 | - Data path acceleration architecture (DPAA2) incorporating acceleration for |
| 97 | the following functions: |
| 98 | - Packet parsing, classification, and distribution (WRIOP) |
| 99 | - Queue and Hardware buffer management for scheduling, packet sequencing, and |
| 100 | congestion management, buffer allocation and de-allocation (QBMan) |
| 101 | - Cryptography acceleration (SEC) at up to 10 Gbps |
| 102 | - RegEx pattern matching acceleration (PME) at up to 10 Gbps |
| 103 | - Decompression/compression acceleration (DCE) at up to 20 Gbps |
| 104 | - Accelerated I/O processing (AIOP) at up to 20 Gbps |
| 105 | - QDMA engine |
| 106 | - 16 SerDes lanes at up to 10.3125 GHz |
| 107 | - Ethernet interfaces |
| 108 | - Up to eight 10 Gbps Ethernet MACs |
| 109 | - Up to eight 1 / 2.5 Gbps Ethernet MACs |
| 110 | - High-speed peripheral interfaces |
| 111 | - Four PCIe 3.0 controllers, one supporting SR-IOV |
| 112 | - Additional peripheral interfaces |
| 113 | - Two serial ATA (SATA 3.0) controllers |
| 114 | - Two high-speed USB 3.0 controllers with integrated PHY |
| 115 | - Enhanced secure digital host controller (eSDXC/eMMC) |
| 116 | - Serial peripheral interface (SPI) controller |
| 117 | - Quad Serial Peripheral Interface (QSPI) Controller |
| 118 | - Four I2C controllers |
| 119 | - Two DUARTs |
| 120 | - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash |
| 121 | - Support for hardware virtualization and partitioning enforcement |
| 122 | - QorIQ platform's trust architecture 3.0 |
| 123 | - Service processor (SP) provides pre-boot initialization and secure-boot |
| 124 | capabilities |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 125 | |
| 126 | LS1012A |
| 127 | -------- |
| 128 | The LS1012A features an advanced 64-bit ARM v8 Cortex- |
| 129 | A53 processor, with 32 KB of parity protected L1-I cache, |
| 130 | 32 KB of ECC protected L1-D cache, as well as 256 KB of |
| 131 | ECC protected L2 cache. |
| 132 | |
| 133 | The LS1012A SoC includes the following function and features: |
| 134 | - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: |
| 135 | - ARM v8 cryptography extensions |
| 136 | - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports |
| 137 | 16-/8-bit operation (no ECC support) |
| 138 | - ARM core-link CCI-400 cache coherent interconnect |
| 139 | - Packet Forwarding Engine (PFE) |
| 140 | - Cryptography acceleration (SEC) |
| 141 | - Ethernet interfaces supported by PFE: |
| 142 | - One Configurable x3 SerDes: |
| 143 | Two Serdes PLLs supported for usage by any SerDes data lane |
| 144 | Support for up to 6 GBaud operation |
| 145 | - High-speed peripheral interfaces: |
| 146 | - One PCI Express Gen2 controller, supporting x1 operation |
| 147 | - One serial ATA (SATA Gen 3.0) controller |
| 148 | - One USB 3.0/2.0 controller with integrated PHY |
| 149 | - One USB 2.0 controller with ULPI interface. . |
| 150 | - Additional peripheral interfaces: |
| 151 | - One quad serial peripheral interface (QuadSPI) controller |
| 152 | - One serial peripheral interface (SPI) controller |
| 153 | - Two enhanced secure digital host controllers |
| 154 | - Two I2C controllers |
| 155 | - One 16550 compliant DUART (two UART interfaces) |
| 156 | - Two general purpose IOs (GPIO) |
| 157 | - Two FlexTimers |
| 158 | - Five synchronous audio interfaces (SAI) |
| 159 | - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading |
| 160 | - Single-source clocking solution enabling generation of core, platform, |
| 161 | DDR, SerDes, and USB clocks from a single external crystal and internal |
| 162 | crystaloscillator |
| 163 | - Thermal monitor unit (TMU) with +/- 3C accuracy |
| 164 | - Two WatchDog timers |
| 165 | - ARM generic timer |
| 166 | - QorIQ platform's trust architecture 2.1 |
Mingkai Hu | cd54c0f | 2016-07-05 16:01:55 +0800 | [diff] [blame] | 167 | |
| 168 | LS1046A |
| 169 | -------- |
| 170 | The LS1046A integrated multicore processor combines four ARM Cortex-A72 |
| 171 | processor cores with datapath acceleration optimized for L2/3 packet |
| 172 | processing, single pass security offload and robust traffic management |
| 173 | and quality of service. |
| 174 | |
| 175 | The LS1046A SoC includes the following function and features: |
| 176 | - Four 64-bit ARM Cortex-A72 CPUs |
| 177 | - 2 MB unified L2 Cache |
| 178 | - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving |
| 179 | support |
| 180 | - Data Path Acceleration Architecture (DPAA) incorporating acceleration the |
| 181 | the following functions: |
| 182 | - Packet parsing, classification, and distribution (FMan) |
| 183 | - Queue management for scheduling, packet sequencing, and congestion |
| 184 | management (QMan) |
| 185 | - Hardware buffer management for buffer allocation and de-allocation (BMan) |
| 186 | - Cryptography acceleration (SEC) |
| 187 | - Two Configurable x4 SerDes |
| 188 | - Two PLLs per four-lane SerDes |
| 189 | - Support for 10G operation |
| 190 | - Ethernet interfaces by FMan |
| 191 | - Up to 2 x XFI supporting 10G interface (MAC 9, 10) |
| 192 | - Up to 1 x QSGMII (MAC 5, 6, 10, 1) |
| 193 | - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) |
| 194 | - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) |
| 195 | - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) |
| 196 | - High-speed peripheral interfaces |
| 197 | - Three PCIe 3.0 controllers, one supporting x4 operation |
| 198 | - One serial ATA (SATA 3.0) controllers |
| 199 | - Additional peripheral interfaces |
| 200 | - Three high-speed USB 3.0 controllers with integrated PHY |
| 201 | - Enhanced secure digital host controller (eSDXC/eMMC) |
| 202 | - Quad Serial Peripheral Interface (QSPI) Controller |
| 203 | - Serial peripheral interface (SPI) controller |
| 204 | - Four I2C controllers |
| 205 | - Two DUARTs |
| 206 | - Integrated flash controller (IFC) supporting NAND and NOR flash |
| 207 | - QorIQ platform's trust architecture 2.1 |
Priyanka Jain | 4a6f173 | 2016-11-17 12:29:55 +0530 | [diff] [blame] | 208 | |
| 209 | LS2088A |
| 210 | -------- |
| 211 | The LS2088A integrated multicore processor combines eight ARM Cortex-A72 |
| 212 | processor cores with high-performance data path acceleration logic and network |
| 213 | and peripheral bus interfaces required for networking, telecom/datacom, |
| 214 | wireless infrastructure, and mil/aerospace applications. |
| 215 | |
| 216 | The LS2088A SoC includes the following function and features: |
| 217 | |
| 218 | - Eight 64-bit ARM Cortex-A72 CPUs |
| 219 | - 1 MB platform cache with ECC |
| 220 | - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support |
| 221 | - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by |
| 222 | the AIOP |
| 223 | - Data path acceleration architecture (DPAA2) incorporating acceleration for |
| 224 | the following functions: |
| 225 | - Packet parsing, classification, and distribution (WRIOP) |
| 226 | - Queue and Hardware buffer management for scheduling, packet sequencing, and |
| 227 | congestion management, buffer allocation and de-allocation (QBMan) |
| 228 | - Cryptography acceleration (SEC) at up to 10 Gbps |
| 229 | - RegEx pattern matching acceleration (PME) at up to 10 Gbps |
| 230 | - Decompression/compression acceleration (DCE) at up to 20 Gbps |
| 231 | - Accelerated I/O processing (AIOP) at up to 20 Gbps |
| 232 | - QDMA engine |
| 233 | - 16 SerDes lanes at up to 10.3125 GHz |
| 234 | - Ethernet interfaces |
| 235 | - Up to eight 10 Gbps Ethernet MACs |
| 236 | - Up to eight 1 / 2.5 Gbps Ethernet MACs |
| 237 | - High-speed peripheral interfaces |
| 238 | - Four PCIe 3.0 controllers, one supporting SR-IOV |
| 239 | - Additional peripheral interfaces |
| 240 | - Two serial ATA (SATA 3.0) controllers |
| 241 | - Two high-speed USB 3.0 controllers with integrated PHY |
| 242 | - Enhanced secure digital host controller (eSDXC/eMMC) |
| 243 | - Serial peripheral interface (SPI) controller |
| 244 | - Quad Serial Peripheral Interface (QSPI) Controller |
| 245 | - Four I2C controllers |
| 246 | - Two DUARTs |
| 247 | - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash |
| 248 | - Support for hardware virtualization and partitioning enforcement |
| 249 | - QorIQ platform's trust architecture 3.0 |
| 250 | - Service processor (SP) provides pre-boot initialization and secure-boot |
| 251 | capabilities |
| 252 | |
| 253 | LS2088A SoC has 3 more similar SoC personalities |
| 254 | 1)LS2048A, few difference w.r.t. LS2088A: |
| 255 | a) Four 64-bit ARM v8 Cortex-A72 CPUs |
| 256 | |
| 257 | 2)LS2084A, few difference w.r.t. LS2088A: |
| 258 | a) No AIOP |
| 259 | b) No 32-bit DDR3 SDRAM memory |
| 260 | c) 5 * 1/10G + 5 *1G WRIOP |
| 261 | d) No L2 switch |
| 262 | |
| 263 | 3)LS2044A, few difference w.r.t. LS2084A: |
| 264 | a) Four 64-bit ARM v8 Cortex-A72 CPUs |
Priyanka Jain | 2b36178 | 2017-04-27 15:08:06 +0530 | [diff] [blame] | 265 | |
| 266 | LS2081A |
| 267 | -------- |
| 268 | LS2081A is 40-pin derivative of LS2084A. |
| 269 | So feature-wise it is same as LS2084A. |
| 270 | Refer to LS2084A(LS2088A) section above for details. |
| 271 | |
| 272 | It has one more similar SoC personality |
| 273 | 1)LS2041A, few difference w.r.t. LS2081A: |
| 274 | a) Four 64-bit ARM v8 Cortex-A72 CPUs |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame^] | 275 | |
| 276 | LX2160A |
| 277 | -------- |
| 278 | The QorIQ LX2160A processor is built in the 16FFC process on |
| 279 | the Layerscape architecture combining sixteen ARM A72 processor |
| 280 | cores with advanced, high-performance datapath acceleration and |
| 281 | network, peripheral interfaces required for networking, wireless |
| 282 | infrastructure, storage, and general-purpose embedded applications. |
| 283 | |
| 284 | LX2160A is compliant with the Layerscape Chassis Generation 3.2. |
| 285 | |
| 286 | The LX2160A SoC includes the following function and features: |
| 287 | Sixteen 32-bit / 64-bit ARM v8 A72 CPUs |
| 288 | Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) |
| 289 | Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. |
| 290 | Data path acceleration architecture (DPAA2) |
| 291 | 24 Serdes lanes at up to 25 GHz |
| 292 | Ethernet interfaces |
| 293 | Single WRIOP tile supporting 130Gbps using 18 MACs |
| 294 | Support for 10G-SXGMII (aka USXGMII). |
| 295 | Support for SGMII (and 1000Base-KX) |
| 296 | Support for XFI (and 10GBase-KR) |
| 297 | Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). |
| 298 | Support for XLAUI (and 40GBase-KR4) for 40G. |
| 299 | Support for two RGMII parallel interfaces. |
| 300 | Energy efficient Ethernet support (802.3az) |
| 301 | IEEE 1588 support. |
| 302 | High-speed peripheral interfaces |
| 303 | Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, |
| 304 | Four PCIe Gen 4.0 4-lane controllers. |
| 305 | Four serial ATA (SATA 3.0) controllers. |
| 306 | Two USB 3.0 controllers with integrated PHY |
| 307 | Two Enhanced secure digital host controllers |
| 308 | Two Controller Area Network (CAN) modules |
| 309 | Flexible Serial peripheral interface (FlexSPI) controller. |
| 310 | Three Serial peripheral interface (SPI) controllers. |
| 311 | Eight I2C Controllers. |
| 312 | Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. |
| 313 | General Purpose IO (GPIO) |
| 314 | Support for hardware virtualization and partitioning (ARM MMU-500) |
| 315 | Support for GIC (ARM GIC-500) |
| 316 | QorIQ platform Trust Architecture 3.0 |
| 317 | One Secure WatchDog timer and one Non-Secure Watchdog timer. |
| 318 | ARM Generic Timer |
| 319 | Two Flextimers |
| 320 | Debug supporting run control, data acquisition, high-speed trace, |
| 321 | performance/event monitoring |
| 322 | Thermal Monitor Unit (TMU) with +/- 2C accuracy |
| 323 | Support for Voltage ID (VID) for yield improvement |
| 324 | |
| 325 | LX2160A SoC has 2 more similar SoC personalities |
| 326 | 1)LX2120A, few difference w.r.t. LX2160A: |
| 327 | a) Twelve 64-bit ARM v8 Cortex-A72 CPUs |
| 328 | |
| 329 | 2)LX2080A, few difference w.r.t. LX2160A: |
| 330 | a) Eight 64-bit ARM v8 Cortex-A72 CPUs |