Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License version 2 as published |
| 6 | * by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Gabor Juhos | 439c50c | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 10 | #include <netdev.h> |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 11 | |
Gabor Juhos | 652ccee | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 12 | #include <asm/addrspace.h> |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 13 | #include <asm/io.h> |
| 14 | #include <asm/malta.h> |
Gabor Juhos | 652ccee | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 15 | #include <pci_gt64120.h> |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 16 | |
Gabor Juhos | 02c754a | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 17 | phys_size_t initdram(int board_type) |
| 18 | { |
| 19 | return CONFIG_SYS_MEM_SIZE; |
| 20 | } |
| 21 | |
| 22 | int checkboard(void) |
| 23 | { |
| 24 | puts("Board: MIPS Malta CoreLV (Qemu)\n"); |
| 25 | return 0; |
| 26 | } |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 27 | |
Gabor Juhos | 439c50c | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 28 | int board_eth_init(bd_t *bis) |
| 29 | { |
| 30 | return pci_eth_init(bis); |
| 31 | } |
| 32 | |
Gabor Juhos | aed4fa4 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 33 | void _machine_restart(void) |
| 34 | { |
| 35 | void __iomem *reset_base; |
| 36 | |
| 37 | reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); |
| 38 | __raw_writel(GORESET, reset_base); |
| 39 | } |
Gabor Juhos | 652ccee | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 40 | |
| 41 | void pci_init_board(void) |
| 42 | { |
| 43 | set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); |
| 44 | |
| 45 | gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), |
| 46 | 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, |
| 47 | 0x10000000, 0x10000000, 128 * 1024 * 1024, |
| 48 | 0x00000000, 0x00000000, 0x20000); |
| 49 | } |