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wdenk7d1eb822004-09-29 11:02:56 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 * Keith Outwater, keith_outwater@mvis.com.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk7d1eb822004-09-29 11:02:56 +00007 */
8
9/*
10 * Virtex2 FPGA configuration support for the QUANTUM computer
11 */
12int fpga_boot(unsigned char *fpgadata, int size);
13
14#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
15#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
16#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */