| Bhupesh Sharma | 2f579cd | 2024-09-10 11:11:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2023, Linaro Limited |
| 4 | */ |
| 5 | |
| 6 | #ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ |
| 7 | #define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ |
| 8 | |
| 9 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28 |
| 10 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c |
| 11 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 |
| 12 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 |
| 13 | #define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c |
| 14 | #define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 |
| 15 | |
| 16 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 |
| 17 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 |
| 18 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24 |
| 19 | #define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28 |
| 20 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54 |
| 21 | #define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58 |
| 22 | #define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4 |
| 23 | #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 |
| 24 | #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc |
| 25 | #define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0 |
| 26 | #define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4 |
| 27 | #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 |
| 28 | #define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0x1ac |
| 29 | #define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc |
| 30 | #define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0 |
| 31 | #define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4 |
| 32 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 |
| 33 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c |
| 34 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2 0x210 |
| 35 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 |
| 36 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4 0x218 |
| 37 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220 |
| 38 | #define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238 |
| 39 | #define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244 |
| 40 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c |
| 41 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260 |
| 42 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 |
| 43 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 |
| 44 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B0 0x274 |
| 45 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B1 0x278 |
| 46 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B2 0x27c |
| 47 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 |
| 48 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284 |
| 49 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c |
| 50 | #define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8 |
| 51 | |
| 52 | #endif |