| Mayuresh Chitale | f440c06 | 2024-08-23 09:41:25 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2024 Ventana Micro Systems Ltd. |
| 4 | * |
| 5 | * Ported from linux insn-def.h. |
| 6 | */ |
| 7 | |
| 8 | #ifndef _ASM_RISCV_BARRIER_H |
| 9 | #define _ASM_RISCV_BARRIER_H |
| 10 | |
| 11 | #define INSN_I_SIMM12_SHIFT 20 |
| 12 | #define INSN_I_RS1_SHIFT 15 |
| 13 | #define INSN_I_FUNC3_SHIFT 12 |
| 14 | #define INSN_I_RD_SHIFT 7 |
| 15 | #define INSN_I_OPCODE_SHIFT 0 |
| 16 | |
| 17 | #define RV_OPCODE(v) __ASM_STR(v) |
| 18 | #define RV_FUNC3(v) __ASM_STR(v) |
| 19 | #define RV_FUNC7(v) __ASM_STR(v) |
| 20 | #define RV_SIMM12(v) __ASM_STR(v) |
| 21 | #define RV_RD(v) __ASM_STR(v) |
| 22 | #define RV_RS1(v) __ASM_STR(v) |
| 23 | #define RV_RS2(v) __ASM_STR(v) |
| 24 | #define __RV_REG(v) __ASM_STR(x ## v) |
| 25 | #define RV___RD(v) __RV_REG(v) |
| 26 | #define RV___RS1(v) __RV_REG(v) |
| 27 | #define RV___RS2(v) __RV_REG(v) |
| 28 | |
| 29 | #define RV_OPCODE_MISC_MEM RV_OPCODE(15) |
| 30 | #define RV_OPCODE_SYSTEM RV_OPCODE(115) |
| 31 | |
| 32 | #define __INSN_I(opcode, func3, rd, rs1, simm12) \ |
| 33 | ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" |
| 34 | |
| 35 | #define INSN_I(opcode, func3, rd, rs1, simm12) \ |
| 36 | __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \ |
| 37 | RV_##rs1, RV_##simm12) |
| 38 | |
| 39 | #endif /* _ASM_RISCV_BARRIER_H */ |