| Simon Glass | 3ed3a4d | 2024-10-23 15:20:10 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-2-Clause-Patent */ |
| 2 | /** |
| 3 | * |
| 4 | * Copyright (c) 2019, ARM Limited. All rights reserved. |
| 5 | * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin@gmail.com> |
| 6 | * Copyright (c) 2016, Linaro Limited. All rights reserved. |
| 7 | * |
| 8 | **/ |
| 9 | |
| 10 | #ifndef __BCM2836_H__ |
| 11 | #define __BCM2836_H__ |
| 12 | |
| 13 | /* |
| 14 | * Both "core" and SoC perpherals (1M each). |
| 15 | */ |
| 16 | #define BCM2836_SOC_REGISTERS 0xfe000000 |
| 17 | #define BCM2836_SOC_REGISTER_LENGTH 0x02000000 |
| 18 | |
| 19 | /* |
| 20 | * Offset between the CPU's view and the VC's view of system memory. |
| 21 | */ |
| 22 | #define BCM2836_DMA_DEVICE_OFFSET 0xc0000000 |
| 23 | |
| 24 | /* watchdog constants */ |
| 25 | #define BCM2836_WDOG_OFFSET 0x00100000 |
| 26 | #define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET) |
| 27 | #define BCM2836_WDOG_PASSWORD 0x5a000000 |
| 28 | #define BCM2836_WDOG_RSTC_OFFSET 0x0000001c |
| 29 | #define BCM2836_WDOG_WDOG_OFFSET 0x00000024 |
| 30 | #define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030 |
| 31 | #define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020 |
| 32 | |
| 33 | /* clock manager constants */ |
| 34 | #define BCM2836_CM_OFFSET 0x00101000 |
| 35 | #define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET) |
| 36 | #define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000 |
| 37 | #define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004 |
| 38 | #define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008 |
| 39 | #define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c |
| 40 | #define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010 |
| 41 | #define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014 |
| 42 | #define BCM2836_CM_H264_CLOCK_CONTROL 0x0028 |
| 43 | #define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c |
| 44 | #define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0 |
| 45 | #define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4 |
| 46 | #define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0 |
| 47 | #define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4 |
| 48 | #define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8 |
| 49 | #define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac |
| 50 | #define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0 |
| 51 | #define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4 |
| 52 | #define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0 |
| 53 | #define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4 |
| 54 | |
| 55 | /* mailbox interface constants */ |
| 56 | #define BCM2836_MBOX_OFFSET 0x0000b880 |
| 57 | #define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET) |
| 58 | #define BCM2836_MBOX_LENGTH 0x00000024 |
| 59 | #define BCM2836_MBOX_READ_OFFSET 0x00000000 |
| 60 | #define BCM2836_MBOX_STATUS_OFFSET 0x00000018 |
| 61 | #define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c |
| 62 | #define BCM2836_MBOX_WRITE_OFFSET 0x00000020 |
| 63 | |
| 64 | #define BCM2836_MBOX_STATUS_FULL 0x1f |
| 65 | #define BCM2836_MBOX_STATUS_EMPTY 0x1e |
| 66 | |
| 67 | #define BCM2836_MBOX_NUM_CHANNELS 16 |
| 68 | |
| 69 | /* interrupt controller constants */ |
| 70 | #define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040 |
| 71 | #define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060 |
| 72 | |
| 73 | /* usb constants */ |
| 74 | #define BCM2836_USB_OFFSET 0x00980000 |
| 75 | #define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET) |
| 76 | #define BCM2836_USB_LENGTH 0x00010000 |
| 77 | |
| 78 | /* serial based protocol constants */ |
| 79 | #define BCM2836_PL011_UART_OFFSET 0x00201000 |
| 80 | #define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET) |
| 81 | #define BCM2836_PL011_UART_LENGTH 0x00001000 |
| 82 | |
| 83 | #define BCM2836_MINI_UART_OFFSET 0x00215000 |
| 84 | #define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET) |
| 85 | #define BCM2836_MINI_UART_LENGTH 0x00000070 |
| 86 | |
| 87 | #define BCM2836_I2C0_OFFSET 0x00205000 |
| 88 | #define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET) |
| 89 | #define BCM2836_I2C0_LENGTH 0x00000020 |
| 90 | |
| 91 | #define BCM2836_I2C1_OFFSET 0x00804000 |
| 92 | #define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET) |
| 93 | #define BCM2836_I2C1_LENGTH 0x00000020 |
| 94 | |
| 95 | #define BCM2836_I2C2_OFFSET 0x00805000 |
| 96 | #define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET) |
| 97 | #define BCM2836_I2C2_LENGTH 0x00000020 |
| 98 | |
| 99 | #define BCM2836_SPI0_OFFSET 0x00204000 |
| 100 | #define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET) |
| 101 | #define BCM2836_SPI0_LENGTH 0x00000020 |
| 102 | |
| 103 | #define BCM2836_SPI1_OFFSET 0x00215080 |
| 104 | #define BCM2836_SPI1_LENGTH 0x00000040 |
| 105 | #define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET) |
| 106 | |
| 107 | #define BCM2836_SPI2_OFFSET 0x002150C0 |
| 108 | #define BCM2836_SPI2_LENGTH 0x00000040 |
| 109 | #define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET) |
| 110 | |
| 111 | #define BCM2836_SYSTEM_TIMER_OFFSET 0x00003000 |
| 112 | #define BCM2836_SYSTEM_TIMER_LENGTH 0x00000020 |
| 113 | #define BCM2836_SYSTEM_TIMER_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SYSTEM_TIMER_OFFSET) |
| 114 | |
| 115 | /* dma constants */ |
| 116 | #define BCM2836_DMA0_OFFSET 0x00007000 |
| 117 | #define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET) |
| 118 | |
| 119 | #define BCM2836_DMA15_OFFSET 0x00E05000 |
| 120 | #define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET) |
| 121 | |
| 122 | #define BCM2836_DMA_CTRL_OFFSET 0x00007FE0 |
| 123 | #define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET) |
| 124 | |
| 125 | #define BCM2836_DMA_CHANNEL_LENGTH 0x00000100 |
| 126 | |
| 127 | #endif /*__BCM2836_H__ */ |