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Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09001/*
Masahiro Yamada94d79e92015-05-29 17:30:05 +09002 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/* U-boot - Common settings for UniPhier Family */
8
9#ifndef __CONFIG_UNIPHIER_COMMON_H__
10#define __CONFIG_UNIPHIER_COMMON_H__
11
Masahiro Yamada1e72b1c2014-12-06 00:03:22 +090012#if defined(CONFIG_MACH_PH1_PRO4)
13#define CONFIG_DDR_NUM_CH0 2
14#define CONFIG_DDR_NUM_CH1 2
15
16/* Physical start address of SDRAM */
17#define CONFIG_SDRAM0_BASE 0x80000000
18#define CONFIG_SDRAM0_SIZE 0x20000000
19#define CONFIG_SDRAM1_BASE 0xa0000000
20#define CONFIG_SDRAM1_SIZE 0x20000000
21#endif
22
23#if defined(CONFIG_MACH_PH1_LD4)
24#define CONFIG_DDR_NUM_CH0 1
25#define CONFIG_DDR_NUM_CH1 1
26
27/* Physical start address of SDRAM */
28#define CONFIG_SDRAM0_BASE 0x80000000
29#define CONFIG_SDRAM0_SIZE 0x10000000
30#define CONFIG_SDRAM1_BASE 0x90000000
31#define CONFIG_SDRAM1_SIZE 0x10000000
32#endif
33
34#if defined(CONFIG_MACH_PH1_SLD8)
35#define CONFIG_DDR_NUM_CH0 1
36#define CONFIG_DDR_NUM_CH1 1
37
38/* Physical start address of SDRAM */
39#define CONFIG_SDRAM0_BASE 0x80000000
40#define CONFIG_SDRAM0_SIZE 0x10000000
41#define CONFIG_SDRAM1_BASE 0x90000000
42#define CONFIG_SDRAM1_SIZE 0x10000000
43#endif
44
Masahiro Yamadaa8dd2012015-01-13 12:44:39 +090045#define CONFIG_I2C_EEPROM
46#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
47
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090048/*
49 * Support card address map
50 */
51#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
52# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
53# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
54# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
55# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
56#endif
57
58#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
59# define CONFIG_SUPPORT_CARD_BASE 0x08000000
60# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
61# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
62# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
63#endif
64
Masahiro Yamada50c12542014-10-23 22:26:10 +090065#ifdef CONFIG_SYS_NS16550_SERIAL
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090066#define CONFIG_SYS_NS16550
67#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
68#define CONFIG_SYS_NS16550_CLK 12288000
69#define CONFIG_SYS_NS16550_REG_SIZE -2
Masahiro Yamada50c12542014-10-23 22:26:10 +090070#endif
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090071
Masahiro Yamada1e72b1c2014-12-06 00:03:22 +090072/* TODO: move to Kconfig and device tree */
73#if 0
74#define CONFIG_SYS_NS16550_SERIAL
75#endif
76
77#define CONFIG_SMC911X
78
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090079#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
80#define CONFIG_SMC911X_32_BIT
81
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090082/*-----------------------------------------------------------------------
83 * MMU and Cache Setting
84 *----------------------------------------------------------------------*/
85
86/* Comment out the following to enable L1 cache */
87/* #define CONFIG_SYS_ICACHE_OFF */
88/* #define CONFIG_SYS_DCACHE_OFF */
89
Masahiro Yamadad50f3362015-02-27 02:27:01 +090090#define CONFIG_SYS_CACHELINE_SIZE 32
91
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090092/* Comment out the following to enable L2 cache */
93#define CONFIG_UNIPHIER_L2CACHE_ON
94
95#define CONFIG_DISPLAY_CPUINFO
96#define CONFIG_DISPLAY_BOARDINFO
Masahiro Yamada4cd15c62015-02-05 14:42:56 +090097#define CONFIG_MISC_INIT_F
Masahiro Yamada1f3d9c72015-02-05 14:42:54 +090098#define CONFIG_BOARD_EARLY_INIT_F
Masahiro Yamada88216812014-12-06 00:03:26 +090099#define CONFIG_BOARD_EARLY_INIT_R
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900100#define CONFIG_BOARD_LATE_INIT
101
102#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
103
104#define CONFIG_TIMESTAMP
105
106/* FLASH related */
107#define CONFIG_MTD_DEVICE
108
109/*
110 * uncomment the following to disable FLASH related code.
111 */
112/* #define CONFIG_SYS_NO_FLASH */
113
114#define CONFIG_FLASH_CFI_DRIVER
115#define CONFIG_SYS_FLASH_CFI
116
117#define CONFIG_SYS_MAX_FLASH_SECT 256
118#define CONFIG_SYS_MONITOR_BASE 0
119#define CONFIG_SYS_FLASH_BASE 0
120
121/*
122 * flash_toggle does not work for out supoort card.
123 * We need to use flash_status_poll.
124 */
125#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
126
127#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
128
Masahiro Yamada88216812014-12-06 00:03:26 +0900129#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900130
131/* serial console configuration */
132#define CONFIG_BAUDRATE 115200
133
134#define CONFIG_SYS_GENERIC_BOARD
135
136#if !defined(CONFIG_SPL_BUILD)
137#define CONFIG_USE_ARCH_MEMSET
138#define CONFIG_USE_ARCH_MEMCPY
139#endif
140
141#define CONFIG_SYS_LONGHELP /* undef to save memory */
142
143#define CONFIG_CMDLINE_EDITING /* add command line history */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
145/* Print Buffer Size */
146#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
147#define CONFIG_SYS_MAXARGS 16 /* max number of command */
148/* Boot Argument Buffer Size */
149#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
150
151#define CONFIG_CONS_INDEX 1
152
153/*
154 * For NAND booting the environment is embedded in the U-Boot image. Please take
155 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
156 */
157/* #define CONFIG_ENV_IS_IN_NAND */
158#define CONFIG_ENV_IS_NOWHERE
159#define CONFIG_ENV_SIZE 0x2000
160#define CONFIG_ENV_OFFSET 0x0
161/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
162
163/* Time clock 1MHz */
164#define CONFIG_SYS_TIMER_RATE 1000000
165
166/*
167 * By default, ARP timeout is 5 sec.
168 * The first ARP request does not seem to work.
169 * So we need to retry ARP request anyway.
170 * We want to shrink the interval until the second ARP request.
171 */
172#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
173
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900174#define CONFIG_SYS_MAX_NAND_DEVICE 1
175#define CONFIG_SYS_NAND_MAX_CHIPS 2
176#define CONFIG_SYS_NAND_ONFI_DETECTION
177
178#define CONFIG_NAND_DENALI_ECC_SIZE 1024
179
180#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
181#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
182
183#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
184
185#define CONFIG_SYS_NAND_USE_FLASH_BBT
186#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
187
Masahiro Yamada0b7e1df2014-11-07 18:48:34 +0900188/* USB */
Masahiro Yamada0b7e1df2014-11-07 18:48:34 +0900189#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Masahiro Yamadad50f3362015-02-27 02:27:01 +0900190#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
Masahiro Yamada0b7e1df2014-11-07 18:48:34 +0900191#define CONFIG_CMD_FAT
192#define CONFIG_FAT_WRITE
193#define CONFIG_DOS_PARTITION
194
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900195/* memtest works on */
196#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
197#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
198
199#define CONFIG_BOOTDELAY 3
200#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900201
202/*
203 * Network Configuration
204 */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900205#define CONFIG_SERVERIP 192.168.11.1
206#define CONFIG_IPADDR 192.168.11.10
207#define CONFIG_GATEWAYIP 192.168.11.1
208#define CONFIG_NETMASK 255.255.255.0
209
210#define CONFIG_LOADADDR 0x84000000
211#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900212
213#define CONFIG_CMDLINE_EDITING /* add command line history */
214
215#define CONFIG_BOOTCOMMAND "run $bootmode"
216
217#define CONFIG_ROOTPATH "/nfs/root/path"
218#define CONFIG_NFSBOOTCOMMAND \
219 "setenv bootargs $bootargs root=/dev/nfs rw " \
220 "nfsroot=$serverip:$rootpath " \
221 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
222 "tftpboot; bootm;"
223
224#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
225
Masahiro Yamadaec81fb52015-07-21 14:04:18 +0900226#ifdef CONFIG_FIT
227#define CONFIG_BOOTFILE "fitImage"
228#define LINUXBOOT_ENV_SETTINGS \
229 "fit_addr=0x00100000\0" \
230 "fit_addr_r=0x84100000\0" \
231 "fit_size=0x00f00000\0" \
232 "norboot=run add_default_bootargs &&" \
233 "bootm $fit_addr\0" \
234 "nandboot=run add_default_bootargs &&" \
235 "nand read $fit_addr_r $fit_addr $fit_size &&" \
Masahiro Yamadaeebc1292015-07-21 14:04:19 +0900236 "bootm $fit_addr_r\0" \
237 "tftpboot=run add_default_bootargs &&" \
238 "tftpboot $fit_addr_r $bootfile &&" \
Masahiro Yamadaec81fb52015-07-21 14:04:18 +0900239 "bootm $fit_addr_r\0"
240#else
241#define CONFIG_BOOTFILE "uImage"
242#define LINUXBOOT_ENV_SETTINGS \
243 "fdt_addr=0x00100000\0" \
244 "fdt_addr_r=0x84100000\0" \
245 "fdt_size=0x00008000\0" \
Masahiro Yamadaeebc1292015-07-21 14:04:19 +0900246 "fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
Masahiro Yamadaec81fb52015-07-21 14:04:18 +0900247 "kernel_addr=0x00200000\0" \
248 "kernel_addr_r=0x84200000\0" \
249 "kernel_size=0x00800000\0" \
250 "ramdisk_addr=0x00a00000\0" \
251 "ramdisk_addr_r=0x84a00000\0" \
252 "ramdisk_size=0x00600000\0" \
Masahiro Yamadaeebc1292015-07-21 14:04:19 +0900253 "ramdisk_file=rootfs.cpio.uboot\0" \
Masahiro Yamadaec81fb52015-07-21 14:04:18 +0900254 "norboot=run add_default_bootargs &&" \
255 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
256 "nandboot=run add_default_bootargs &&" \
257 "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
258 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
259 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
Masahiro Yamadaeebc1292015-07-21 14:04:19 +0900260 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
261 "tftpboot=run add_default_bootargs &&" \
262 "tftpboot $kernel_addr_r $bootfile &&" \
263 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
264 "tftpboot $fdt_addr_r $fdt_file &&" \
Masahiro Yamadaec81fb52015-07-21 14:04:18 +0900265 "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
266#endif
267
268#define CONFIG_EXTRA_ENV_SETTINGS \
269 "netdev=eth0\0" \
270 "verify=n\0" \
271 "nandupdate=nand erase 0 0x00100000 &&" \
272 "tftpboot u-boot-spl.bin &&" \
273 "nand write $loadaddr 0 0x00010000 &&" \
274 "tftpboot u-boot-dtb.img &&" \
275 "nand write $loadaddr 0x00010000 0x000f0000\0" \
276 "add_default_bootargs=setenv bootargs $bootargs" \
277 " console=ttyS0,$baudrate\0" \
278 LINUXBOOT_ENV_SETTINGS
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900279
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900280/* Open Firmware flat tree */
281#define CONFIG_OF_LIBFDT
282
283#define CONFIG_HAVE_ARM_SECURE
284
285/* Memory Size & Mapping */
286#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
287
288#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
289/* Thre is no memory hole */
290#define CONFIG_NR_DRAM_BANKS 1
291#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
292#else
293#define CONFIG_NR_DRAM_BANKS 2
294#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
295#endif
296
Masahiro Yamada1e72b1c2014-12-06 00:03:22 +0900297#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
298#define CONFIG_SPL_TEXT_BASE 0x00040000
299#endif
300#if defined(CONFIG_MACH_PH1_PRO4)
301#define CONFIG_SPL_TEXT_BASE 0x00100000
302#endif
303
Masahiro Yamada5b01ec42015-03-23 00:07:26 +0900304#define CONFIG_SPL_STACK (0x0ff08000)
Masahiro Yamada424e7822015-03-23 00:07:28 +0900305#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900306
Masahiro Yamada37797532015-03-23 00:07:24 +0900307#define CONFIG_PANIC_HANG
308
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900309#define CONFIG_SPL_FRAMEWORK
Masahiro Yamada6b23db82015-03-23 00:07:25 +0900310#define CONFIG_SPL_SERIAL_SUPPORT
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900311#define CONFIG_SPL_NAND_SUPPORT
312
313#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
314#define CONFIG_SPL_LIBGENERIC_SUPPORT
315
316#define CONFIG_SPL_BOARD_INIT
317
318#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
319
Masahiro Yamadab4f865d2015-03-23 00:07:27 +0900320#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
321
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900322#endif /* __CONFIG_UNIPHIER_COMMON_H__ */