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git01.mediatek.com / filogic / uboot / eeb012275b01b5db43007ab82f0a797c22bbfa80 / . / drivers / pinctrl / mediatek / pinctrl-mt7622.c
blob: b413a4c7e48b2e82bb167f5f5cb69062f0e70ee2 [file] [log] [blame]
developer2a2b17f2020-01-10 16:30:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <dm.h>
8
9#include "pinctrl-mtk-common.h"
10
11#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
12
13#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
14 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
15 _x_bits, 32, 0)
16
17#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
18 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
19 _x_bits, 32, 1)
20
21static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
22 PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
23 PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
24 PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
25 PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
26 PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
27 PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
28 PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
29 PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
30 PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
31 PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
32 PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
33 PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
34 PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
35 PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
36 PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
37 PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
38 PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
39 PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
40 PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
41 PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
42 PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
43 PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
44 PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
45 PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
46 PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
47 PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
48};
49
50static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
51 PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
52};
53
54static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
55 PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
56};
57
58static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
59 PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
60};
61
62static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
63 PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
64 PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
65 PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
66 PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
67 PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
68 PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
69 PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
70};
71
72static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
73 PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
74 PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
75 PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
76 PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
77 PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
78 PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
79 PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
80};
81
82static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
83 PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
84 PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
85 PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
86 PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
87 PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
88 PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
89 PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
90};
91
92static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
93 PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
94 PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
95 PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
96 PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
97 PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
98 PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
99 PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
100};
101
102static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
103 PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
104 PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
105 PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
106 PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
107 PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
108 PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
109 PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
110};
111
112static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
113 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
114 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
115 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
116 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
117 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
118 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
119 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
120 [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
121 [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
122};
123
124static const struct mtk_pin_desc mt7622_pins[] = {
125 MT7622_PIN(0, "GPIO_A"),
126 MT7622_PIN(1, "I2S1_IN"),
127 MT7622_PIN(2, "I2S1_OUT"),
128 MT7622_PIN(3, "I2S_BCLK"),
129 MT7622_PIN(4, "I2S_WS"),
130 MT7622_PIN(5, "I2S_MCLK"),
131 MT7622_PIN(6, "TXD0"),
132 MT7622_PIN(7, "RXD0"),
133 MT7622_PIN(8, "SPI_WP"),
134 MT7622_PIN(9, "SPI_HOLD"),
135 MT7622_PIN(10, "SPI_CLK"),
136 MT7622_PIN(11, "SPI_MOSI"),
137 MT7622_PIN(12, "SPI_MISO"),
138 MT7622_PIN(13, "SPI_CS"),
139 MT7622_PIN(14, "I2C_SDA"),
140 MT7622_PIN(15, "I2C_SCL"),
141 MT7622_PIN(16, "I2S2_IN"),
142 MT7622_PIN(17, "I2S3_IN"),
143 MT7622_PIN(18, "I2S4_IN"),
144 MT7622_PIN(19, "I2S2_OUT"),
145 MT7622_PIN(20, "I2S3_OUT"),
146 MT7622_PIN(21, "I2S4_OUT"),
147 MT7622_PIN(22, "GPIO_B"),
148 MT7622_PIN(23, "MDC"),
149 MT7622_PIN(24, "MDIO"),
150 MT7622_PIN(25, "G2_TXD0"),
151 MT7622_PIN(26, "G2_TXD1"),
152 MT7622_PIN(27, "G2_TXD2"),
153 MT7622_PIN(28, "G2_TXD3"),
154 MT7622_PIN(29, "G2_TXEN"),
155 MT7622_PIN(30, "G2_TXC"),
156 MT7622_PIN(31, "G2_RXD0"),
157 MT7622_PIN(32, "G2_RXD1"),
158 MT7622_PIN(33, "G2_RXD2"),
159 MT7622_PIN(34, "G2_RXD3"),
160 MT7622_PIN(35, "G2_RXDV"),
161 MT7622_PIN(36, "G2_RXC"),
162 MT7622_PIN(37, "NCEB"),
163 MT7622_PIN(38, "NWEB"),
164 MT7622_PIN(39, "NREB"),
165 MT7622_PIN(40, "NDL4"),
166 MT7622_PIN(41, "NDL5"),
167 MT7622_PIN(42, "NDL6"),
168 MT7622_PIN(43, "NDL7"),
169 MT7622_PIN(44, "NRB"),
170 MT7622_PIN(45, "NCLE"),
171 MT7622_PIN(46, "NALE"),
172 MT7622_PIN(47, "NDL0"),
173 MT7622_PIN(48, "NDL1"),
174 MT7622_PIN(49, "NDL2"),
175 MT7622_PIN(50, "NDL3"),
176 MT7622_PIN(51, "MDI_TP_P0"),
177 MT7622_PIN(52, "MDI_TN_P0"),
178 MT7622_PIN(53, "MDI_RP_P0"),
179 MT7622_PIN(54, "MDI_RN_P0"),
180 MT7622_PIN(55, "MDI_TP_P1"),
181 MT7622_PIN(56, "MDI_TN_P1"),
182 MT7622_PIN(57, "MDI_RP_P1"),
183 MT7622_PIN(58, "MDI_RN_P1"),
184 MT7622_PIN(59, "MDI_RP_P2"),
185 MT7622_PIN(60, "MDI_RN_P2"),
186 MT7622_PIN(61, "MDI_TP_P2"),
187 MT7622_PIN(62, "MDI_TN_P2"),
188 MT7622_PIN(63, "MDI_TP_P3"),
189 MT7622_PIN(64, "MDI_TN_P3"),
190 MT7622_PIN(65, "MDI_RP_P3"),
191 MT7622_PIN(66, "MDI_RN_P3"),
192 MT7622_PIN(67, "MDI_RP_P4"),
193 MT7622_PIN(68, "MDI_RN_P4"),
194 MT7622_PIN(69, "MDI_TP_P4"),
195 MT7622_PIN(70, "MDI_TN_P4"),
196 MT7622_PIN(71, "PMIC_SCL"),
197 MT7622_PIN(72, "PMIC_SDA"),
198 MT7622_PIN(73, "SPIC1_CLK"),
199 MT7622_PIN(74, "SPIC1_MOSI"),
200 MT7622_PIN(75, "SPIC1_MISO"),
201 MT7622_PIN(76, "SPIC1_CS"),
202 MT7622_PIN(77, "GPIO_D"),
203 MT7622_PIN(78, "WATCHDOG"),
204 MT7622_PIN(79, "RTS3_N"),
205 MT7622_PIN(80, "CTS3_N"),
206 MT7622_PIN(81, "TXD3"),
207 MT7622_PIN(82, "RXD3"),
208 MT7622_PIN(83, "PERST0_N"),
209 MT7622_PIN(84, "PERST1_N"),
210 MT7622_PIN(85, "WLED_N"),
211 MT7622_PIN(86, "EPHY_LED0_N"),
212 MT7622_PIN(87, "AUXIN0"),
213 MT7622_PIN(88, "AUXIN1"),
214 MT7622_PIN(89, "AUXIN2"),
215 MT7622_PIN(90, "AUXIN3"),
216 MT7622_PIN(91, "TXD4"),
217 MT7622_PIN(92, "RXD4"),
218 MT7622_PIN(93, "RTS4_N"),
219 MT7622_PIN(94, "CTS4_N"),
220 MT7622_PIN(95, "PWM1"),
221 MT7622_PIN(96, "PWM2"),
222 MT7622_PIN(97, "PWM3"),
223 MT7622_PIN(98, "PWM4"),
224 MT7622_PIN(99, "PWM5"),
225 MT7622_PIN(100, "PWM6"),
226 MT7622_PIN(101, "PWM7"),
227 MT7622_PIN(102, "GPIO_E"),
228};
229
230/* List all groups consisting of these pins dedicated to the enablement of
231 * certain hardware block and the corresponding mode for all of the pins. The
232 * hardware probably has multiple combinations of these pinouts.
233 */
234
235/* EMMC */
236static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
237static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
238
239static int mt7622_emmc_rst_pins[] = { 37, };
240static int mt7622_emmc_rst_funcs[] = { 1, };
241
242/* LED for EPHY */
243static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
244static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
245static int mt7622_ephy0_led_pins[] = { 86, };
246static int mt7622_ephy0_led_funcs[] = { 0, };
247static int mt7622_ephy1_led_pins[] = { 91, };
248static int mt7622_ephy1_led_funcs[] = { 2, };
249static int mt7622_ephy2_led_pins[] = { 92, };
250static int mt7622_ephy2_led_funcs[] = { 2, };
251static int mt7622_ephy3_led_pins[] = { 93, };
252static int mt7622_ephy3_led_funcs[] = { 2, };
253static int mt7622_ephy4_led_pins[] = { 94, };
254static int mt7622_ephy4_led_funcs[] = { 2, };
255
256/* Embedded Switch */
257static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
258 62, 63, 64, 65, 66, 67, 68, 69, 70, };
259static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 0, 0, 0, 0, 0, 0, 0, 0, 0, };
261static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
262static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
263static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
264 68, 69, 70, };
265static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
266 0, 0, 0, };
267/* RGMII via ESW */
268static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
269 67, 68, 69, 70, };
270static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
271 0, };
272
273/* RGMII via GMAC1 */
274static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
275 67, 68, 69, 70, };
276static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
277 2, };
278
279/* RGMII via GMAC2 */
280static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
281 33, 34, 35, 36, };
282static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
283 0, };
284
285/* I2C */
286static int mt7622_i2c0_pins[] = { 14, 15, };
287static int mt7622_i2c0_funcs[] = { 0, 0, };
288static int mt7622_i2c1_0_pins[] = { 55, 56, };
289static int mt7622_i2c1_0_funcs[] = { 0, 0, };
290static int mt7622_i2c1_1_pins[] = { 73, 74, };
291static int mt7622_i2c1_1_funcs[] = { 3, 3, };
292static int mt7622_i2c1_2_pins[] = { 87, 88, };
293static int mt7622_i2c1_2_funcs[] = { 0, 0, };
294static int mt7622_i2c2_0_pins[] = { 57, 58, };
295static int mt7622_i2c2_0_funcs[] = { 0, 0, };
296static int mt7622_i2c2_1_pins[] = { 75, 76, };
297static int mt7622_i2c2_1_funcs[] = { 3, 3, };
298static int mt7622_i2c2_2_pins[] = { 89, 90, };
299static int mt7622_i2c2_2_funcs[] = { 0, 0, };
300
301/* I2S */
302static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
303static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
304static int mt7622_i2s1_in_data_pins[] = { 1, };
305static int mt7622_i2s1_in_data_funcs[] = { 0, };
306static int mt7622_i2s2_in_data_pins[] = { 16, };
307static int mt7622_i2s2_in_data_funcs[] = { 0, };
308static int mt7622_i2s3_in_data_pins[] = { 17, };
309static int mt7622_i2s3_in_data_funcs[] = { 0, };
310static int mt7622_i2s4_in_data_pins[] = { 18, };
311static int mt7622_i2s4_in_data_funcs[] = { 0, };
312static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
313static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
314static int mt7622_i2s1_out_data_pins[] = { 2, };
315static int mt7622_i2s1_out_data_funcs[] = { 0, };
316static int mt7622_i2s2_out_data_pins[] = { 19, };
317static int mt7622_i2s2_out_data_funcs[] = { 0, };
318static int mt7622_i2s3_out_data_pins[] = { 20, };
319static int mt7622_i2s3_out_data_funcs[] = { 0, };
320static int mt7622_i2s4_out_data_pins[] = { 21, };
321static int mt7622_i2s4_out_data_funcs[] = { 0, };
322
323/* IR */
324static int mt7622_ir_0_tx_pins[] = { 16, };
325static int mt7622_ir_0_tx_funcs[] = { 4, };
326static int mt7622_ir_1_tx_pins[] = { 59, };
327static int mt7622_ir_1_tx_funcs[] = { 5, };
328static int mt7622_ir_2_tx_pins[] = { 99, };
329static int mt7622_ir_2_tx_funcs[] = { 3, };
330static int mt7622_ir_0_rx_pins[] = { 17, };
331static int mt7622_ir_0_rx_funcs[] = { 4, };
332static int mt7622_ir_1_rx_pins[] = { 60, };
333static int mt7622_ir_1_rx_funcs[] = { 5, };
334static int mt7622_ir_2_rx_pins[] = { 100, };
335static int mt7622_ir_2_rx_funcs[] = { 3, };
336
337/* MDIO */
338static int mt7622_mdc_mdio_pins[] = { 23, 24, };
339static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
340
341/* PCIE */
342static int mt7622_pcie0_0_waken_pins[] = { 14, };
343static int mt7622_pcie0_0_waken_funcs[] = { 2, };
344static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
345static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
346static int mt7622_pcie0_1_waken_pins[] = { 79, };
347static int mt7622_pcie0_1_waken_funcs[] = { 4, };
348static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
349static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
350static int mt7622_pcie1_0_waken_pins[] = { 14, };
351static int mt7622_pcie1_0_waken_funcs[] = { 3, };
352static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
353static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
354
355static int mt7622_pcie0_pad_perst_pins[] = { 83, };
356static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
357static int mt7622_pcie1_pad_perst_pins[] = { 84, };
358static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
359
360/* PMIC bus */
361static int mt7622_pmic_bus_pins[] = { 71, 72, };
362static int mt7622_pmic_bus_funcs[] = { 0, 0, };
363
364/* Parallel NAND */
365static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
366 48, 49, 50, };
367static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
368 0, };
369
370/* PWM */
371static int mt7622_pwm_ch1_0_pins[] = { 51, };
372static int mt7622_pwm_ch1_0_funcs[] = { 3, };
373static int mt7622_pwm_ch1_1_pins[] = { 73, };
374static int mt7622_pwm_ch1_1_funcs[] = { 4, };
375static int mt7622_pwm_ch1_2_pins[] = { 95, };
376static int mt7622_pwm_ch1_2_funcs[] = { 0, };
377static int mt7622_pwm_ch2_0_pins[] = { 52, };
378static int mt7622_pwm_ch2_0_funcs[] = { 3, };
379static int mt7622_pwm_ch2_1_pins[] = { 74, };
380static int mt7622_pwm_ch2_1_funcs[] = { 4, };
381static int mt7622_pwm_ch2_2_pins[] = { 96, };
382static int mt7622_pwm_ch2_2_funcs[] = { 0, };
383static int mt7622_pwm_ch3_0_pins[] = { 53, };
384static int mt7622_pwm_ch3_0_funcs[] = { 3, };
385static int mt7622_pwm_ch3_1_pins[] = { 75, };
386static int mt7622_pwm_ch3_1_funcs[] = { 4, };
387static int mt7622_pwm_ch3_2_pins[] = { 97, };
388static int mt7622_pwm_ch3_2_funcs[] = { 0, };
389static int mt7622_pwm_ch4_0_pins[] = { 54, };
390static int mt7622_pwm_ch4_0_funcs[] = { 3, };
391static int mt7622_pwm_ch4_1_pins[] = { 67, };
392static int mt7622_pwm_ch4_1_funcs[] = { 3, };
393static int mt7622_pwm_ch4_2_pins[] = { 76, };
394static int mt7622_pwm_ch4_2_funcs[] = { 4, };
395static int mt7622_pwm_ch4_3_pins[] = { 98, };
396static int mt7622_pwm_ch4_3_funcs[] = { 0, };
397static int mt7622_pwm_ch5_0_pins[] = { 68, };
398static int mt7622_pwm_ch5_0_funcs[] = { 3, };
399static int mt7622_pwm_ch5_1_pins[] = { 77, };
400static int mt7622_pwm_ch5_1_funcs[] = { 4, };
401static int mt7622_pwm_ch5_2_pins[] = { 99, };
402static int mt7622_pwm_ch5_2_funcs[] = { 0, };
403static int mt7622_pwm_ch6_0_pins[] = { 69, };
404static int mt7622_pwm_ch6_0_funcs[] = { 3, };
405static int mt7622_pwm_ch6_1_pins[] = { 78, };
406static int mt7622_pwm_ch6_1_funcs[] = { 4, };
407static int mt7622_pwm_ch6_2_pins[] = { 81, };
408static int mt7622_pwm_ch6_2_funcs[] = { 4, };
409static int mt7622_pwm_ch6_3_pins[] = { 100, };
410static int mt7622_pwm_ch6_3_funcs[] = { 0, };
411static int mt7622_pwm_ch7_0_pins[] = { 70, };
412static int mt7622_pwm_ch7_0_funcs[] = { 3, };
413static int mt7622_pwm_ch7_1_pins[] = { 82, };
414static int mt7622_pwm_ch7_1_funcs[] = { 4, };
415static int mt7622_pwm_ch7_2_pins[] = { 101, };
416static int mt7622_pwm_ch7_2_funcs[] = { 0, };
417
418/* SD */
419static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
420static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
421static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
422static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
423
424/* Serial NAND */
425static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
426static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
427
428/* SPI NOR */
429static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
430static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
431
432/* SPIC */
433static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
434static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
435static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
436static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
437static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
438static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
439static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
440static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
441static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
442static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
443static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
444static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
445
446/* TDM */
447static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
448static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
449static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
450static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
451static int mt7622_tdm_0_out_data_pins[] = { 20, };
452static int mt7622_tdm_0_out_data_funcs[] = { 3, };
453static int mt7622_tdm_0_in_data_pins[] = { 21, };
454static int mt7622_tdm_0_in_data_funcs[] = { 3, };
455static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
456static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
457static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
458static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
459static int mt7622_tdm_1_out_data_pins[] = { 55, };
460static int mt7622_tdm_1_out_data_funcs[] = { 3, };
461static int mt7622_tdm_1_in_data_pins[] = { 56, };
462static int mt7622_tdm_1_in_data_funcs[] = { 3, };
463
464/* UART */
465static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
466static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
467static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
468static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
469static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
470static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
471static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
472static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
473static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
474static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
475static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
476static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
477static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
478static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
479static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
480static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
481static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
482static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
483static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
484static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
485static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
486static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
487static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
488static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
489static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
490static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
491static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
492static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
493static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
494static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
495static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
496static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
497static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
498static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
499static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
500static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
501static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
502static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
503static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
504static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
505
506/* Watchdog */
507static int mt7622_watchdog_pins[] = { 78, };
508static int mt7622_watchdog_funcs[] = { 0, };
509
510/* WLAN LED */
511static int mt7622_wled_pins[] = { 85, };
512static int mt7622_wled_funcs[] = { 0, };
513
514static const struct mtk_group_desc mt7622_groups[] = {
515 PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
516 PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
517 PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
518 PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
519 PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
520 PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
521 PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
522 PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
523 PINCTRL_PIN_GROUP("esw", mt7622_esw),
524 PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
525 PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
526 PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
527 PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
528 PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
529 PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
530 PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
531 PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
532 PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
533 PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
534 PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
535 PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
536 PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
537 PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
538 PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
539 PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
540 PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
541 PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
542 PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
543 PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
544 PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
545 PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
546 PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
547 PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
548 PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
549 PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
550 PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
551 PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
552 PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
553 PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
554 PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
555 PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
556 PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
557 PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
558 PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
559 PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
560 PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
561 PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
562 PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
563 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
564 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
565 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
566 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
567 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
568 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
569 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
570 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
571 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
572 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
573 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
574 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
575 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
576 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
577 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
578 PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
579 PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
580 PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
581 PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
582 PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
583 PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
584 PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
585 PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
586 PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
587 PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
588 PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
589 PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
590 PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
591 PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
592 PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
593 PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
594 PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
595 PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
596 PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
597 mt7622_tdm_0_out_mclk_bclk_ws),
598 PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
599 mt7622_tdm_0_in_mclk_bclk_ws),
600 PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
601 PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
602 PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
603 mt7622_tdm_1_out_mclk_bclk_ws),
604 PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
605 mt7622_tdm_1_in_mclk_bclk_ws),
606 PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
607 PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
608 PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
609 PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
610 PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
611 PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
612 PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
613 PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
614 PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
615 PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
616 PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
617 PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
618 PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
619 PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
620 PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
621 PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
622 PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
623 PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
624 PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
625 PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
626 PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
627 PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
628 PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
629 PINCTRL_PIN_GROUP("wled", mt7622_wled),
630};
631
632/* Joint those groups owning the same capability in user point of view which
633 * allows that people tend to use through the device tree.
634 */
635static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
636static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
637 "esw_p2_p3_p4", "mdc_mdio",
638 "rgmii_via_gmac1",
639 "rgmii_via_gmac2",
640 "rgmii_via_esw", };
641static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
642 "i2c1_2", "i2c2_0", "i2c2_1",
643 "i2c2_2", };
644static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
645 "i2s_in_mclk_bclk_ws",
646 "i2s1_in_data", "i2s2_in_data",
647 "i2s3_in_data", "i2s4_in_data",
648 "i2s1_out_data", "i2s2_out_data",
649 "i2s3_out_data", "i2s4_out_data", };
650static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
651 "ir_0_rx", "ir_1_rx", "ir_2_rx"};
652static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
653 "ephy1_led", "ephy2_led",
654 "ephy3_led", "ephy4_led",
655 "wled", };
656static const char *const mt7622_flash_groups[] = { "par_nand", "snfi",
657 "spi_nor"};
658static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken",
659 "pcie0_0_clkreq", "pcie0_1_waken",
660 "pcie0_1_clkreq", "pcie1_0_waken",
661 "pcie1_0_clkreq", "pcie0_pad_perst",
662 "pcie1_pad_perst", };
663static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", };
664static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
665 "pwm_ch1_2", "pwm_ch2_0",
666 "pwm_ch2_1", "pwm_ch2_2",
667 "pwm_ch3_0", "pwm_ch3_1",
668 "pwm_ch3_2", "pwm_ch4_0",
669 "pwm_ch4_1", "pwm_ch4_2",
670 "pwm_ch4_3", "pwm_ch5_0",
671 "pwm_ch5_1", "pwm_ch5_2",
672 "pwm_ch6_0", "pwm_ch6_1",
673 "pwm_ch6_2", "pwm_ch6_3",
674 "pwm_ch7_0", "pwm_ch7_1",
675 "pwm_ch7_2", };
676static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", };
677static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1",
678 "spic1_0", "spic1_1", "spic2_0",
679 "spic2_0_wp_hold", };
680static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
681 "tdm_0_in_mclk_bclk_ws",
682 "tdm_0_out_data",
683 "tdm_0_in_data",
684 "tdm_1_out_mclk_bclk_ws",
685 "tdm_1_in_mclk_bclk_ws",
686 "tdm_1_out_data",
687 "tdm_1_in_data", };
688
689static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx",
690 "uart1_0_tx_rx", "uart1_0_rts_cts",
691 "uart1_1_tx_rx", "uart1_1_rts_cts",
692 "uart2_0_tx_rx", "uart2_0_rts_cts",
693 "uart2_1_tx_rx", "uart2_1_rts_cts",
694 "uart2_2_tx_rx", "uart2_2_rts_cts",
695 "uart2_3_tx_rx",
696 "uart3_0_tx_rx",
697 "uart3_1_tx_rx", "uart3_1_rts_cts",
698 "uart4_0_tx_rx",
699 "uart4_1_tx_rx", "uart4_1_rts_cts",
700 "uart4_2_tx_rx",
701 "uart4_2_rts_cts",};
702static const char *const mt7622_wdt_groups[] = { "watchdog", };
703
704static const struct mtk_function_desc mt7622_functions[] = {
705 {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
706 {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
707 {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
708 {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
709 {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
710 {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
711 {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
712 {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
713 {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
714 {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
715 {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
716 {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
717 {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
718 {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
719 {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
720};
721
722static struct mtk_pinctrl_soc mt7622_data = {
723 .name = "mt7622_pinctrl",
724 .reg_cal = mt7622_reg_cals,
725 .pins = mt7622_pins,
726 .npins = ARRAY_SIZE(mt7622_pins),
727 .grps = mt7622_groups,
728 .ngrps = ARRAY_SIZE(mt7622_groups),
729 .funcs = mt7622_functions,
730 .nfuncs = ARRAY_SIZE(mt7622_functions),
developer74d69012020-01-10 16:30:28 +0800[diff] [blame]731 .gpio_mode = 1,
732 .rev = MTK_PINCTRL_V0,
developer2a2b17f2020-01-10 16:30:27 +0800[diff] [blame]733};
734
735static int mtk_pinctrl_mt7622_probe(struct udevice *dev)
736{
737 return mtk_pinctrl_common_probe(dev, &mt7622_data);
738}
739
740static const struct udevice_id mt7622_pctrl_match[] = {
741 { .compatible = "mediatek,mt7622-pinctrl" },
742 { /* sentinel */ }
743};
744
745U_BOOT_DRIVER(mt7622_pinctrl) = {
746 .name = "mt7622_pinctrl",
747 .id = UCLASS_PINCTRL,
748 .of_match = mt7622_pctrl_match,
749 .ops = &mtk_pinctrl_ops,
750 .probe = mtk_pinctrl_mt7622_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700[diff] [blame]751 .priv_auto = sizeof(struct mtk_pinctrl_priv),
developer2a2b17f2020-01-10 16:30:27 +0800[diff] [blame]752};
753
754