blob: dfbd51c92468dcd3b99b6c413ee43113360702a8 [file] [log] [blame]
Stefan Roeseede2c662021-04-07 09:12:38 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell / Cavium Inc. NIC23
4 */
5
6/dts-v1/;
7
8#include "mrvl,cn73xx.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 model = "cavium,nic23";
13 compatible = "cavium,nic23";
14
15 aliases {
16 mmc0 = &mmc0;
17 serial0 = &uart0;
18 spi0 = &spi;
19 };
20
21 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 /* Power on GPIO 8, active high */
27 reg_mmc_3v3: regulator@0 {
28 compatible = "regulator-fixed";
29 reg = <0>;
30 regulator-name = "mmc-3v3";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
34 enable-active-high;
35 };
36 };
37
38 chosen {
39 stdout-path = &uart0;
40 };
41};
42
43&bootbus {
44 /*
45 * bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
46 * as the initial size is too small for the 8MiB flash device
47 */
48 ranges = <0 0 0 0x1f400000 0xc00000>,
49 <1 0 0x10000 0x10000000 0>,
50 <2 0 0x10000 0x20000000 0>,
51 <3 0 0x10000 0x30000000 0>,
52 <4 0 0 0x1d020000 0x10000>,
53 <5 0 0x10000 0x50000000 0>,
54 <6 0 0x10000 0x60000000 0>,
55 <7 0 0x10000 0x70000000 0>;
56
57 cavium,cs-config@0 {
58 compatible = "cavium,octeon-3860-bootbus-config";
59 cavium,cs-index = <0>;
60 cavium,t-adr = <10>;
61 cavium,t-ce = <50>;
62 cavium,t-oe = <50>;
63 cavium,t-we = <35>;
64 cavium,t-rd-hld = <25>;
65 cavium,t-wr-hld = <35>;
66 cavium,t-pause = <0>;
67 cavium,t-wait = <50>;
68 cavium,t-page = <30>;
69 cavium,t-rd-dly = <0>;
70 cavium,page-mode = <1>;
71 cavium,pages = <8>;
72 cavium,bus-width = <8>;
73 };
74
75 cavium,cs-config@4 {
76 compatible = "cavium,octeon-3860-bootbus-config";
77 cavium,cs-index = <4>;
78 cavium,t-adr = <10>;
79 cavium,t-ce = <10>;
80 cavium,t-oe = <160>;
81 cavium,t-we = <100>;
82 cavium,t-rd-hld = <10>;
83 cavium,t-wr-hld = <0>;
84 cavium,t-pause = <50>;
85 cavium,t-wait = <50>;
86 cavium,t-page = <10>;
87 cavium,t-rd-dly = <10>;
88 cavium,pages = <0>;
89 cavium,bus-width = <8>;
90 };
91
92 flash0: nor@0,0 {
93 compatible = "cfi-flash";
94 reg = <0 0 0x800000>;
95 #address-cells = <1>;
96 #size-cells = <1>;
97 partition@0 {
98 label = "bootloader";
99 reg = <0 0x340000>;
100 read-only;
101 };
102 partition@300000 {
103 label = "storage";
104 reg = <0x340000 0x4be000>;
105 };
106 partition@7fe000 {
107 label = "environment";
108 reg = <0x7fe000 0x2000>;
109 read-only;
110 };
111 };
112};
113
114&uart0 {
115 clock-frequency = <800000000>;
116};
117
118&i2c0 {
119 u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
120 clock-frequency = <100000>;
Stefan Roeseee4b8f22022-04-07 09:11:51 +0200121
122 sfp0eeprom: eeprom@50 {
123 compatible = "atmel,24c01";
124 reg = <0x50>;
125 };
126
127 sfp0alerts: eeprom@51 {
128 compatible = "atmel,24c01";
129 reg = <0x51>;
130 };
Stefan Roeseede2c662021-04-07 09:12:38 +0200131};
132
133&i2c1 {
134 u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
135 clock-frequency = <100000>;
Stefan Roeseee4b8f22022-04-07 09:11:51 +0200136
137 vitesse@10 {
138 compatible = "vitesse,vsc7224";
139 reg = <0x10>;
140 #address-cells = <1>;
141 #size-cells = <0>;
142
143 /* Note that reset is active high with this device */
144 reset = <&gpio 7 0>;
145
146 /* LoS pin can be pulled low when there is a loss of signal */
147 los = <&gpio 6 0>;
148
149 vitesse,reg-init =
150 /* Clear all masks */
151 /* Page select FSYNC0 (0x30) */
152 <0x7f 0x0030>,
153 /* Set FSYNC0 for 10.3125Gbps */
154 <0x80 0x2841>, /* See Table 3. */
155 <0x81 0x0008>,
156 <0x82 0xc000>,
157 <0x83 0x0010>,
158 <0x84 0x1d00>,
159
160 /* All channels Rx settings set equally */
161 <0x7f 0x0050>,
162 /* Shrink EQ_BUFF */
163 <0x82 0x0014>,
164 /* Set EQVGA_ADAP = 1 (enable EQVGA circuitry),
165 * USE_UNIT_GAIN = 1 (EQVGA is in unity gain),
166 * USE_LPF = 0 (VGA adapt not using LPF),
167 * USE_EQVGA = 1
168 <0x89 0x7f13>,
169 /* Select min DFE Delay (DFE_DELAY) */
170 <0x90 0x5785>,
171 /* Set DFE 1-3 limit (DXMAX) = 32dec,
172 * AP Max limit = 127 decimal
173 */
174 <0x92 0x207f>,
175 /* Set AP Min limit = 32 decimal */
176 <0x93 0x2000>,
177 /* Set DFE Averaging to the slowest (DFE_AVG) */
178 <0x94 0x0031>,
179 /* Set Inductor Bypass OD_IND_BYP = 0 & fastest Rise/Fall */
180 <0x9c 0x0000>,
181 /* Setting DFE Boost = none. Must set for
182 * rev C (if DFE in adapt mode)
183 */
184 <0xaa 0x0888>,
185 /* Setting EQ Min = 8 & Max limit = 72 dec.
186 * Must set for rev C, otherwise EQ is 0
187 * (if EQ is in adaptive mode)
188 */
189 <0xa8 0x2408>,
190 /* Setting EQVGA = 96, when in EQVGA manual mode */
191 <0xa9 0x0060>,
192 /* Setting SW_BFOCM, bits 15:14 to 01 */
193 <0x87 0x4021>,
194 /* Turn off adaptive input equalization
195 * and VGA adaptive algorithm control.
196 */
197 <0x89 0x7313>,
198 /* Turn on adaptive input equalization
199 * and VGA adaptive algorithm control.
200 */
201 <0x89 0x7f13>;
202
203 vitesse-channel@0 {
204 compatible = "vitesse,vsc7224-channel";
205 reg = <0>;
206 direction-tx;
207 sfp-mac = <&eth0>;
208
209 /* TAP settings. The format of this is as
210 * follows:
211 * - cable length in meters, 0 = active or
212 * optical module
213 * - maintap value
214 * - pretap value
215 * - posttap value
216 *
217 * For the cable length, the value will apply
218 * for that cable length and greater until the
219 * next largest cable length specified. These
220 * values must be ordered first by channel mask
221 * then by cable length. These are typically
222 * set for the transmit channels, not the
223 * receive channels.
224 */
225 taps = <0 0x0013 0x000f 0x0000>,
226 <1 0x001f 0x000f 0x0004>,
227 <3 0x0014 0x000b 0x0004>,
228 <5 0x0014 0x0009 0x0006>,
229 <7 0x0014 0x000f 0x0000>,
230 <10 0x0012 0x000b 0x0013>;
231 };
232
233 vitesse-channel@1 {
234 compatible = "vitesse,vsc7224-channel";
235 reg = <1>;
236 /* Ignore mod_abs and module */
237 direction-rx;
238 sfp-mac = <&eth0>;
239
240 /* Disable pre-tap */
241 pretap-disable;
242
243 /* Disable post-tap */
244 posttap-disable;
245
246 /* Taps has the following fields:
247 * - cable length (ignored for rx)
248 * - main tap value
249 * - pre tap value
250 * - post tap value
251 *
252 * NOTE: if taps are disabled then they
253 * are not programmed.
254 */
255 taps = <0 0x0a 0x0b 0x10>;
256 };
257
258 vitesse-channel@2 {
259 compatible = "vitesse,vsc7224-channel";
260 reg = <2>;
261 direction-tx;
262 sfp-mac = <&eth1>;
263
264 /* TAP settings. The format of this is as
265 * follows:
266 * - cable length in meters, 0 = active or
267 * optical module
268 * - maintap value
269 * - pretap value
270 * - posttap value
271 *
272 * For the cable length, the value will apply
273 * for that cable length and greater until the
274 * next largest cable length specified. These
275 * values must be ordered first by channel mask
276 * then by cable length. These are typically
277 * set for the transmit channels, not the
278 * receive channels.
279 */
280 taps = <0 0x0013 0x000f 0x0000>,
281 <1 0x001f 0x000f 0x0004>,
282 <3 0x0014 0x000b 0x0004>,
283 <5 0x0014 0x0009 0x0006>,
284 <7 0x0014 0x000f 0x0000>,
285 <10 0x0012 0x000b 0x0013>;
286 };
287
288 vitesse-channel@3 {
289 compatible = "vitesse,vsc7224-channel";
290 reg = <3>;
291 /* Ignore mod_abs and module */
292 direction-rx;
293 sfp-mac = <&eth1>;
294
295 /* Disable pre-tap */
296 pretap-disable;
297
298 /* Disable post-tap */
299 posttap-disable;
300
301 /* Taps has the following fields:
302 * - cable length (ignored for rx)
303 * - main tap value
304 * - pre tap value
305 * - post tap value
306 *
307 * NOTE: if taps are disabled then they
308 * are not programmed.
309 */
310 taps = <0 0x0a 0x0b 0x10>;
311 };
312 };
313
314 sfp1eeprom: eeprom@50 {
315 compatible = "atmel,24c01";
316 reg = <0x50>;
317 };
318
319 sfp1alerts: eeprom@51 {
320 compatible = "atmel,24c01";
321 reg = <0x51>;
322 };
Stefan Roeseede2c662021-04-07 09:12:38 +0200323};
324
325&mmc {
326 status = "okay";
327
328 mmc0: mmc-slot@0 {
329 compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot";
330 reg = <0>;
331 vqmmc-supply = <&reg_mmc_3v3>;
332 voltage-ranges = <3300 3300>;
333 spi-max-frequency = <52000000>;
334 /* bus width can be 1, 4 or 8 */
335 bus-width = <8>; /* new std property */
336 cavium,bus-max-width = <8>; /* custom property */
337 non-removable;
338 };
339};
340
341&soc0 {
342 pci-console@0 {
343 compatible = "marvell,pci-console";
344 status = "okay";
345 };
346
347 pci-bootcmd@0 {
348 compatible = "marvell,pci-bootcmd";
349 status = "okay";
350 };
Stefan Roeseee4b8f22022-04-07 09:11:51 +0200351
352 sfp0: sfp-slot@0 {
353 compatible = "ethernet,sfp-slot";
354 tx_disable = <&gpio 16 0>;
355 mod_abs = <&gpio 17 0>;
356 tx_error = <&gpio 19 0>;
357 rx_los = <&gpio 18 0>;
358 eeprom = <&sfp0eeprom>;
359 diag = <&sfp0alerts>;
360 };
361
362 sfp1: sfp-slot@1 {
363 compatible = "ethernet,sfp-slot";
364 tx_disable = <&gpio 21 0>;
365 mod_abs = <&gpio 22 0>;
366 tx_error = <&gpio 24 0>;
367 rx_los = <&gpio 23 0>;
368 eeprom = <&sfp1eeprom>;
369 diag = <&sfp1alerts>;
370 };
Stefan Roeseede2c662021-04-07 09:12:38 +0200371};
372
373&spi {
374 flash@0 {
375 compatible = "micron,n25q128a11", "jedec,spi-nor";
376 spi-max-frequency = <2000000>;
377 reg = <0>;
378 };
379};
Stefan Roeseee4b8f22022-04-07 09:11:51 +0200380
381/* BGX 2 */
382&bgx2 {
383 status = "okay";
384
385 /* SerDes 0, may differ from PCS Lane/LMAC */
386 eth0: ethernet-mac@0 {
387 compatible = "cavium,octeon-7890-bgx-port";
388 reg = <0>;
389 local-mac-address = [ 00 00 00 00 00 00 ];
390 sfp-slot = <&sfp0>;
391 };
392
393 /* SerDes 1, may differ from PCS Lane/LMAC */
394 eth1: ethernet-mac@1 {
395 compatible = "cavium,octeon-7890-bgx-port";
396 reg = <1>;
397 local-mac-address = [ 00 00 00 00 00 00 ];
398 sfp-slot = <&sfp1>;
399 };
400};