Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / ee4a427cec5182879b1570b13c7d5e65948f30b7 / . / board / terasic / de0-nano-soc / qts / sdram_config.h
blob: d96b28af82f31235290f1f12745dfb896b0df1c8 [file] [log] [blame]
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]1/*
2 * Altera SoCFPGA SDRAM configuration
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef __SDRAM_CONFIG_H
7#define __SDRAM_CONFIG_H
8
9#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
10#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
11#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
12#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
13#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
14#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
15#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
16#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
17#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
18#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
19#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
20#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
21#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
22#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
23#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
24#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
25#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
26#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
27#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
28#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
29#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
30#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
31#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
32#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
33#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
34#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
35#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
36#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
37#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
38#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
39#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
40#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
41#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
42#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
43#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
44#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
Chin Liang Seeff38f262016-09-21 10:26:03 +0800[diff] [blame]45#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
46#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
47#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]48#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
49#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
50#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
51#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
52#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
53#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
54#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
55#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
56#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
57#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
58#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
59#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
60#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
61#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
62
63#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
64#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
65#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
66#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
67#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
68#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
69#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
70#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
71#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
72#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
73#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
74#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
75#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
76#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
77#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
78#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
79#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
80#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
81#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
82#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
83
84/* Sequencer auto configuration */
85#define RW_MGR_ACTIVATE_0_AND_1 0x0D
86#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
87#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
88#define RW_MGR_ACTIVATE_1 0x0F
89#define RW_MGR_CLEAR_DQS_ENABLE 0x49
90#define RW_MGR_GUARANTEED_READ 0x4C
91#define RW_MGR_GUARANTEED_READ_CONT 0x54
92#define RW_MGR_GUARANTEED_WRITE 0x18
93#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
94#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
95#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
96#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
97#define RW_MGR_IDLE 0x00
98#define RW_MGR_IDLE_LOOP1 0x7B
99#define RW_MGR_IDLE_LOOP2 0x7A
100#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
101#define RW_MGR_INIT_RESET_1_CKE_0 0x74
102#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
103#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
104#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
105#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
106#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
107#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
108#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
109#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
110#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
111#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
112#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
113#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
114#define RW_MGR_MRS0_DLL_RESET 0x02
115#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
116#define RW_MGR_MRS0_USER 0x07
117#define RW_MGR_MRS0_USER_MIRR 0x0C
118#define RW_MGR_MRS1 0x03
119#define RW_MGR_MRS1_MIRR 0x09
120#define RW_MGR_MRS2 0x04
121#define RW_MGR_MRS2_MIRR 0x0A
122#define RW_MGR_MRS3 0x05
123#define RW_MGR_MRS3_MIRR 0x0B
124#define RW_MGR_PRECHARGE_ALL 0x12
125#define RW_MGR_READ_B2B 0x59
126#define RW_MGR_READ_B2B_WAIT1 0x61
127#define RW_MGR_READ_B2B_WAIT2 0x6B
128#define RW_MGR_REFRESH_ALL 0x14
129#define RW_MGR_RETURN 0x01
130#define RW_MGR_SGLE_READ 0x7D
131#define RW_MGR_ZQCL 0x06
132
133/* Sequencer defines configuration */
134#define AFI_RATE_RATIO 1
135#define CALIB_LFIFO_OFFSET 8
136#define CALIB_VFIFO_OFFSET 6
137#define ENABLE_SUPER_QUICK_CALIBRATION 0
138#define IO_DELAY_PER_DCHAIN_TAP 25
139#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
140#define IO_DELAY_PER_OPA_TAP 312
141#define IO_DLL_CHAIN_LENGTH 8
142#define IO_DQDQS_OUT_PHASE_MAX 0
143#define IO_DQS_EN_DELAY_MAX 31
144#define IO_DQS_EN_DELAY_OFFSET 0
145#define IO_DQS_EN_PHASE_MAX 7
146#define IO_DQS_IN_DELAY_MAX 31
147#define IO_DQS_IN_RESERVE 4
148#define IO_DQS_OUT_RESERVE 4
149#define IO_IO_IN_DELAY_MAX 31
150#define IO_IO_OUT1_DELAY_MAX 31
151#define IO_IO_OUT2_DELAY_MAX 0
152#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
153#define MAX_LATENCY_COUNT_WIDTH 5
154#define READ_VALID_FIFO_SIZE 16
155#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
156#define RW_MGR_MEM_ADDRESS_MIRRORING 0
157#define RW_MGR_MEM_DATA_MASK_WIDTH 4
158#define RW_MGR_MEM_DATA_WIDTH 32
159#define RW_MGR_MEM_DQ_PER_READ_DQS 8
160#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
161#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
162#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
163#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
164#define RW_MGR_MEM_NUMBER_OF_RANKS 1
165#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
166#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
167#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
168#define TINIT_CNTR0_VAL 99
169#define TINIT_CNTR1_VAL 32
170#define TINIT_CNTR2_VAL 32
171#define TRESET_CNTR0_VAL 99
172#define TRESET_CNTR1_VAL 99
173#define TRESET_CNTR2_VAL 10
174
175/* Sequencer ac_rom_init configuration */
176const u32 ac_rom_init[] = {
177 0x20700000,
178 0x20780000,
179 0x10080431,
180 0x10080530,
181 0x10090044,
182 0x100a0010,
183 0x100b0000,
184 0x10380400,
185 0x10080449,
186 0x100804c8,
187 0x100a0024,
188 0x10090008,
189 0x100b0000,
190 0x30780000,
191 0x38780000,
192 0x30780000,
193 0x10680000,
194 0x106b0000,
195 0x10280400,
196 0x10480000,
197 0x1c980000,
198 0x1c9b0000,
199 0x1c980008,
200 0x1c9b0008,
201 0x38f80000,
202 0x3cf80000,
203 0x38780000,
204 0x18180000,
205 0x18980000,
206 0x13580000,
207 0x135b0000,
208 0x13580008,
209 0x135b0008,
210 0x33780000,
211 0x10580008,
212 0x10780000
213};
214
215/* Sequencer inst_rom_init configuration */
216const u32 inst_rom_init[] = {
217 0x80000,
218 0x80680,
219 0x8180,
220 0x8200,
221 0x8280,
222 0x8300,
223 0x8380,
224 0x8100,
225 0x8480,
226 0x8500,
227 0x8580,
228 0x8600,
229 0x8400,
230 0x800,
231 0x8680,
232 0x880,
233 0xa680,
234 0x80680,
235 0x900,
236 0x80680,
237 0x980,
238 0xa680,
239 0x8680,
240 0x80680,
241 0xb68,
242 0xcce8,
243 0xae8,
244 0x8ce8,
245 0xb88,
246 0xec88,
247 0xa08,
248 0xac88,
249 0x80680,
250 0xce00,
251 0xcd80,
252 0xe700,
253 0xc00,
254 0x20ce0,
255 0x20ce0,
256 0x20ce0,
257 0x20ce0,
258 0xd00,
259 0x680,
260 0x680,
261 0x680,
262 0x680,
263 0x60e80,
264 0x61080,
265 0x61080,
266 0x61080,
267 0xa680,
268 0x8680,
269 0x80680,
270 0xce00,
271 0xcd80,
272 0xe700,
273 0xc00,
274 0x30ce0,
275 0x30ce0,
276 0x30ce0,
277 0x30ce0,
278 0xd00,
279 0x680,
280 0x680,
281 0x680,
282 0x680,
283 0x70e80,
284 0x71080,
285 0x71080,
286 0x71080,
287 0xa680,
288 0x8680,
289 0x80680,
290 0x1158,
291 0x6d8,
292 0x80680,
293 0x1168,
294 0x7e8,
295 0x7e8,
296 0x87e8,
297 0x40fe8,
298 0x410e8,
299 0x410e8,
300 0x410e8,
301 0x1168,
302 0x7e8,
303 0x7e8,
304 0xa7e8,
305 0x80680,
306 0x40e88,
307 0x41088,
308 0x41088,
309 0x41088,
310 0x40f68,
311 0x410e8,
312 0x410e8,
313 0x410e8,
314 0xa680,
315 0x40fe8,
316 0x410e8,
317 0x410e8,
318 0x410e8,
319 0x41008,
320 0x41088,
321 0x41088,
322 0x41088,
323 0x1100,
324 0xc680,
325 0x8680,
326 0xe680,
327 0x80680,
328 0x0,
329 0x8000,
330 0xa000,
331 0xc000,
332 0x80000,
333 0x80,
334 0x8080,
335 0xa080,
336 0xc080,
337 0x80080,
338 0x9180,
339 0x8680,
340 0xa680,
341 0x80680,
342 0x40f08,
343 0x80680
344};
345#endif /*#ifndef__SDRAM_CONFIG_H */