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git01.mediatek.com / filogic / uboot / ee4a427cec5182879b1570b13c7d5e65948f30b7 / . / board / seco / common / mx6.c
blob: ad4bb5bed74dc61539b8cbca74fac9c991b81c17 [file] [log] [blame]
Boris BREZILLON7832bf32015-03-04 13:13:05 +0100[diff] [blame]1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2015 ECA Sinters
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
14#include <asm/arch/mx6-pins.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +0900[diff] [blame]15#include <linux/errno.h>
Boris BREZILLON7832bf32015-03-04 13:13:05 +0100[diff] [blame]16#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +0200[diff] [blame]17#include <asm/mach-imx/iomux-v3.h>
18#include <asm/mach-imx/boot_mode.h>
Boris BREZILLON7832bf32015-03-04 13:13:05 +0100[diff] [blame]19#include <mmc.h>
20#include <fsl_esdhc.h>
21#include <miiphy.h>
22#include <netdev.h>
23#include <asm/arch/mxc_hdmi.h>
24#include <asm/arch/crm_regs.h>
25#include <linux/fb.h>
26#include <ipu_pixfmt.h>
27#include <asm/io.h>
28#include <asm/arch/sys_proto.h>
29#include <micrel.h>
Stefano Babic33731bc2017-06-29 10:16:06 +0200[diff] [blame]30#include <asm/mach-imx/mxc_i2c.h>
Boris BREZILLON7832bf32015-03-04 13:13:05 +0100[diff] [blame]31#include <i2c.h>
32
33#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37static iomux_v3_cfg_t const uart2_pads[] = {
38 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
39 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
40};
41
42void seco_mx6_setup_uart_iomux(void)
43{
44 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
45}
46
47#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
48 PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_40ohm | \
50 PAD_CTL_HYS)
51
52static iomux_v3_cfg_t const enet_pads[] = {
53 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
54 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
55 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
56 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
68};
69
70void seco_mx6_setup_enet_iomux(void)
71{
72 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
73}
74
75int seco_mx6_rgmii_rework(struct phy_device *phydev)
76{
77 /* control data pad skew - devaddr = 0x02, register = 0x04 */
78 ksz9031_phy_extended_write(phydev, 0x02,
79 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
80 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
81 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
82 ksz9031_phy_extended_write(phydev, 0x02,
83 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
84 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
85 /* tx data pad skew - devaddr = 0x02, register = 0x05 */
86 ksz9031_phy_extended_write(phydev, 0x02,
87 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
88 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
89
90 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
91 ksz9031_phy_extended_write(phydev, 0x02,
92 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
93 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
94 return 0;
95}
96
97#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
98 PAD_CTL_SPEED_LOW | \
99 PAD_CTL_DSE_80ohm | \
100 PAD_CTL_SRE_FAST | \
101 PAD_CTL_HYS)
102
103static iomux_v3_cfg_t const usdhc3_pads[] = {
104 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110};
111
112static iomux_v3_cfg_t const usdhc4_pads[] = {
113 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119};
120
121void seco_mx6_setup_usdhc_iomux(int id)
122{
123 switch (id) {
124 case 3:
125 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
126 ARRAY_SIZE(usdhc3_pads));
127 break;
128
129 case 4:
130 imx_iomux_v3_setup_multiple_pads(usdhc4_pads,
131 ARRAY_SIZE(usdhc4_pads));
132 break;
133
134 default:
135 printf("Warning: invalid usdhc id (%d)\n", id);
136 break;
137 }
138}