| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Thierry Reding | 09c0cf2 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 NVIDIA Corporation |
| Thierry Reding | 09c0cf2 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __POWER_AS3722_H__ |
| 7 | #define __POWER_AS3722_H__ |
| 8 | |
| Thierry Reding | 09c0cf2 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 9 | #define AS3722_GPIO_OUTPUT_VDDH (1 << 0) |
| 10 | #define AS3722_GPIO_INVERT (1 << 1) |
| 11 | |
| Simon Glass | 8f18951 | 2017-07-25 08:30:10 -0600 | [diff] [blame] | 12 | #define AS3722_DEVICE_ID 0x0c |
| 13 | #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) |
| 14 | #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) |
| 15 | #define AS3722_SD_CONTROL 0x4d |
| Marcel Ziswiler | ee107b3 | 2018-05-08 17:34:08 +0200 | [diff] [blame^] | 16 | #define AS3722_LDO_CONTROL0 0x4e |
| 17 | #define AS3722_LDO_CONTROL1 0x4f |
| Simon Glass | 8f18951 | 2017-07-25 08:30:10 -0600 | [diff] [blame] | 18 | #define AS3722_ASIC_ID1 0x90 |
| 19 | #define AS3722_ASIC_ID2 0x91 |
| 20 | |
| Simon Glass | c30ddcc | 2017-07-25 08:30:11 -0600 | [diff] [blame] | 21 | #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) |
| Simon Glass | b3d2ed3 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 22 | #define AS3722_GPIO_SIGNAL_OUT 0x20 |
| Simon Glass | c30ddcc | 2017-07-25 08:30:11 -0600 | [diff] [blame] | 23 | #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) |
| 24 | #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) |
| 25 | #define AS3722_GPIO_CONTROL_INVERT (1 << 7) |
| 26 | |
| Simon Glass | b3d2ed3 | 2017-07-25 08:30:12 -0600 | [diff] [blame] | 27 | int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value); |
| Thierry Reding | 09c0cf2 | 2014-12-09 22:25:05 -0700 | [diff] [blame] | 28 | |
| 29 | #endif /* __POWER_AS3722_H__ */ |