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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek04b7e622015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek04b7e622015-01-15 10:01:51 +01005 */
6
7#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glassa9dc0682019-12-28 10:44:59 -07009#include <time.h>
Michal Simek0ca55572015-04-15 14:59:19 +020010#include <asm/arch/clk.h>
Michal Simek04b7e622015-01-15 10:01:51 +010011#include <asm/arch/hardware.h>
12#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Michal Simek04b7e622015-01-15 10:01:51 +010014
15DECLARE_GLOBAL_DATA_PTR;
16
Michal Simekc23d3f82015-11-05 08:34:35 +010017unsigned long zynqmp_get_system_timer_freq(void)
18{
19 u32 ver = zynqmp_get_silicon_version();
20
21 switch (ver) {
Michal Simekc23d3f82015-11-05 08:34:35 +010022 case ZYNQMP_CSU_VERSION_QEMU:
23 return 50000000;
24 }
25
26 return 100000000;
27}
28
Michal Simek04b7e622015-01-15 10:01:51 +010029#ifdef CONFIG_CLOCKS
30/**
31 * set_cpu_clk_info() - Initialize clock framework
32 * Always returns zero.
33 *
34 * This function is called from common code after relocation and sets up the
35 * clock framework. The framework must not be used before this function had been
36 * called.
37 */
38int set_cpu_clk_info(void)
39{
40 gd->cpu_clk = get_tbclk();
41
Michal Simekdaf315f2018-05-14 15:33:22 +020042 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
Michal Simek04b7e622015-01-15 10:01:51 +010043
44 gd->bd->bi_dsp_freq = 0;
45
46 return 0;
47}
48#endif