Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 1 | /* |
Timur Tabi | 32f709e | 2011-04-11 14:18:22 -0500 | [diff] [blame] | 2 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 3 | * |
Tom Rini | e237880 | 2016-01-14 22:05:13 -0500 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * MPC8610HPCD board configuration file |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /* High Level Configuration Options */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 15 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| 16 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 17 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 18 | |
York Sun | 59e7468 | 2007-10-31 14:59:04 -0500 | [diff] [blame] | 19 | /* video */ |
Timur Tabi | 32f709e | 2011-04-11 14:18:22 -0500 | [diff] [blame] | 20 | #define CONFIG_FSL_DIU_FB |
| 21 | |
Timur Tabi | 020edd2 | 2011-02-15 17:09:19 -0600 | [diff] [blame] | 22 | #ifdef CONFIG_FSL_DIU_FB |
| 23 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) |
Timur Tabi | e604463 | 2010-08-31 19:56:43 -0500 | [diff] [blame] | 24 | #define CONFIG_VIDEO_LOGO |
| 25 | #define CONFIG_VIDEO_BMP_LOGO |
York Sun | 59e7468 | 2007-10-31 14:59:04 -0500 | [diff] [blame] | 26 | #endif |
| 27 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 28 | #ifdef RUN_DIAG |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 29 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 30 | #endif |
| 31 | |
Becky Bruce | d1cb6cb | 2008-11-03 15:44:01 -0600 | [diff] [blame] | 32 | /* |
| 33 | * virtual address to be used for temporary mappings. There |
| 34 | * should be 128k free at this VA. |
| 35 | */ |
| 36 | #define CONFIG_SYS_SCRATCH_VA 0xc0000000 |
| 37 | |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 38 | #define CONFIG_PCI1 1 /* PCI controller 1 */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 39 | #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ |
| 40 | #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ |
| 41 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 42 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Kumar Gala | 6f2c1e9 | 2008-10-21 18:06:15 -0500 | [diff] [blame] | 43 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 44 | |
| 45 | #define CONFIG_ENV_OVERWRITE |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 46 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
| 47 | |
Peter Tyser | 86dee4a | 2010-10-07 22:32:48 -0500 | [diff] [blame] | 48 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 49 | #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 50 | #define CONFIG_ALTIVEC 1 |
| 51 | |
| 52 | /* |
| 53 | * L2CR setup -- make sure this is right for your board! |
| 54 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #define CONFIG_SYS_L2 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 56 | #define L2_INIT 0 |
York Sun | b714517 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 57 | #define L2_ENABLE (L2CR_L2E |0x00100000 ) |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 58 | |
| 59 | #ifndef CONFIG_SYS_CLK_FREQ |
| 60 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
| 61 | #endif |
| 62 | |
York Sun | b714517 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 63 | #define CONFIG_MISC_INIT_R 1 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 64 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 66 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Base addresses -- Note these are effective addresses where the |
| 70 | * actual resources get mapped (not physical addresses) |
| 71 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 73 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 74 | |
Jon Loeliger | ab6960f | 2008-11-20 14:02:56 -0600 | [diff] [blame] | 75 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| 76 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 |
Kumar Gala | a37b9ce | 2009-08-05 07:59:35 -0500 | [diff] [blame] | 77 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
Jon Loeliger | ab6960f | 2008-11-20 14:02:56 -0600 | [diff] [blame] | 78 | |
Jon Loeliger | 54634b4 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 79 | /* DDR Setup */ |
Jon Loeliger | 54634b4 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 80 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 81 | #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ |
| 82 | #define CONFIG_DDR_SPD |
| 83 | |
| 84 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 85 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 86 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 88 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Becky Bruce | d1cb6cb | 2008-11-03 15:44:01 -0600 | [diff] [blame] | 89 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 90 | #define CONFIG_VERY_BIG_RAM |
| 91 | |
Jon Loeliger | 54634b4 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 92 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 93 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 94 | |
Kumar Gala | c68e86c | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 95 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 96 | |
Jon Loeliger | 54634b4 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 97 | /* These are used when DDR doesn't use SPD. */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 98 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 99 | |
| 100 | #if 0 /* TODO */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 101 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F |
| 102 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ |
| 103 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 104 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 105 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 |
| 106 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
| 107 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 |
| 108 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 109 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 |
| 110 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 111 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 112 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 113 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| 114 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ |
| 115 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 |
| 118 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 119 | #define CONFIG_SYS_DDR_SBE 0x000f0000 |
Jon Loeliger | 54634b4 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 120 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 121 | #endif |
Jon Loeliger | 54634b4 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 122 | |
Jon Loeliger | 4eab623 | 2008-01-15 13:42:41 -0600 | [diff] [blame] | 123 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_I2C_EEPROM_NXID |
Jean-Christophe PLAGNIOL-VILLARD | 8349c72 | 2008-08-30 23:54:58 +0200 | [diff] [blame] | 125 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 127 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ |
| 130 | #define CONFIG_SYS_FLASH_BASE2 0xf8000000 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 131 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ |
| 135 | #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 136 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ |
| 138 | #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 139 | #if 0 /* TODO */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_BR2_PRELIM 0xf0000000 |
| 141 | #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 142 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 143 | #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ |
| 144 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 145 | |
Jason Jin | 33df3e2 | 2007-10-29 19:26:21 +0800 | [diff] [blame] | 146 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 147 | #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ |
| 148 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 149 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 150 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 151 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 152 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ |
| 153 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
York Sun | b714517 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 154 | #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 155 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 156 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 157 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 158 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
| 159 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 160 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 161 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 162 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Timur Tabi | 7ba8b32 | 2010-03-31 17:44:13 -0500 | [diff] [blame] | 163 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 164 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 166 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 167 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 169 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 170 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Becky Bruce | 2a97867 | 2008-11-05 14:55:35 -0600 | [diff] [blame] | 172 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 173 | |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 174 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_FLASH_CFI |
| 176 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 177 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 179 | #define CONFIG_SYS_RAMBOOT |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 180 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #undef CONFIG_SYS_RAMBOOT |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 182 | #endif |
| 183 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #if defined(CONFIG_SYS_RAMBOOT) |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 185 | #undef CONFIG_SPD_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_SDRAM_SIZE 256 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 187 | #endif |
| 188 | |
| 189 | #undef CONFIG_CLOCKS_IN_MHZ |
| 190 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 191 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 192 | #ifndef CONFIG_SYS_INIT_RAM_LOCK |
| 193 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 194 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 196 | #endif |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 198 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 201 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ |
| 203 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 204 | |
| 205 | /* Serial Port */ |
| 206 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 207 | #define CONFIG_SYS_NS16550_SERIAL |
| 208 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 209 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 212 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 213 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 215 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 216 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 217 | /* maximum size of the flat tree (8K) */ |
| 218 | #define OF_FLAT_TREE_MAX_SIZE 8192 |
| 219 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 220 | /* |
| 221 | * I2C |
| 222 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_I2C |
| 224 | #define CONFIG_SYS_I2C_FSL |
| 225 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 226 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 227 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 228 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 229 | |
| 230 | /* |
| 231 | * General PCI |
| 232 | * Addresses are mapped 1-1. |
| 233 | */ |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 234 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 235 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS |
| 236 | #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 238 | #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 239 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 240 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 241 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 242 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 243 | /* controller 1, Base address 0xa000 */ |
Kumar Gala | d0142ce | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 244 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 245 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
| 246 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 248 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
| 250 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 251 | |
| 252 | /* controller 2, Base Address 0x9000 */ |
Kumar Gala | d0142ce | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 253 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 254 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 |
| 255 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 257 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 258 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 |
| 259 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 260 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 261 | #if defined(CONFIG_PCI) |
| 262 | |
| 263 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 264 | |
Roy Zang | 4ef10e5 | 2008-01-15 16:38:38 +0800 | [diff] [blame] | 265 | #define CONFIG_ULI526X |
| 266 | #ifdef CONFIG_ULI526X |
Roy Zang | a648733 | 2007-09-13 18:52:28 +0800 | [diff] [blame] | 267 | #endif |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 268 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 269 | /************************************************************ |
| 270 | * USB support |
| 271 | ************************************************************/ |
York Sun | 59e7468 | 2007-10-31 14:59:04 -0500 | [diff] [blame] | 272 | #define CONFIG_PCI_OHCI 1 |
| 273 | #define CONFIG_USB_OHCI_NEW 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 274 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
| 275 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
| 276 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 277 | |
| 278 | #if !defined(CONFIG_PCI_PNP) |
| 279 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 280 | #define PCI_ENET0_MEMADDR 0xe0000000 |
| 281 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| 282 | #endif |
| 283 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 284 | #ifdef CONFIG_SCSI_AHCI |
Rob Herring | 83f6648 | 2013-08-24 10:10:54 -0500 | [diff] [blame] | 285 | #define CONFIG_LIBATA |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 286 | #define CONFIG_SATA_ULI5288 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 288 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 289 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 290 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 291 | #endif |
| 292 | |
| 293 | #endif /* CONFIG_PCI */ |
| 294 | |
| 295 | /* |
| 296 | * BAT0 2G Cacheable, non-guarded |
| 297 | * 0x0000_0000 2G DDR |
| 298 | */ |
Timur Tabi | 107e9cd | 2010-03-29 12:51:07 -0500 | [diff] [blame] | 299 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW) |
| 300 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW) |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 301 | |
| 302 | /* |
| 303 | * BAT1 1G Cache-inhibited, guarded |
| 304 | * 0x8000_0000 256M PCI-1 Memory |
| 305 | * 0xa000_0000 256M PCI-Express 1 Memory |
| 306 | * 0x9000_0000 256M PCI-Express 2 Memory |
| 307 | */ |
| 308 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 310 | | BATL_GUARDEDSTORAGE) |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 311 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 312 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 313 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 314 | |
| 315 | /* |
Jason Jin | 80dff48 | 2007-10-26 18:31:59 +0800 | [diff] [blame] | 316 | * BAT2 16M Cache-inhibited, guarded |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 317 | * 0xe100_0000 1M PCI-1 I/O |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 318 | */ |
| 319 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 320 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 321 | | BATL_GUARDEDSTORAGE) |
Becky Bruce | 47d20df | 2008-12-03 22:36:44 -0600 | [diff] [blame] | 322 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 323 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 324 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 325 | |
| 326 | /* |
Becky Bruce | 7e554a3 | 2008-11-02 18:19:32 -0600 | [diff] [blame] | 327 | * BAT3 4M Cache-inhibited, guarded |
| 328 | * 0xe000_0000 4M CCSR |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 329 | */ |
| 330 | |
Becky Bruce | 7e554a3 | 2008-11-02 18:19:32 -0600 | [diff] [blame] | 331 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 332 | | BATL_GUARDEDSTORAGE) |
Becky Bruce | 7e554a3 | 2008-11-02 18:19:32 -0600 | [diff] [blame] | 333 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) |
| 334 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 336 | |
Jon Loeliger | ab6960f | 2008-11-20 14:02:56 -0600 | [diff] [blame] | 337 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 338 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ |
| 339 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 340 | | BATL_GUARDEDSTORAGE) |
| 341 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ |
| 342 | | BATU_BL_1M | BATU_VS | BATU_VP) |
| 343 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ |
| 344 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 345 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU |
| 346 | #endif |
| 347 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 348 | /* |
Becky Bruce | 7e554a3 | 2008-11-02 18:19:32 -0600 | [diff] [blame] | 349 | * BAT4 32M Cache-inhibited, guarded |
| 350 | * 0xe200_0000 1M PCI-Express 2 I/O |
| 351 | * 0xe300_0000 1M PCI-Express 1 I/O |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 352 | */ |
Becky Bruce | 7e554a3 | 2008-11-02 18:19:32 -0600 | [diff] [blame] | 353 | |
| 354 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 355 | | BATL_GUARDEDSTORAGE) |
Becky Bruce | 7e554a3 | 2008-11-02 18:19:32 -0600 | [diff] [blame] | 356 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) |
| 357 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 358 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 359 | |
| 360 | /* |
| 361 | * BAT5 128K Cacheable, non-guarded |
| 362 | * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
| 363 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 364 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 365 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
| 366 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L |
| 367 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 368 | |
| 369 | /* |
| 370 | * BAT6 256M Cache-inhibited, guarded |
| 371 | * 0xf000_0000 256M FLASH |
| 372 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 373 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 374 | | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 375 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 376 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 377 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 378 | |
Becky Bruce | 2a97867 | 2008-11-05 14:55:35 -0600 | [diff] [blame] | 379 | /* Map the last 1M of flash where we're running from reset */ |
| 380 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 381 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 382 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
Becky Bruce | 2a97867 | 2008-11-05 14:55:35 -0600 | [diff] [blame] | 383 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 384 | | BATL_MEMCOHERENCE) |
| 385 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY |
| 386 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 387 | /* |
| 388 | * BAT7 4M Cache-inhibited, guarded |
| 389 | * 0xe800_0000 4M PIXIS |
| 390 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 391 | #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 392 | | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 393 | #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
| 394 | #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 395 | #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 396 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 397 | /* |
| 398 | * Environment |
| 399 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 400 | #ifndef CONFIG_SYS_RAMBOOT |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 401 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 402 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ |
| 403 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 404 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 405 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 406 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 407 | #endif |
| 408 | |
| 409 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 410 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 411 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 412 | /* |
| 413 | * BOOTP options |
| 414 | */ |
| 415 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 416 | #define CONFIG_BOOTP_BOOTPATH |
| 417 | #define CONFIG_BOOTP_GATEWAY |
| 418 | #define CONFIG_BOOTP_HOSTNAME |
| 419 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 420 | /* |
| 421 | * Command line configuration. |
| 422 | */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 423 | |
Jason Jin | 6c71b94 | 2008-05-13 11:50:36 +0800 | [diff] [blame] | 424 | #define CONFIG_WATCHDOG /* watchdog enabled */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 425 | #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 426 | |
| 427 | /* |
| 428 | * Miscellaneous configurable options |
| 429 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 430 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Timur Tabi | 35c4d18 | 2008-01-16 15:48:12 -0600 | [diff] [blame] | 431 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 432 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 433 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 434 | /* |
| 435 | * For booting Linux, the board info and command line data |
| 436 | * have to be in the first 8 MB of memory, since this is |
| 437 | * the maximum mapped by the Linux kernel during initialization. |
| 438 | */ |
Scott Wood | 0c431f7 | 2016-07-19 17:51:55 -0500 | [diff] [blame] | 439 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
| 440 | #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 441 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 442 | #if defined(CONFIG_CMD_KGDB) |
| 443 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 444 | #endif |
| 445 | |
| 446 | /* |
| 447 | * Environment Configuration |
| 448 | */ |
| 449 | #define CONFIG_IPADDR 192.168.1.100 |
| 450 | |
| 451 | #define CONFIG_HOSTNAME unknown |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 452 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 453 | #define CONFIG_BOOTFILE "uImage" |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 454 | #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin |
| 455 | |
| 456 | #define CONFIG_SERVERIP 192.168.1.1 |
| 457 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 458 | #define CONFIG_NETMASK 255.255.255.0 |
| 459 | |
| 460 | /* default location for tftp and bootm */ |
Scott Wood | 0c431f7 | 2016-07-19 17:51:55 -0500 | [diff] [blame] | 461 | #define CONFIG_LOADADDR 0x10000000 |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 462 | |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 463 | #if defined(CONFIG_PCI1) |
| 464 | #define PCI_ENV \ |
| 465 | "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ |
| 466 | "echo e;md ${a}e00 9\0" \ |
| 467 | "pci1regs=setenv a e0008; run pcireg\0" \ |
| 468 | "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ |
| 469 | "pci d.w $b.0 56 1\0" \ |
| 470 | "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ |
| 471 | "pci w.w $b.0 56 ffff\0" \ |
| 472 | "pci1err=setenv a e0008; run pcierr\0" \ |
| 473 | "pci1errc=setenv a e0008; run pcierrc\0" |
| 474 | #else |
| 475 | #define PCI_ENV "" |
| 476 | #endif |
| 477 | |
| 478 | #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) |
| 479 | #define PCIE_ENV \ |
| 480 | "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ |
| 481 | "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ |
| 482 | "pcie1regs=setenv a e000a; run pciereg\0" \ |
| 483 | "pcie2regs=setenv a e0009; run pciereg\0" \ |
| 484 | "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ |
| 485 | "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ |
| 486 | "pci d $b.0 130 1\0" \ |
| 487 | "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ |
| 488 | "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ |
| 489 | "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ |
| 490 | "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ |
| 491 | "pcie1err=setenv a e000a; run pcieerr\0" \ |
| 492 | "pcie2err=setenv a e0009; run pcieerr\0" \ |
| 493 | "pcie1errc=setenv a e000a; run pcieerrc\0" \ |
| 494 | "pcie2errc=setenv a e0009; run pcieerrc\0" |
| 495 | #else |
| 496 | #define PCIE_ENV "" |
| 497 | #endif |
| 498 | |
| 499 | #define DMA_ENV \ |
| 500 | "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ |
| 501 | "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ |
| 502 | "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ |
| 503 | "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ |
| 504 | "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ |
| 505 | "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ |
| 506 | "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ |
| 507 | "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" |
| 508 | |
York Sun | 98698c3 | 2007-10-29 13:57:53 -0500 | [diff] [blame] | 509 | #ifdef ENV_DEBUG |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 510 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 511 | "netdev=eth0\0" \ |
| 512 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 513 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 514 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 515 | " +$filesize; " \ |
| 516 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 517 | " +$filesize; " \ |
| 518 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 519 | " $filesize; " \ |
| 520 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 521 | " +$filesize; " \ |
| 522 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 523 | " $filesize\0" \ |
| 524 | "consoledev=ttyS0\0" \ |
Scott Wood | 0c431f7 | 2016-07-19 17:51:55 -0500 | [diff] [blame] | 525 | "ramdiskaddr=0x18000000\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 526 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ |
Scott Wood | 0c431f7 | 2016-07-19 17:51:55 -0500 | [diff] [blame] | 527 | "fdtaddr=0x17c00000\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 528 | "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ |
| 529 | "bdev=sda3\0" \ |
| 530 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ |
| 531 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ |
| 532 | "maxcpus=1" \ |
| 533 | "eoi=mw e00400b0 0\0" \ |
| 534 | "iack=md e00400a0 1\0" \ |
| 535 | "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 536 | "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ |
| 537 | "md ${a}f00 5\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 538 | "ddr1regs=setenv a e0002; run ddrreg\0" \ |
| 539 | "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 540 | "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ |
| 541 | "md ${a}e60 1; md ${a}ef0 1d\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 542 | "guregs=setenv a e00e0; run gureg\0" \ |
| 543 | "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ |
| 544 | "mcmregs=setenv a e0001; run mcmreg\0" \ |
| 545 | "diuregs=md e002c000 1d\0" \ |
| 546 | "dium=mw e002c01c\0" \ |
| 547 | "diuerr=md e002c014 1\0" \ |
| 548 | "pmregs=md e00e1000 2b\0" \ |
| 549 | "lawregs=md e0000c08 4b\0" \ |
| 550 | "lbcregs=md e0005000 36\0" \ |
| 551 | "dma0regs=md e0021100 12\0" \ |
| 552 | "dma1regs=md e0021180 12\0" \ |
| 553 | "dma2regs=md e0021200 12\0" \ |
| 554 | "dma3regs=md e0021280 12\0" \ |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 555 | PCI_ENV \ |
| 556 | PCIE_ENV \ |
| 557 | DMA_ENV |
York Sun | 98698c3 | 2007-10-29 13:57:53 -0500 | [diff] [blame] | 558 | #else |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 559 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 560 | "netdev=eth0\0" \ |
| 561 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 562 | "consoledev=ttyS0\0" \ |
Scott Wood | 0c431f7 | 2016-07-19 17:51:55 -0500 | [diff] [blame] | 563 | "ramdiskaddr=0x18000000\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 564 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ |
Scott Wood | 0c431f7 | 2016-07-19 17:51:55 -0500 | [diff] [blame] | 565 | "fdtaddr=0x17c00000\0" \ |
Marek Vasut | 0b3176c | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 566 | "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ |
| 567 | "bdev=sda3\0" |
York Sun | 98698c3 | 2007-10-29 13:57:53 -0500 | [diff] [blame] | 568 | #endif |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 569 | |
| 570 | #define CONFIG_NFSBOOTCOMMAND \ |
| 571 | "setenv bootargs root=/dev/nfs rw " \ |
| 572 | "nfsroot=$serverip:$rootpath " \ |
| 573 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 574 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 575 | "tftp $loadaddr $bootfile;" \ |
Jon Loeliger | 6bb38c4 | 2008-01-04 12:07:27 -0600 | [diff] [blame] | 576 | "tftp $fdtaddr $fdtfile;" \ |
| 577 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 578 | |
| 579 | #define CONFIG_RAMBOOTCOMMAND \ |
| 580 | "setenv bootargs root=/dev/ram rw " \ |
| 581 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 582 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 583 | "tftp $loadaddr $bootfile;" \ |
Jon Loeliger | 6bb38c4 | 2008-01-04 12:07:27 -0600 | [diff] [blame] | 584 | "tftp $fdtaddr $fdtfile;" \ |
| 585 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 586 | |
| 587 | #define CONFIG_BOOTCOMMAND \ |
| 588 | "setenv bootargs root=/dev/$bdev rw " \ |
| 589 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 590 | "tftp $loadaddr $bootfile;" \ |
Jon Loeliger | 6bb38c4 | 2008-01-04 12:07:27 -0600 | [diff] [blame] | 591 | "tftp $fdtaddr $fdtfile;" \ |
| 592 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | 3b971c9 | 2007-10-16 15:26:51 -0500 | [diff] [blame] | 593 | |
| 594 | #endif /* __CONFIG_H */ |