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git01.mediatek.com / filogic / uboot / edf6692efa52ed2288320770dfb6778fab750740 / . / arch / m68k / include / asm / immap.h
blob: 9e84fb9d260ce62dfad3e33166cd70a1ab2d34af [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]2/*
3 * ColdFire Internal Memory Map and Defines
4 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2004-2012 Freescale Semiconductor, Inc.
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]7 */
8
9#ifndef __IMMAP_H
10#define __IMMAP_H
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]11
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]12#if defined(CONFIG_MCF520x)
13#include <asm/immap_520x.h>
14#include <asm/m520x.h>
15
16#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
17#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
18
19/* Timer */
20#ifdef CONFIG_MCFTMR
21#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
22#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
23#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
24#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
25#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
26#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
27#define CONFIG_SYS_TMRINTR_PRI (6)
28#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
29#endif
30
TsiChung Liewb354aef2009-06-12 11:29:00 +0000[diff] [blame]31#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
32#define CONFIG_SYS_NUM_IRQS (128)
33#endif /* CONFIG_M520x */
34
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]35#ifdef CONFIG_M52277
36#include <asm/immap_5227x.h>
37#include <asm/m5227x.h>
38
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]39#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]40
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]41#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]42
43#ifdef CONFIG_LCD
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]44#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]45#endif
46
47/* Timer */
48#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]49#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
50#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
51#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
52#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
53#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
54#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
55#define CONFIG_SYS_TMRINTR_PRI (6)
56#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]57#endif
58
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]59#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
60#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew99b037a2008-01-14 17:43:33 -0600[diff] [blame]61#endif /* CONFIG_M52277 */
62
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]63#ifdef CONFIG_M5235
64#include <asm/immap_5235.h>
65#include <asm/m5235.h>
66
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]67#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
68#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]69
70/* Timer */
71#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]72#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
73#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
74#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
75#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
76#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
77#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
78#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
79#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]80#endif
81
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]82#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
83#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]84#endif /* CONFIG_M5235 */
85
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]86#ifdef CONFIG_M5249
87#include <asm/immap_5249.h>
88#include <asm/m5249.h>
89
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]90#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]91
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]92#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
93#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]94
95/* Timer */
96#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]97#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
98#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
99#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
100#define CONFIG_SYS_TMRINTR_NO (31)
101#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
102#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
103#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
104#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]105#endif
106#endif /* CONFIG_M5249 */
107
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]108#ifdef CONFIG_M5253
109#include <asm/immap_5253.h>
110#include <asm/m5249.h>
111#include <asm/m5253.h>
112
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]113#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]114
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]115#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
116#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]117
118/* Timer */
119#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]120#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
121#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
122#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
123#define CONFIG_SYS_TMRINTR_NO (27)
124#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
125#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
126#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
127#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
TsiChungLiew34674692007-08-16 13:20:50 -0500[diff] [blame]128#endif
129#endif /* CONFIG_M5253 */
130
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]131#ifdef CONFIG_M5271
132#include <asm/immap_5271.h>
133#include <asm/m5271.h>
134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]135#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
136#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]137
138/* Timer */
139#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]140#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
141#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
142#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
143#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
144#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
145#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
Richard Retanubun0dd94312009-03-26 15:26:01 -0400[diff] [blame]146#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]147#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]148#endif
149
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]150#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
151#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]152#endif /* CONFIG_M5271 */
153
154#ifdef CONFIG_M5272
155#include <asm/immap_5272.h>
156#include <asm/m5272.h>
157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]158#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
159#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]160
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]161#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
162#define CONFIG_SYS_NUM_IRQS (64)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]163
164/* Timer */
165#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]166#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
167#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
168#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
169#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
170#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
171#define CONFIG_SYS_TMRINTR_PEND (0)
172#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
173#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]174#endif
175#endif /* CONFIG_M5272 */
176
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]177#ifdef CONFIG_M5275
178#include <asm/immap_5275.h>
179#include <asm/m5275.h>
180
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]181#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
182#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
183#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]184
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]185#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
186#define CONFIG_SYS_NUM_IRQS (192)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]187
188/* Timer */
189#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]190#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
191#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
192#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
193#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
194#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
195#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
196#define CONFIG_SYS_TMRINTR_PRI (0x1E)
197#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
Matthew Fettke761e2e92008-02-04 15:38:20 -0600[diff] [blame]198#endif
199#endif /* CONFIG_M5275 */
200
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]201#ifdef CONFIG_M5282
202#include <asm/immap_5282.h>
203#include <asm/m5282.h>
204
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]205#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
206#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]208#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
209#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]210
211/* Timer */
212#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]213#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
214#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
215#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
216#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
217#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
218#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
219#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
220#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]221#endif
222#endif /* CONFIG_M5282 */
223
angelo@sysam.itbb4ba2c2015-02-12 01:40:00 +0100[diff] [blame]224#ifdef CONFIG_M5307
225#include <asm/immap_5307.h>
226#include <asm/m5307.h>
227
228#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
229 (CONFIG_SYS_UART_PORT * 0x40))
230#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
231#define CONFIG_SYS_NUM_IRQS (64)
232
233/* Timer */
234#ifdef CONFIG_MCFTMR
235#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
236#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
237#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \
238 (CONFIG_SYS_INTR_BASE))->ipr)
239#define CONFIG_SYS_TMRINTR_NO (31)
240#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
241#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
242#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
243 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
244#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
245#endif
246#endif /* CONFIG_M5307 */
247
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]248#if defined(CONFIG_MCF5301x)
249#include <asm/immap_5301x.h>
250#include <asm/m5301x.h>
251
252#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
253#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
254#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
255
256#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
257
258/* Timer */
259#ifdef CONFIG_MCFTMR
260#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
261#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
262#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
263#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
264#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
265#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
266#define CONFIG_SYS_TMRINTR_PRI (6)
267#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
268#endif
269
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000[diff] [blame]270#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
271#define CONFIG_SYS_NUM_IRQS (128)
272#endif /* CONFIG_M5301x */
273
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]274#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]275#include <asm/immap_5329.h>
276#include <asm/m5329.h>
277
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]278#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
279#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
280#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]281
282/* Timer */
283#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]284#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
285#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
286#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
287#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
288#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
289#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
290#define CONFIG_SYS_TMRINTR_PRI (6)
291#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]292#endif
293
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]294#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
295#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew6f8a0a32008-01-14 17:23:08 -0600[diff] [blame]296#endif /* CONFIG_M5329 && CONFIG_M5373 */
Stefan Roesef1110122007-07-16 13:11:12 +0200[diff] [blame]297
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]298#if defined(CONFIG_M54418)
299#include <asm/immap_5441x.h>
300#include <asm/m5441x.h>
301
302#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
303#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
304
305#if (CONFIG_SYS_UART_PORT < 4)
306#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
307 (CONFIG_SYS_UART_PORT * 0x4000))
308#else
309#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
310 ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
311#endif
312
313#define MMAP_DSPI MMAP_DSPI0
314#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
315
316/* Timer */
317#ifdef CONFIG_MCFTMR
318#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
319#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
320#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
321#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
322#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
323#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
324#define CONFIG_SYS_TMRINTR_PRI (6)
325#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
326#endif
327
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]328#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
Angelo Dureghelloe2f93932018-02-04 21:13:12 +0100[diff] [blame]329#define CONFIG_SYS_NUM_IRQS (192)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]330
331#endif /* CONFIG_M54418 */
332
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]333#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]334#include <asm/immap_5445x.h>
335#include <asm/m5445x.h>
336
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]337#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]338#if defined(CONFIG_M54455EVB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]339#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]340#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]341
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]342#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]343
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]344#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]345
346/* Timer */
347#ifdef CONFIG_MCFTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]348#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
349#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
350#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
351#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
352#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
353#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
354#define CONFIG_SYS_TMRINTR_PRI (6)
355#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]356#endif
357
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]358#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
359#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]360
361#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]362#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
363#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
364#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
365#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]366#endif
TsiChung Liew3cdc00a2008-08-11 13:41:49 +0000[diff] [blame]367#endif /* CONFIG_M54451 || CONFIG_M54455 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]368
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]369#ifdef CONFIG_M547x
370#include <asm/immap_547x_8x.h>
371#include <asm/m547x_8x.h>
372
373#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]374#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
375#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]376
377#define FEC0_RX_TASK 0
378#define FEC0_TX_TASK 1
379#define FEC0_RX_PRIORITY 6
380#define FEC0_TX_PRIORITY 7
381#define FEC0_RX_INIT 16
382#define FEC0_TX_INIT 17
383#define FEC1_RX_TASK 2
384#define FEC1_TX_TASK 3
385#define FEC1_RX_PRIORITY 6
386#define FEC1_TX_PRIORITY 7
387#define FEC1_RX_INIT 30
388#define FEC1_TX_INIT 31
389#endif
390
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]391#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]392
393#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]394#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
395#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
396#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
397#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
398#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
399#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
400#define CONFIG_SYS_TMRINTR_PRI (0x1E)
401#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]402#endif
403
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]404#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
405#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]406
407#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]408#define CONFIG_SYS_PCI_BAR0 (0x40000000)
409#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
410#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
411#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]412#endif
413#endif /* CONFIG_M547x */
414
415#ifdef CONFIG_M548x
416#include <asm/immap_547x_8x.h>
417#include <asm/m547x_8x.h>
418
419#ifdef CONFIG_FSLDMAFEC
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]420#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
421#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]422
423#define FEC0_RX_TASK 0
424#define FEC0_TX_TASK 1
425#define FEC0_RX_PRIORITY 6
426#define FEC0_TX_PRIORITY 7
427#define FEC0_RX_INIT 16
428#define FEC0_TX_INIT 17
429#define FEC1_RX_TASK 2
430#define FEC1_TX_TASK 3
431#define FEC1_RX_PRIORITY 6
432#define FEC1_TX_PRIORITY 7
433#define FEC1_RX_INIT 30
434#define FEC1_TX_INIT 31
435#endif
436
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]437#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]438
439/* Timer */
440#ifdef CONFIG_SLTTMR
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]441#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
442#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
443#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
444#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
445#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
446#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
447#define CONFIG_SYS_TMRINTR_PRI (0x1E)
448#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]449#endif
450
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]451#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
452#define CONFIG_SYS_NUM_IRQS (128)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]453
454#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]455#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
456#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
457#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
458#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
TsiChungLiew471b2c62008-01-15 13:39:44 -0600[diff] [blame]459#endif
460#endif /* CONFIG_M548x */
461
TsiChungLiew2e0aeef2007-07-05 22:39:07 -0500[diff] [blame]462#endif /* __IMMAP_H */