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wdenk7e920de2004-06-09 12:47:02 +00001/*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
Wolfgang Denka1be4762008-05-20 16:00:29 +020036#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
wdenk7e920de2004-06-09 12:47:02 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
40#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
41#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
42
43/*
44 * OS Bootstrap configuration
45 *
46 */
47
48#if 0
49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50#else
51#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
52#endif
53
54#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
55
56#if 1
57#undef CONFIG_BOOTARGS
58#define CONFIG_BOOTCOMMAND \
59 "setenv bootargs console=ttyS0,38400 debug " \
60 "root=/dev/ram rw ramdisk_size=4096 " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010061 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk7e920de2004-06-09 12:47:02 +000062 "bootm ff800000 ff900000"
63#endif
64
65#if 0
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
68 "bootp; " \
69 "setenv bootargs console=ttyS0,38400 debug " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010070 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk7e920de2004-06-09 12:47:02 +000072 "bootm"
73#endif
74
75/*
Jon Loeligerdcf14512007-07-09 21:48:26 -050076 * BOOTP options
wdenk7e920de2004-06-09 12:47:02 +000077 */
Jon Loeligerdcf14512007-07-09 21:48:26 -050078#define CONFIG_BOOTP_SUBNETMASK
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_BOOTFILESIZE
83#define CONFIG_BOOTP_DNS2
84
Jon Loeliger37ec35e2007-07-04 22:31:56 -050085
wdenk7e920de2004-06-09 12:47:02 +000086/*
Jon Loeliger37ec35e2007-07-04 22:31:56 -050087 * Command line configuration.
wdenk7e920de2004-06-09 12:47:02 +000088 */
Jon Loeliger37ec35e2007-07-04 22:31:56 -050089#include <config_cmd_default.h>
wdenk7e920de2004-06-09 12:47:02 +000090
Jon Loeliger37ec35e2007-07-04 22:31:56 -050091#define CONFIG_CMD_ASKENV
92#define CONFIG_CMD_BEDBUG
93#define CONFIG_CMD_ELF
94#define CONFIG_CMD_IRQ
95#define CONFIG_CMD_I2C
96#define CONFIG_CMD_PCI
97#define CONFIG_CMD_DATE
98#define CONFIG_CMD_MII
99#define CONFIG_CMD_PING
100#define CONFIG_CMD_DHCP
101
wdenk7e920de2004-06-09 12:47:02 +0000102/*
103 * Serial download configuration
104 *
105 */
106#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7e920de2004-06-09 12:47:02 +0000108
109/*
110 * KGDB Configuration
111 *
112 */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500113#if defined(CONFIG_CMD_KGDB)
wdenk7e920de2004-06-09 12:47:02 +0000114#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
115#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
116#endif
117
118/*
119 * Miscellaneous configurable options
120 *
121 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
123#ifdef CONFIG_SYS_HUSH_PARSER
124#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
wdenk7e920de2004-06-09 12:47:02 +0000125#endif
126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_LONGHELP /* undef to save memory */
128#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37ec35e2007-07-04 22:31:56 -0500129#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7e920de2004-06-09 12:47:02 +0000131#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7e920de2004-06-09 12:47:02 +0000133#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7e920de2004-06-09 12:47:02 +0000137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk7e920de2004-06-09 12:47:02 +0000140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
143#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk7e920de2004-06-09 12:47:02 +0000144
145/*
146 * For booting Linux, the board info and command line data
147 * have to be in the first 8 MB of memory, since this is
148 * the maximum mapped by the Linux kernel during initialization.
149 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7e920de2004-06-09 12:47:02 +0000151
152/*
153 * watchdog configuration
154 *
155 */
156#undef CONFIG_WATCHDOG /* watchdog disabled */
157
158/*
159 * UART configuration
160 *
161 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_BASE_BAUD 691200
wdenk7e920de2004-06-09 12:47:02 +0000164#define CONFIG_BAUDRATE 38400 /* Default baud rate */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7e920de2004-06-09 12:47:02 +0000166 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
167
168/*
169 * I2C configuration
170 *
171 */
172#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
174#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
wdenk7e920de2004-06-09 12:47:02 +0000175
176/*
177 * MII PHY configuration
178 *
179 */
Ben Warren3a918a62008-10-27 23:50:15 -0700180#define CONFIG_PPC4xx_EMAC
wdenk7e920de2004-06-09 12:47:02 +0000181#define CONFIG_MII 1 /* MII PHY management */
182#define CONFIG_PHY_ADDR 0 /* PHY address */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200183#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
wdenk7e920de2004-06-09 12:47:02 +0000184 /* 32usec min. for LXT971A */
185#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
Ben Warren6c262932009-04-28 16:50:53 -0700186#define CONFIG_NET_MULTI
wdenk7e920de2004-06-09 12:47:02 +0000187
188/*
189 * RTC configuration
190 *
191 * Note that DS1307 RTC is limited to 100Khz I2C bus.
192 *
193 */
194#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
195
196/*
197 * PCI stuff
198 *
199 */
200#define CONFIG_PCI /* include pci support */
201#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
202#define PCI_HOST_FORCE 1 /* configure as pci host */
203#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
204
205#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
206#define CONFIG_PCI_PNP /* do pci plug-and-play */
207 /* resource configuration */
208#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
209#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
210
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
212#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
213#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
214#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
215#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
216#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
217#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
218#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk7e920de2004-06-09 12:47:02 +0000219
220/*
221 * IDE stuff
222 *
223 */
224#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
225#undef CONFIG_IDE_LED /* no led for ide supported */
226#undef CONFIG_IDE_RESET /* no reset for ide supported */
227
228/*
229 * Environment configuration
230 *
231 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200232#define CONFIG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200233#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200234#undef CONFIG_ENV_IS_IN_EEPROM
wdenk7e920de2004-06-09 12:47:02 +0000235
236/*
237 * General Memory organization
238 *
239 * Start addresses for the final memory configuration
240 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7e920de2004-06-09 12:47:02 +0000242 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_SDRAM_BASE 0x00000000
244#define CONFIG_SYS_FLASH_BASE 0xFF800000
245#define CONFIG_SYS_FLASH_SIZE 0x00800000
246#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
247#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
248#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
wdenk7e920de2004-06-09 12:47:02 +0000249
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
251#define CONFIG_SYS_RAMSTART
wdenk7e920de2004-06-09 12:47:02 +0000252#endif
253
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200254#if defined(CONFIG_ENV_IS_IN_FLASH)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200255#define CONFIG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
256#define CONFIG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
257#define CONFIG_ENV_SIZE 0x00001000 /* Size of Environment */
258#define CONFIG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
wdenk7e920de2004-06-09 12:47:02 +0000259#endif
260
261/*
262 * FLASH Device configuration
263 *
264 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200266#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
268#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
269#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
270#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max # of sectors on one chip */
271#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
272#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
wdenk7e920de2004-06-09 12:47:02 +0000273
274/*
275 * On Chip Memory location/size
276 *
277 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200278#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
279#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenk7e920de2004-06-09 12:47:02 +0000280
281/*
282 * Global info and initial stack
283 *
284 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
286#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
287#define CONFIG_SYS_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
288#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
289#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7e920de2004-06-09 12:47:02 +0000290
291/*
wdenk7e920de2004-06-09 12:47:02 +0000292 * Miscellaneous board specific definitions
293 *
294 */
295#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
296
297/*
298 * Internal Definitions
299 *
300 * Boot Flags
301 *
302 */
303#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
304#define BOOTFLAG_WARM 0x02 /* Software reboot */
305
306#endif /* __CONFIG_H */