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Marek Vasutc140e982011-11-08 23:18:08 +00001/*
2 * Freescale i.MX28 common code
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <asm/errno.h>
31#include <asm/io.h>
32#include <asm/arch/clock.h>
33#include <asm/arch/gpio.h>
Marek Vasut53fdab22011-11-08 23:18:13 +000034#include <asm/arch/iomux.h>
Marek Vasutc140e982011-11-08 23:18:08 +000035#include <asm/arch/imx-regs.h>
36#include <asm/arch/sys_proto.h>
37
Marek Vasut5bf48fb2011-11-08 23:18:23 +000038DECLARE_GLOBAL_DATA_PTR;
39
Marek Vasutc140e982011-11-08 23:18:08 +000040/* 1 second delay should be plenty of time for block reset. */
41#define RESET_MAX_TIMEOUT 1000000
42
43#define MX28_BLOCK_SFTRST (1 << 31)
44#define MX28_BLOCK_CLKGATE (1 << 30)
45
46/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
47inline void lowlevel_init(void) {}
48
49void reset_cpu(ulong ignored) __attribute__((noreturn));
50
51void reset_cpu(ulong ignored)
52{
53
54 struct mx28_rtc_regs *rtc_regs =
55 (struct mx28_rtc_regs *)MXS_RTC_BASE;
56
57 /* Wait 1 uS before doing the actual watchdog reset */
58 writel(1, &rtc_regs->hw_rtc_watchdog);
59 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
60
61 /* Endless loop, reset will exit from here */
62 for (;;)
63 ;
64}
65
66int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
67{
68 while (--timeout) {
69 if ((readl(&reg->reg) & mask) == mask)
70 break;
71 udelay(1);
72 }
73
74 return !timeout;
75}
76
77int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
78{
79 while (--timeout) {
80 if ((readl(&reg->reg) & mask) == 0)
81 break;
82 udelay(1);
83 }
84
85 return !timeout;
86}
87
88int mx28_reset_block(struct mx28_register *reg)
89{
90 /* Clear SFTRST */
91 writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
92
93 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
94 return 1;
95
96 /* Clear CLKGATE */
97 writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
98
99 /* Set SFTRST */
100 writel(MX28_BLOCK_SFTRST, &reg->reg_set);
101
102 /* Wait for CLKGATE being set */
103 if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
104 return 1;
105
106 /* Clear SFTRST */
107 writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
108
109 if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
110 return 1;
111
112 /* Clear CLKGATE */
113 writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
114
115 if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
116 return 1;
117
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000118 return 0;
119}
120
121void mx28_fixup_vt(uint32_t start_addr)
122{
123 uint32_t *vt = (uint32_t *)0x20;
124 int i;
125
126 for (i = 0; i < 8; i++)
127 vt[i] = start_addr + (4 * i);
128}
129
130#ifdef CONFIG_ARCH_MISC_INIT
131int arch_misc_init(void)
132{
133 mx28_fixup_vt(gd->relocaddr);
Marek Vasutc140e982011-11-08 23:18:08 +0000134 return 0;
135}
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000136#endif
Marek Vasutc140e982011-11-08 23:18:08 +0000137
138#ifdef CONFIG_ARCH_CPU_INIT
139int arch_cpu_init(void)
140{
141 struct mx28_clkctrl_regs *clkctrl_regs =
142 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
Marek Vasut5bf48fb2011-11-08 23:18:23 +0000143 extern uint32_t _start;
144
145 mx28_fixup_vt((uint32_t)&_start);
Marek Vasutc140e982011-11-08 23:18:08 +0000146
147 /*
148 * Enable NAND clock
149 */
150 /* Clear bypass bit */
151 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
152 &clkctrl_regs->hw_clkctrl_clkseq_set);
153
154 /* Set GPMI clock to ref_gpmi / 12 */
155 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
156 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
157
158 udelay(1000);
159
Marek Vasut53fdab22011-11-08 23:18:13 +0000160 /*
161 * Configure GPIO unit
162 */
163 mxs_gpio_init();
164
Marek Vasutc140e982011-11-08 23:18:08 +0000165 return 0;
166}
167#endif
168
169#if defined(CONFIG_DISPLAY_CPUINFO)
170int print_cpuinfo(void)
171{
Fabio Estevamedba4bd2012-01-22 16:38:08 +0000172 printf("Freescale i.MX28 family at %d MHz\n",
173 mxc_get_clock(MXC_ARM_CLK) / 1000000);
Marek Vasutc140e982011-11-08 23:18:08 +0000174 return 0;
175}
176#endif
177
178int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
179{
180 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
181 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
182 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
183 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
184 return 0;
185}
186
187/*
188 * Initializes on-chip ethernet controllers.
189 */
190#ifdef CONFIG_CMD_NET
191int cpu_eth_init(bd_t *bis)
192{
193 struct mx28_clkctrl_regs *clkctrl_regs =
194 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
195
196 /* Turn on ENET clocks */
197 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
198 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
199
200 /* Set up ENET PLL for 50 MHz */
201 /* Power on ENET PLL */
202 writel(CLKCTRL_PLL2CTRL0_POWER,
203 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
204
205 udelay(10);
206
207 /* Gate on ENET PLL */
208 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
209 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
210
211 /* Enable pad output */
212 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
213
214 return 0;
215}
216#endif
217
Fabio Estevam4029c012011-12-20 06:42:29 +0000218static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
219{
220 mac[0] = 0x00;
221 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
222
223 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
224 mac[5] += 1;
225}
226
227void mx28_adjust_mac(int dev_id, unsigned char *mac)
228 __attribute__((weak, alias("__mx28_adjust_mac")));
229
230#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
231
232#define MXS_OCOTP_MAX_TIMEOUT 1000000
233void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
234{
235 struct mx28_ocotp_regs *ocotp_regs =
236 (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
237 uint32_t data;
238
239 memset(mac, 0, 6);
240
241 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
242
243 if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
244 MXS_OCOTP_MAX_TIMEOUT)) {
245 printf("MXS FEC: Can't get MAC from OCOTP\n");
246 return;
247 }
248
249 data = readl(&ocotp_regs->hw_ocotp_cust0);
250
251 mac[2] = (data >> 24) & 0xff;
252 mac[3] = (data >> 16) & 0xff;
253 mac[4] = (data >> 8) & 0xff;
254 mac[5] = data & 0xff;
255 mx28_adjust_mac(dev_id, mac);
256}
257#else
258void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
259{
260 memset(mac, 0, 6);
261}
262#endif
263
Fabio Estevam93f3a892011-12-20 05:46:33 +0000264#define HW_DIGCTRL_SCRATCH0 0x8001c280
265#define HW_DIGCTRL_SCRATCH1 0x8001c290
266int mx28_dram_init(void)
267{
268 uint32_t sz[2];
269
270 sz[0] = readl(HW_DIGCTRL_SCRATCH0);
271 sz[1] = readl(HW_DIGCTRL_SCRATCH1);
272
273 if (sz[0] != sz[1]) {
274 printf("MX28:\n"
275 "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
276 "HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
277 "verify these two registers contain valid RAM size!\n");
278 hang();
279 }
280
281 gd->ram_size = sz[0];
282 return 0;
283}
284
Marek Vasutc140e982011-11-08 23:18:08 +0000285U_BOOT_CMD(
286 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
287 "display clocks",
288 ""
289);