blob: 89624227c29383346eb366ec5802cb6fd6c05977 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warrenfccc9c52016-08-08 11:28:25 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warrenfccc9c52016-08-08 11:28:25 -06004 */
5
Stephen Warrenfccc9c52016-08-08 11:28:25 -06006#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06007#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -07008#include <malloc.h>
Stephen Warrenfccc9c52016-08-08 11:28:25 -06009#include <misc.h>
10#include <reset-uclass.h>
11#include <asm/arch-tegra/bpmp_abi.h>
12
Stephen Warrenfccc9c52016-08-08 11:28:25 -060013static int tegra186_reset_common(struct reset_ctl *reset_ctl,
14 enum mrq_reset_commands cmd)
15{
16 struct mrq_reset_request req;
17 int ret;
18
19 req.cmd = cmd;
20 req.reset_id = reset_ctl->id;
21
22 ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
23 NULL, 0);
24 if (ret < 0)
25 return ret;
26
27 return 0;
28}
29
30static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
31{
32 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
33 reset_ctl->dev, reset_ctl->id);
34
35 return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
36}
37
38static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
39{
40 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
41 reset_ctl->dev, reset_ctl->id);
42
43 return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
44}
45
46struct reset_ops tegra186_reset_ops = {
Stephen Warrenfccc9c52016-08-08 11:28:25 -060047 .rst_assert = tegra186_reset_assert,
48 .rst_deassert = tegra186_reset_deassert,
49};
50
Stephen Warrenfccc9c52016-08-08 11:28:25 -060051U_BOOT_DRIVER(tegra186_reset) = {
52 .name = "tegra186_reset",
53 .id = UCLASS_RESET,
Stephen Warrenfccc9c52016-08-08 11:28:25 -060054 .ops = &tegra186_reset_ops,
55};