Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 1 | /* |
Hatim RV | 793ed48 | 2012-12-11 00:52:48 +0000 | [diff] [blame] | 2 | * Copyright (C) 2012 Samsung Electronics |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 3 | * |
Hatim RV | 793ed48 | 2012-12-11 00:52:48 +0000 | [diff] [blame] | 4 | * Configuration settings for the SAMSUNG EXYNOS5250 board. |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef __CONFIG_H |
| 26 | #define __CONFIG_H |
| 27 | |
| 28 | /* High Level Configuration Options */ |
| 29 | #define CONFIG_SAMSUNG /* in a SAMSUNG core */ |
| 30 | #define CONFIG_S5P /* S5P Family */ |
| 31 | #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ |
| 32 | #define CONFIG_SMDK5250 /* which is in a SMDK5250 */ |
| 33 | |
| 34 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
| 35 | |
Simon Glass | cdf4e97 | 2013-03-05 14:39:58 +0000 | [diff] [blame] | 36 | #define CONFIG_SYS_GENERIC_BOARD |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 37 | #define CONFIG_ARCH_CPU_INIT |
| 38 | #define CONFIG_DISPLAY_CPUINFO |
| 39 | #define CONFIG_DISPLAY_BOARDINFO |
| 40 | |
Hatim RV | 793ed48 | 2012-12-11 00:52:48 +0000 | [diff] [blame] | 41 | /* Enable fdt support for Exynos5250 */ |
| 42 | #define CONFIG_ARCH_DEVICE_TREE exynos5250 |
| 43 | #define CONFIG_OF_CONTROL |
| 44 | #define CONFIG_OF_SEPARATE |
| 45 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 46 | /* Keep L2 Cache Disabled */ |
| 47 | #define CONFIG_SYS_DCACHE_OFF |
| 48 | |
Akshay Saraswat | 150a9db | 2013-03-20 21:00:57 +0000 | [diff] [blame] | 49 | /* Enable ACE acceleration for SHA1 and SHA256 */ |
| 50 | #define CONFIG_EXYNOS_ACE_SHA |
Akshay Saraswat | b20d7d6 | 2013-03-20 21:00:59 +0000 | [diff] [blame] | 51 | #define CONFIG_SHA_HW_ACCEL |
Akshay Saraswat | 150a9db | 2013-03-20 21:00:57 +0000 | [diff] [blame] | 52 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 53 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 54 | #define CONFIG_SYS_TEXT_BASE 0x43E00000 |
| 55 | |
| 56 | /* input clock of PLL: SMDK5250 has 24MHz input clock */ |
| 57 | #define CONFIG_SYS_CLK_FREQ 24000000 |
| 58 | |
| 59 | #define CONFIG_SETUP_MEMORY_TAGS |
| 60 | #define CONFIG_CMDLINE_TAG |
| 61 | #define CONFIG_INITRD_TAG |
| 62 | #define CONFIG_CMDLINE_EDITING |
| 63 | |
| 64 | /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */ |
| 65 | #define MACH_TYPE_SMDK5250 3774 |
| 66 | #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 |
| 67 | |
| 68 | /* Power Down Modes */ |
| 69 | #define S5P_CHECK_SLEEP 0x00000BAD |
| 70 | #define S5P_CHECK_DIDLE 0xBAD00000 |
| 71 | #define S5P_CHECK_LPA 0xABAD0000 |
| 72 | |
| 73 | /* Offset for inform registers */ |
| 74 | #define INFORM0_OFFSET 0x800 |
| 75 | #define INFORM1_OFFSET 0x804 |
| 76 | |
| 77 | /* Size of malloc() pool */ |
Rajeshwari Shinde | 418eb7e | 2012-12-10 01:55:48 +0000 | [diff] [blame] | 78 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 79 | |
| 80 | /* select serial console configuration */ |
Rajeshwari Shinde | e8bfeda | 2012-07-03 20:03:00 +0000 | [diff] [blame] | 81 | #define CONFIG_SERIAL3 /* use SERIAL 3 */ |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 82 | #define CONFIG_BAUDRATE 115200 |
| 83 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 |
| 84 | |
Ajay Kumar | f6a62fe | 2013-01-10 21:06:11 +0000 | [diff] [blame] | 85 | /* Console configuration */ |
| 86 | #define CONFIG_CONSOLE_MUX |
| 87 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 88 | #define EXYNOS_DEVICE_SETTINGS \ |
| 89 | "stdin=serial\0" \ |
| 90 | "stdout=serial,lcd\0" \ |
| 91 | "stderr=serial,lcd\0" |
| 92 | |
| 93 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 94 | EXYNOS_DEVICE_SETTINGS |
| 95 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 96 | #define TZPC_BASE_OFFSET 0x10000 |
| 97 | |
| 98 | /* SD/MMC configuration */ |
| 99 | #define CONFIG_GENERIC_MMC |
| 100 | #define CONFIG_MMC |
Jaehoon Chung | a38690e | 2012-04-23 02:36:29 +0000 | [diff] [blame] | 101 | #define CONFIG_SDHCI |
| 102 | #define CONFIG_S5P_SDHCI |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 103 | |
| 104 | #define CONFIG_BOARD_EARLY_INIT_F |
| 105 | |
| 106 | /* PWM */ |
| 107 | #define CONFIG_PWM |
| 108 | |
| 109 | /* allow to overwrite serial and ethaddr */ |
| 110 | #define CONFIG_ENV_OVERWRITE |
| 111 | |
| 112 | /* Command definition*/ |
| 113 | #include <config_cmd_default.h> |
| 114 | |
| 115 | #define CONFIG_CMD_PING |
| 116 | #define CONFIG_CMD_ELF |
| 117 | #define CONFIG_CMD_MMC |
| 118 | #define CONFIG_CMD_EXT2 |
| 119 | #define CONFIG_CMD_FAT |
Chander Kashyap | 5ff8061e | 2012-02-09 01:26:19 +0000 | [diff] [blame] | 120 | #define CONFIG_CMD_NET |
Akshay Saraswat | b20d7d6 | 2013-03-20 21:00:59 +0000 | [diff] [blame] | 121 | #define CONFIG_CMD_HASH |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 122 | |
| 123 | #define CONFIG_BOOTDELAY 3 |
| 124 | #define CONFIG_ZERO_BOOTDELAY_CHECK |
| 125 | |
Akshay Saraswat | c9ba97e | 2013-02-25 01:13:03 +0000 | [diff] [blame] | 126 | /* Thermal Management Unit */ |
| 127 | #define CONFIG_EXYNOS_TMU |
Akshay Saraswat | 60e72fa | 2013-02-25 01:13:05 +0000 | [diff] [blame] | 128 | #define CONFIG_CMD_DTT |
| 129 | #define CONFIG_TMU_CMD_DTT |
Akshay Saraswat | c9ba97e | 2013-02-25 01:13:03 +0000 | [diff] [blame] | 130 | |
Rajeshwari Shinde | 8755bb9 | 2012-05-14 05:52:05 +0000 | [diff] [blame] | 131 | /* USB */ |
| 132 | #define CONFIG_CMD_USB |
| 133 | #define CONFIG_USB_EHCI |
| 134 | #define CONFIG_USB_EHCI_EXYNOS |
| 135 | #define CONFIG_USB_STORAGE |
| 136 | |
Vivek Gautam | 681dd83 | 2013-01-28 00:39:59 +0000 | [diff] [blame] | 137 | /* USB boot mode */ |
| 138 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 |
| 139 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 |
| 140 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 |
| 141 | |
Simon Glass | 2df1f7a | 2013-04-12 10:44:58 +0000 | [diff] [blame] | 142 | /* TPM */ |
| 143 | #define CONFIG_TPM |
| 144 | #define CONFIG_CMD_TPM |
| 145 | #define CONFIG_INFINEON_TPM_I2C |
| 146 | #define CONFIG_INFINEON_TPM_I2C_BUS 3 |
| 147 | #define CONFIG_INFINEON_TPM_I2C_ADDR 0x20 |
| 148 | |
Chander Kashyap | 1633dd1 | 2012-02-05 23:01:48 +0000 | [diff] [blame] | 149 | /* MMC SPL */ |
| 150 | #define CONFIG_SPL |
| 151 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
| 152 | |
Rajeshwari Shinde | e44ebd0 | 2012-07-03 20:02:53 +0000 | [diff] [blame] | 153 | /* specific .lds file */ |
| 154 | #define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds" |
| 155 | #define CONFIG_SPL_TEXT_BASE 0x02023400 |
Albert ARIBAUD | 19a053d | 2013-04-12 05:14:33 +0000 | [diff] [blame] | 156 | #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) |
Rajeshwari Shinde | e44ebd0 | 2012-07-03 20:02:53 +0000 | [diff] [blame] | 157 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 158 | #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" |
| 159 | |
| 160 | /* Miscellaneous configurable options */ |
| 161 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 162 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 163 | #define CONFIG_SYS_PROMPT "SMDK5250 # " |
| 164 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 165 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ |
| 166 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 167 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" |
| 168 | /* Boot Argument Buffer Size */ |
| 169 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 170 | /* memtest works on */ |
| 171 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 172 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) |
| 173 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) |
| 174 | |
| 175 | #define CONFIG_SYS_HZ 1000 |
| 176 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 177 | #define CONFIG_RD_LVL |
| 178 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 179 | #define CONFIG_NR_DRAM_BANKS 8 |
| 180 | #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ |
| 181 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
| 182 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE |
| 183 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) |
| 184 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE |
| 185 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) |
| 186 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE |
| 187 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) |
| 188 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE |
| 189 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) |
| 190 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE |
| 191 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) |
| 192 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE |
| 193 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) |
| 194 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE |
| 195 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) |
| 196 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE |
| 197 | |
| 198 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 |
| 199 | |
| 200 | /* FLASH and environment organization */ |
| 201 | #define CONFIG_SYS_NO_FLASH |
| 202 | #undef CONFIG_CMD_IMLS |
| 203 | #define CONFIG_IDENT_STRING " for SMDK5250" |
| 204 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 205 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 206 | |
| 207 | #define CONFIG_SECURE_BL1_ONLY |
| 208 | |
| 209 | /* Secure FW size configuration */ |
| 210 | #ifdef CONFIG_SECURE_BL1_ONLY |
| 211 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ |
| 212 | #else |
| 213 | #define CONFIG_SEC_FW_SIZE 0 |
| 214 | #endif |
| 215 | |
| 216 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ |
| 217 | #define CONFIG_RES_BLOCK_SIZE (512) |
| 218 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ |
| 219 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ |
| 220 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ |
| 221 | |
| 222 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) |
| 223 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) |
| 224 | #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) |
| 225 | |
Chander Kashyap | 1633dd1 | 2012-02-05 23:01:48 +0000 | [diff] [blame] | 226 | /* U-boot copy size from boot Media to DRAM.*/ |
| 227 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) |
| 228 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) |
Rajeshwari Shinde | 9cb48e8 | 2012-11-02 01:15:38 +0000 | [diff] [blame] | 229 | |
| 230 | #define OM_STAT (0x1f << 1) |
| 231 | #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 |
| 232 | #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) |
| 233 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 234 | #define CONFIG_DOS_PARTITION |
| 235 | |
| 236 | #define CONFIG_IRAM_STACK 0x02050000 |
| 237 | |
| 238 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) |
| 239 | |
Rajeshwari Shinde | 1d518e6 | 2012-07-23 21:23:55 +0000 | [diff] [blame] | 240 | /* I2C */ |
| 241 | #define CONFIG_SYS_I2C_INIT_BOARD |
| 242 | #define CONFIG_HARD_I2C |
| 243 | #define CONFIG_CMD_I2C |
| 244 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */ |
| 245 | #define CONFIG_DRIVER_S3C24X0_I2C |
| 246 | #define CONFIG_I2C_MULTI_BUS |
| 247 | #define CONFIG_MAX_I2C_NUM 8 |
| 248 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
Simon Glass | 9f68f8e | 2012-12-05 14:46:45 +0000 | [diff] [blame] | 249 | #define CONFIG_I2C_EDID |
Rajeshwari Shinde | 1d518e6 | 2012-07-23 21:23:55 +0000 | [diff] [blame] | 250 | |
Rajeshwari Shinde | 346fe62 | 2012-08-24 00:39:24 +0000 | [diff] [blame] | 251 | /* PMIC */ |
| 252 | #define CONFIG_PMIC |
| 253 | #define CONFIG_PMIC_I2C |
| 254 | #define CONFIG_PMIC_MAX77686 |
| 255 | |
Hatim RV | 000b548 | 2012-11-02 01:15:37 +0000 | [diff] [blame] | 256 | /* SPI */ |
| 257 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 258 | #define CONFIG_SPI_FLASH |
| 259 | |
| 260 | #ifdef CONFIG_SPI_FLASH |
| 261 | #define CONFIG_EXYNOS_SPI |
| 262 | #define CONFIG_CMD_SF |
| 263 | #define CONFIG_CMD_SPI |
| 264 | #define CONFIG_SPI_FLASH_WINBOND |
| 265 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
| 266 | #define CONFIG_SF_DEFAULT_SPEED 50000000 |
| 267 | #define EXYNOS5_SPI_NUM_CONTROLLERS 5 |
| 268 | #endif |
| 269 | |
| 270 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH |
| 271 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 |
| 272 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE |
| 273 | #define CONFIG_ENV_SPI_BUS 1 |
| 274 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 |
| 275 | #endif |
| 276 | |
Albert ARIBAUD | 8f9e08b | 2012-12-22 11:59:14 +0100 | [diff] [blame] | 277 | /* PMIC */ |
Rajeshwari Shinde | 418eb7e | 2012-12-10 01:55:48 +0000 | [diff] [blame] | 278 | #define CONFIG_POWER |
| 279 | #define CONFIG_POWER_I2C |
| 280 | #define CONFIG_POWER_MAX77686 |
Chander Kashyap | 5ff8061e | 2012-02-09 01:26:19 +0000 | [diff] [blame] | 281 | |
| 282 | /* SPI */ |
| 283 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 284 | #define CONFIG_SPI_FLASH |
| 285 | |
Chander Kashyap | d94e1f2 | 2012-09-05 00:38:21 +0000 | [diff] [blame] | 286 | #ifdef CONFIG_SPI_FLASH |
| 287 | #define CONFIG_EXYNOS_SPI |
| 288 | #define CONFIG_CMD_SF |
| 289 | #define CONFIG_CMD_SPI |
| 290 | #define CONFIG_SPI_FLASH_WINBOND |
| 291 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 292 | #define CONFIG_SF_DEFAULT_SPEED 50000000 |
| 293 | #define EXYNOS5_SPI_NUM_CONTROLLERS 5 |
| 294 | #endif |
| 295 | |
| 296 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH |
Rajeshwari Shinde | 4453d23 | 2012-10-25 19:49:30 +0000 | [diff] [blame] | 297 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 |
| 298 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE |
| 299 | #define CONFIG_ENV_SPI_BUS 1 |
| 300 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 |
| 301 | #endif |
| 302 | |
| 303 | /* Ethernet Controllor Driver */ |
| 304 | #ifdef CONFIG_CMD_NET |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 305 | #define CONFIG_SMC911X |
| 306 | #define CONFIG_SMC911X_BASE 0x5000000 |
| 307 | #define CONFIG_SMC911X_16_BIT |
| 308 | #define CONFIG_ENV_SROM_BANK 1 |
| 309 | #endif /*CONFIG_CMD_NET*/ |
| 310 | |
| 311 | /* Enable PXE Support */ |
| 312 | #ifdef CONFIG_CMD_NET |
| 313 | #define CONFIG_CMD_PXE |
| 314 | #define CONFIG_MENU |
| 315 | #endif |
| 316 | |
| 317 | /* Sound */ |
| 318 | #define CONFIG_CMD_SOUND |
| 319 | #ifdef CONFIG_CMD_SOUND |
| 320 | #define CONFIG_SOUND |
| 321 | #define CONFIG_I2S |
Rajeshwari Shinde | 4200a52 | 2013-02-14 19:46:16 +0000 | [diff] [blame] | 322 | #define CONFIG_SOUND_MAX98095 |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 323 | #define CONFIG_SOUND_WM8994 |
| 324 | #endif |
| 325 | |
| 326 | /* Enable devicetree support */ |
| 327 | #define CONFIG_OF_LIBFDT |
| 328 | |
Simon Glass | 9f68f8e | 2012-12-05 14:46:45 +0000 | [diff] [blame] | 329 | /* SHA hashing */ |
| 330 | #define CONFIG_CMD_HASH |
| 331 | #define CONFIG_HASH_VERIFY |
| 332 | #define CONFIG_SHA1 |
| 333 | #define CONFIG_SHA256 |
| 334 | |
Ajay Kumar | ca67ee2 | 2013-01-08 20:42:26 +0000 | [diff] [blame] | 335 | /* Display */ |
| 336 | #define CONFIG_LCD |
Ajay Kumar | 11575ae | 2013-01-10 21:06:10 +0000 | [diff] [blame] | 337 | #ifdef CONFIG_LCD |
Ajay Kumar | ca67ee2 | 2013-01-08 20:42:26 +0000 | [diff] [blame] | 338 | #define CONFIG_EXYNOS_FB |
| 339 | #define CONFIG_EXYNOS_DP |
| 340 | #define LCD_XRES 2560 |
| 341 | #define LCD_YRES 1600 |
| 342 | #define LCD_BPP LCD_COLOR16 |
Ajay Kumar | 11575ae | 2013-01-10 21:06:10 +0000 | [diff] [blame] | 343 | #endif |
Ajay Kumar | ca67ee2 | 2013-01-08 20:42:26 +0000 | [diff] [blame] | 344 | |
Akshay Saraswat | a3e6c19 | 2013-03-28 04:32:15 +0000 | [diff] [blame] | 345 | /* Enable Time Command */ |
| 346 | #define CONFIG_CMD_TIME |
| 347 | |
Chander Kashyap | ed2e25a | 2012-02-05 23:01:47 +0000 | [diff] [blame] | 348 | #endif /* __CONFIG_H */ |