blob: 74baa3fc40f53757a4cd46710cdd7e9319dcc960 [file] [log] [blame]
Stefan Roese181e06b2012-05-30 22:59:08 +00001/*
2 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <spartan3.h>
25#include <command.h>
26#include <asm/gpio.h>
27#include <asm/io.h>
28#include <asm/arch/hardware.h>
29#include <asm/arch/spr_misc.h>
30#include <asm/arch/spr_ssp.h>
31
32/*
33 * FPGA program pin configuration on X600:
34 *
35 * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
36 * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
37 * 16bit serial writes via this SSP port to write the data bits into the
38 * FPGA.
39 */
40#define CONFIG_SYS_FPGA_PROG 2
41#define CONFIG_SYS_FPGA_DONE 3
42
43/*
44 * Set the active-low FPGA reset signal.
45 */
46static void fpga_reset(int assert)
47{
48 /*
49 * On x600 we have no means to toggle the FPGA reset signal
50 */
51 debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
52}
53
54/*
55 * Set the FPGA's active-low SelectMap program line to the specified level
56 */
57static int fpga_pgm_fn(int assert, int flush, int cookie)
58{
59 debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
60
61 gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
62
63 return assert;
64}
65
66/*
67 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
68 * asserted (low).
69 */
70static int fpga_init_fn(int cookie)
71{
72 static int state;
73
74 debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
75
76 /*
77 * On x600, the FPGA INIT signal is not connected to the SoC.
78 * We can't read the INIT status. Let's return the "correct"
79 * INIT signal state generated via a local state-machine.
80 */
81 if (++state == 1) {
82 return 1;
83 } else {
84 state = 0;
85 return 0;
86 }
87}
88
89/*
90 * Test the state of the active-high FPGA DONE pin
91 */
92static int fpga_done_fn(int cookie)
93{
94 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
95
96 /*
97 * Wait for Tx-FIFO to become empty before looking for DONE
98 */
99 while (!(readl(&ssp->sspsr) & SSPSR_TFE))
100 ;
101
102 if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
103 return 1;
104 else
105 return 0;
106}
107
108/*
109 * FPGA pre-configuration function. Just make sure that
110 * FPGA reset is asserted to keep the FPGA from starting up after
111 * configuration.
112 */
113static int fpga_pre_config_fn(int cookie)
114{
115 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
York Sun4a598092013-04-01 11:29:11 -0700116 fpga_reset(true);
Stefan Roese181e06b2012-05-30 22:59:08 +0000117
118 return 0;
119}
120
121/*
122 * FPGA post configuration function. Blip the FPGA reset line and then see if
123 * the FPGA appears to be running.
124 */
125static int fpga_post_config_fn(int cookie)
126{
127 int rc = 0;
128
129 debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
130
York Sun4a598092013-04-01 11:29:11 -0700131 fpga_reset(true);
Stefan Roese181e06b2012-05-30 22:59:08 +0000132 udelay(100);
York Sun4a598092013-04-01 11:29:11 -0700133 fpga_reset(false);
Stefan Roese181e06b2012-05-30 22:59:08 +0000134 udelay(100);
135
136 return rc;
137}
138
139static int fpga_clk_fn(int assert_clk, int flush, int cookie)
140{
141 /*
142 * No dedicated clock signal on x600 (data & clock generated)
143 * in SSP interface. So we don't have to do anything here.
144 */
145 return assert_clk;
146}
147
148static int fpga_wr_fn(int assert_write, int flush, int cookie)
149{
150 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
151 static int count;
152 static u16 data;
153
154 /*
155 * First collect 16 bits of data
156 */
157 data = data << 1;
158 if (assert_write)
159 data |= 1;
160
161 /*
162 * If 16 bits are not available, return for more bits
163 */
164 count++;
165 if (count != 16)
166 return assert_write;
167
168 count = 0;
169
170 /*
171 * Wait for Tx-FIFO to become ready
172 */
173 while (!(readl(&ssp->sspsr) & SSPSR_TNF))
174 ;
175
176 /* Send 16 bits to FPGA via SSP bus */
177 writel(data, &ssp->sspdr);
178
179 return assert_write;
180}
181
182static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
183 fpga_pre_config_fn,
184 fpga_pgm_fn,
185 fpga_clk_fn,
186 fpga_init_fn,
187 fpga_done_fn,
188 fpga_wr_fn,
189 fpga_post_config_fn,
190};
191
192static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
193 XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
194};
195
196/*
197 * Initialize the SelectMap interface. We assume that the mode and the
198 * initial state of all of the port pins have already been set!
199 */
200static void fpga_serialslave_init(void)
201{
202 debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
York Sun4a598092013-04-01 11:29:11 -0700203 fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
Stefan Roese181e06b2012-05-30 22:59:08 +0000204}
205
206static int expi_setup(int freq)
207{
208 struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
209 int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
210
211 pll2_m = (freq * 2) / 1000;
212 pll2_n = 15;
213 pll2_p = 1;
214 expi_x = 1;
215 expi_y = 2;
216
217 /*
218 * Disable reset, Low compression, Disable retiming, Enable Expi,
219 * Enable soft reset, DMA, PLL2, Internal
220 */
221 writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
222 EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
223 EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
224 &misc->expi_clk_cfg);
225
226 /*
227 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
228 * Enable PLL2, Disable reset
229 */
230 writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
231 writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
232 PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
233
234 /*
235 * Disable soft reset
236 */
237 clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
238
239 return 0;
240}
241
242/*
243 * Initialize the fpga
244 */
245int x600_init_fpga(void)
246{
247 struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
248 struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
249
250 /* Enable SSP2 clock */
251 writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
252 &misc->periph1_clken);
253
254 /* Set EXPI clock to 45 MHz */
255 expi_setup(45000);
256
257 /* Configure GPIO directions */
258 gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
259 gpio_direction_input(CONFIG_SYS_FPGA_DONE);
260
261 writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
262 writel(SSPCR1_SSE, &ssp->sspcr1);
263
264 /*
265 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
266 * speed.
267 *
268 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
269 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
270 */
271 writel(2, &ssp->sspcpsr);
272
273 fpga_init();
274 fpga_serialslave_init();
275
276 debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
277 fpga_add(fpga_xilinx, &fpga[0]);
278
279 return 0;
280}