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Stefano Babicf02e6972011-01-20 08:05:15 +00001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <config.h>
23#include <asm/arch/imx-regs.h>
Stefano Babic2a1f1ac2011-09-05 04:32:28 +000024#include <generated/asm-offsets.h>
Stefano Babicf02e6972011-01-20 08:05:15 +000025#include "mx35pdk.h"
Benoît Thébaudeau5cc51c52012-08-20 09:54:53 +000026#include <asm/arch/lowlevel_macro.S>
Stefano Babicf02e6972011-01-20 08:05:15 +000027
28/*
29 * return soc version
30 * 0x10: TO1
31 * 0x20: TO2
32 * 0x30: TO3
33 */
34.macro check_soc_version ret, tmp
35 ldr \tmp, =IIM_BASE_ADDR
36 ldr \ret, [\tmp, #IIM_SREV]
37 cmp \ret, #0x00
38 moveq \tmp, #ROMPATCH_REV
39 ldreq \ret, [\tmp]
40 moveq \ret, \ret, lsl #4
41 addne \ret, \ret, #0x10
42.endm
43
Stefano Babicf02e6972011-01-20 08:05:15 +000044/* CPLD on CS5 setup */
45.macro init_debug_board
46 ldr r0, =DBG_BASE_ADDR
47 ldr r1, =DBG_CSCR_U_CONFIG
48 str r1, [r0, #0x00]
49 ldr r1, =DBG_CSCR_L_CONFIG
50 str r1, [r0, #0x04]
51 ldr r1, =DBG_CSCR_A_CONFIG
52 str r1, [r0, #0x08]
53.endm
54
55/* clock setup */
56.macro init_clock
57 ldr r0, =CCM_BASE_ADDR
58
59 /* default CLKO to 1/32 of the ARM core*/
60 ldr r1, [r0, #CLKCTL_COSR]
61 bic r1, r1, #0x00000FF00
62 bic r1, r1, #0x0000000FF
63 mov r2, #0x00006C00
64 add r2, r2, #0x67
65 orr r1, r1, r2
66 str r1, [r0, #CLKCTL_COSR]
67
68 ldr r2, =CCM_CCMR_CONFIG
69 str r2, [r0, #CLKCTL_CCMR]
70
71 check_soc_version r1, r2
72 cmp r1, #CHIP_REV_2_0
73 ldrhs r3, =CCM_MPLL_532_HZ
74 bhs 1f
75 ldr r2, [r0, #CLKCTL_PDR0]
76 tst r2, #CLKMODE_CONSUMER
77 ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
78 ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
791:
80 str r3, [r0, #CLKCTL_MPCTL]
81
82 ldr r1, =CCM_PPLL_300_HZ
83 str r1, [r0, #CLKCTL_PPCTL]
84
85 ldr r1, =CCM_PDR0_CONFIG
86 bic r1, r1, #0x800000
87 str r1, [r0, #CLKCTL_PDR0]
88
89 ldr r1, [r0, #CLKCTL_CGR0]
90 orr r1, r1, #0x0C300000
91 str r1, [r0, #CLKCTL_CGR0]
92
93 ldr r1, [r0, #CLKCTL_CGR1]
94 orr r1, r1, #0x00000C00
95 orr r1, r1, #0x00000003
96 str r1, [r0, #CLKCTL_CGR1]
Benoît Thébaudeau50af5db2012-11-13 09:58:25 +000097
98 ldr r1, [r0, #CLKCTL_CGR2]
99 orr r1, r1, #0x00C00000
100 str r1, [r0, #CLKCTL_CGR2]
Stefano Babicf02e6972011-01-20 08:05:15 +0000101.endm
102
103.macro setup_sdram
104 ldr r0, =ESDCTL_BASE_ADDR
105 mov r3, #0x2000
106 str r3, [r0, #0x0]
107 str r3, [r0, #0x8]
108
109 /*ip(r12) has used to save lr register in upper calling*/
110 mov fp, lr
111
112 mov r5, #0x00
113 mov r2, #0x00
114 mov r1, #CSD0_BASE_ADDR
115 bl setup_sdram_bank
Stefano Babic19edc942011-08-02 14:42:36 +0200116
117 mov r5, #0x00
118 mov r2, #0x00
119 mov r1, #CSD1_BASE_ADDR
120 bl setup_sdram_bank
Stefano Babicf02e6972011-01-20 08:05:15 +0000121
122 mov lr, fp
123
1241:
125 ldr r3, =ESDCTL_DELAY_LINE5
126 str r3, [r0, #0x30]
127.endm
128
129.globl lowlevel_init
130lowlevel_init:
131 mov r10, lr
132
Benoît Thébaudeau5cc51c52012-08-20 09:54:53 +0000133 core_init
Stefano Babicf02e6972011-01-20 08:05:15 +0000134
135 init_aips
136
137 init_max
138
139 init_m3if
140
141 init_clock
142 init_debug_board
143
144 cmp pc, #PHYS_SDRAM_1
145 blo init_sdram_start
146 cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
147 blo skip_sdram_setup
148
149init_sdram_start:
150 /*init_sdram*/
151 setup_sdram
152
153skip_sdram_setup:
154 mov lr, r10
155 mov pc, lr
156
157
158/*
159 * r0: ESDCTL control base, r1: sdram slot base
160 * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
161 */
162setup_sdram_bank:
163 mov r3, #0xE
164 tst r2, #0x1
165 orreq r3, r3, #0x300 /*DDR2*/
166 str r3, [r0, #0x10]
167 bic r3, r3, #0x00A
168 str r3, [r0, #0x10]
169 beq 2f
170
171 mov r3, #0x20000
1721: subs r3, r3, #1
173 bne 1b
174
1752: tst r2, #0x1
176 ldreq r3, =ESDCTL_DDR2_CONFIG
177 ldrne r3, =ESDCTL_MDDR_CONFIG
178 cmp r1, #CSD1_BASE_ADDR
179 strlo r3, [r0, #0x4]
180 strhs r3, [r0, #0xC]
181
182 ldr r3, =ESDCTL_0x92220000
183 strlo r3, [r0, #0x0]
184 strhs r3, [r0, #0x8]
185 mov r3, #0xDA
186 ldr r4, =ESDCTL_PRECHARGE
187 strb r3, [r1, r4]
188
189 tst r2, #0x1
190 bne skip_set_mode
191
192 cmp r1, #CSD1_BASE_ADDR
193 ldr r3, =ESDCTL_0xB2220000
194 strlo r3, [r0, #0x0]
195 strhs r3, [r0, #0x8]
196 mov r3, #0xDA
197 ldr r4, =ESDCTL_DDR2_EMR2
198 strb r3, [r1, r4]
199 ldr r4, =ESDCTL_DDR2_EMR3
200 strb r3, [r1, r4]
201 ldr r4, =ESDCTL_DDR2_EN_DLL
202 strb r3, [r1, r4]
203 ldr r4, =ESDCTL_DDR2_RESET_DLL
204 strb r3, [r1, r4]
205
206 ldr r3, =ESDCTL_0x92220000
207 strlo r3, [r0, #0x0]
208 strhs r3, [r0, #0x8]
209 mov r3, #0xDA
210 ldr r4, =ESDCTL_PRECHARGE
211 strb r3, [r1, r4]
212
213skip_set_mode:
214 cmp r1, #CSD1_BASE_ADDR
215 ldr r3, =ESDCTL_0xA2220000
216 strlo r3, [r0, #0x0]
217 strhs r3, [r0, #0x8]
218 mov r3, #0xDA
219 strb r3, [r1]
220 strb r3, [r1]
221
222 ldr r3, =ESDCTL_0xB2220000
223 strlo r3, [r0, #0x0]
224 strhs r3, [r0, #0x8]
225 tst r2, #0x1
226 ldreq r4, =ESDCTL_DDR2_MR
227 ldrne r4, =ESDCTL_MDDR_MR
228 mov r3, #0xDA
229 strb r3, [r1, r4]
230 ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
231 streqb r3, [r1, r4]
232 ldreq r4, =ESDCTL_DDR2_EN_DLL
233 ldrne r4, =ESDCTL_MDDR_EMR
234 strb r3, [r1, r4]
235
236 cmp r1, #CSD1_BASE_ADDR
237 ldr r3, =ESDCTL_0x82228080
238 strlo r3, [r0, #0x0]
239 strhs r3, [r0, #0x8]
240
241 tst r2, #0x1
242 moveq r4, #0x20000
243 movne r4, #0x200
2441: subs r4, r4, #1
245 bne 1b
246
247 str r3, [r1, #0x100]
248 ldr r4, [r1, #0x100]
249 cmp r3, r4
250 movne r3, #1
251 moveq r3, #0
252
253 mov pc, lr