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git01.mediatek.com / filogic / uboot / ed2724bba86823df712326f3ade7bbe41d7601c7 / . / arch / arm / dts / imx8mp-evk-u-boot.dtsi
blob: f43eb6238d03cf295eb42fc6eeff51f73a1f2b46 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]3 * Copyright 2019, 2021 NXP
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]4 */
5
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]6#include "imx8mp-u-boot.dtsi"
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]7
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]8/ {
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]9 wdt-reboot {
10 compatible = "wdt-reboot";
11 wdt = <&wdog1>;
12 u-boot,dm-spl;
13 };
Clement Faurea93b0d92021-03-25 17:30:33 +0800[diff] [blame]14 firmware {
15 optee {
16 compatible = "linaro,optee-tz";
17 method = "smc";
18 };
19 };
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]20};
21
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]22&reg_usdhc2_vmmc {
Andrey Zhizhikincf51a552020-12-05 17:29:17 +0000[diff] [blame]23 u-boot,off-on-delay-us = <20000>;
24};
25
26&reg_usdhc2_vmmc {
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]27 u-boot,dm-spl;
28};
29
30&pinctrl_uart2 {
31 u-boot,dm-spl;
32};
33
34&pinctrl_usdhc2_gpio {
35 u-boot,dm-spl;
36};
37
38&pinctrl_usdhc2 {
39 u-boot,dm-spl;
40};
41
42&pinctrl_usdhc3 {
43 u-boot,dm-spl;
44};
45
Peng Fane22df442022-05-05 19:05:59 +0800[diff] [blame]46&pinctrl_wdog {
47 u-boot,dm-spl;
48};
49
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]50&gpio1 {
51 u-boot,dm-spl;
52};
53
54&gpio2 {
55 u-boot,dm-spl;
56};
57
58&gpio3 {
59 u-boot,dm-spl;
60};
61
62&gpio4 {
63 u-boot,dm-spl;
64};
65
66&gpio5 {
67 u-boot,dm-spl;
68};
69
70&uart2 {
71 u-boot,dm-spl;
72};
73
Gaurav Jainbce9acf2022-03-24 11:50:26 +0530[diff] [blame]74&crypto {
75 u-boot,dm-spl;
76};
77
78&sec_jr0 {
79 u-boot,dm-spl;
80};
81
82&sec_jr1 {
83 u-boot,dm-spl;
84};
85
86&sec_jr2 {
87 u-boot,dm-spl;
88};
89
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]90&i2c1 {
91 u-boot,dm-spl;
92};
93
94&i2c2 {
95 u-boot,dm-spl;
96};
97
98&i2c3 {
99 u-boot,dm-spl;
100};
101
102&i2c4 {
103 u-boot,dm-spl;
104};
105
106&i2c5 {
107 u-boot,dm-spl;
108};
109
110&i2c6 {
111 u-boot,dm-spl;
112};
113
114&usdhc1 {
115 u-boot,dm-spl;
116};
117
118&usdhc2 {
119 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]120 sd-uhs-sdr104;
121 sd-uhs-ddr50;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]122};
123
124&usdhc3 {
125 u-boot,dm-spl;
Andrey Zhizhikin9aa95982020-12-05 17:29:18 +0000[diff] [blame]126 mmc-hs400-1_8v;
127 mmc-hs400-enhanced-strobe;
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]128};
Marek Vasut797a19a2020-04-29 15:04:26 +0200[diff] [blame]129
130&wdog1 {
131 u-boot,dm-spl;
132};
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]133
Ye Li25804942021-08-16 18:44:28 +0800[diff] [blame]134&eqos {
Ye Li25804942021-08-16 18:44:28 +0800[diff] [blame]135 /delete-property/ assigned-clocks;
136 /delete-property/ assigned-clock-parents;
137 /delete-property/ assigned-clock-rates;
138};
139
140&ethphy0 {
141 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
142 reset-delay-us = <15000>;
143 reset-post-delay-us = <100000>;
144};
145
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]146&fec {
147 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
Ye Lid1b82062021-02-18 22:33:48 -0800[diff] [blame]148 phy-reset-duration = <15>;
149 phy-reset-post-delay = <100>;
Peng Fan4f0c97b2020-12-25 16:16:34 +0800[diff] [blame]150};
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]151
Peng Fand96d94b2021-04-06 11:59:02 +0800[diff] [blame]152