blob: 2129dfd804c90418140f17cb9dc2c640240b33c0 [file] [log] [blame]
wdenkbb1b8262003-03-27 12:09:35 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkbb1b8262003-03-27 12:09:35 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the INCA-IP board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
32#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
33
wdenk5d841732003-08-17 18:55:18 +000034#ifndef CPU_CLOCK_RATE
wdenk92bbe3f2003-04-20 14:04:18 +000035/* allowed values: 100000000, 133000000, and 150000000 */
wdenk41d153a2004-01-06 11:32:21 +000036#define CPU_CLOCK_RATE 150000000 /* default: 150 MHz clock for the MIPS core */
wdenk5d841732003-08-17 18:55:18 +000037#endif
wdenkbb1b8262003-03-27 12:09:35 +000038
wdenk67f13362003-12-27 19:24:54 +000039#define INFINEON_EBU_BOOTCFG 0x40C4 /* CMULT = 8 */
wdenkbb1b8262003-03-27 12:09:35 +000040
wdenkb02744a2003-04-05 00:53:31 +000041#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkbb1b8262003-03-27 12:09:35 +000042
wdenkb02744a2003-04-05 00:53:31 +000043#define CONFIG_BAUDRATE 115200
wdenkbb1b8262003-03-27 12:09:35 +000044
45/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkbb1b8262003-03-27 12:09:35 +000047
wdenkb02744a2003-04-05 00:53:31 +000048#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49
50#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk1baed662008-03-03 12:16:44 +010051 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkb02744a2003-04-05 00:53:31 +000052 "echo"
53
54#undef CONFIG_BOOTARGS
55
56#define CONFIG_EXTRA_ENV_SETTINGS \
57 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010058 "nfsroot=${serverip}:${rootpath}\0" \
wdenkb02744a2003-04-05 00:53:31 +000059 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010060 "addip=setenv bootargs ${bootargs} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
62 ":${hostname}:${netdev}:off\0" \
63 "addmisc=setenv bootargs ${bootargs} " \
64 "console=ttyS0,${baudrate} " \
65 "ethaddr=${ethaddr} " \
wdenkb02744a2003-04-05 00:53:31 +000066 "panic=1\0" \
67 "flash_nfs=run nfsargs addip addmisc;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010068 "bootm ${kernel_addr}\0" \
wdenkb02744a2003-04-05 00:53:31 +000069 "flash_self=run ramargs addip addmisc;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010070 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
71 "net_nfs=tftp 80500000 ${bootfile};" \
wdenkb02744a2003-04-05 00:53:31 +000072 "run nfsargs addip addmisc;bootm\0" \
73 "rootpath=/opt/eldk/mips_4KC\0" \
74 "bootfile=/tftpboot/INCA/uImage\0" \
75 "kernel_addr=B0040000\0" \
76 "ramdisk_addr=B0100000\0" \
77 "u-boot=/tftpboot/INCA/u-boot.bin\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010078 "load=tftp 80500000 ${u-boot}\0" \
wdenkb02744a2003-04-05 00:53:31 +000079 "update=protect off 1:0-2;era 1:0-2;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010080 "cp.b 80500000 B0000000 ${filesize}\0" \
wdenkb02744a2003-04-05 00:53:31 +000081 ""
82#define CONFIG_BOOTCOMMAND "run flash_self"
83
Jon Loeliger860435b2007-07-04 22:32:32 -050084
85/*
Jon Loeliger140b69c2007-07-10 09:38:02 -050086 * BOOTP options
87 */
88#define CONFIG_BOOTP_BOOTFILESIZE
89#define CONFIG_BOOTP_BOOTPATH
90#define CONFIG_BOOTP_GATEWAY
91#define CONFIG_BOOTP_HOSTNAME
92
93
94/*
Jon Loeliger860435b2007-07-04 22:32:32 -050095 * Command line configuration.
96 */
97#include <config_cmd_default.h>
98
99#define CONFIG_CMD_ASKENV
100#define CONFIG_CMD_DHCP
101#define CONFIG_CMD_ELF
102#define CONFIG_CMD_JFFS2
103#define CONFIG_CMD_NFS
104#define CONFIG_CMD_PING
105#define CONFIG_CMD_SNTP
106
wdenkbb1b8262003-03-27 12:09:35 +0000107
108/*
109 * Miscellaneous configurable options
110 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_LONGHELP /* undef to save memory */
112#define CONFIG_SYS_PROMPT "INCA-IP # " /* Monitor Command Prompt */
113#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenkbb1b8262003-03-27 12:09:35 +0000116
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenkb02744a2003-04-05 00:53:31 +0000118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenkb02744a2003-04-05 00:53:31 +0000120
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2)
Shinya Kuribayashi5d374e02008-06-05 22:29:00 +0900122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_HZ 1000
wdenkb02744a2003-04-05 00:53:31 +0000124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_SDRAM_BASE 0x80000000
wdenkb02744a2003-04-05 00:53:31 +0000126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_LOAD_ADDR 0x80100000 /* default load address */
wdenkbb1b8262003-03-27 12:09:35 +0000128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_MEMTEST_START 0x80100000
130#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenkbb1b8262003-03-27 12:09:35 +0000131
132/*-----------------------------------------------------------------------
133 * FLASH and environment organization
134 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
136#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenkbb1b8262003-03-27 12:09:35 +0000137
138#define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
139#define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
140
141/* The following #defines are needed to get flash environment right */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
143#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenkbb1b8262003-03-27 12:09:35 +0000144
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200145#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenkbb1b8262003-03-27 12:09:35 +0000146
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkbb1b8262003-03-27 12:09:35 +0000148
149/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
151#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkbb1b8262003-03-27 12:09:35 +0000152
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200153#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbb1b8262003-03-27 12:09:35 +0000154
155/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200156#define CONFIG_ENV_ADDR 0xB0030000
157#define CONFIG_ENV_SIZE 0x10000
wdenkbb1b8262003-03-27 12:09:35 +0000158
159#define CONFIG_FLASH_16BIT
160
161#define CONFIG_NR_DRAM_BANKS 1
162
163#define CONFIG_INCA_IP_SWITCH
164#define CONFIG_NET_MULTI
wdenkdb82c8e2004-02-26 23:01:04 +0000165#define CONFIG_INCA_IP_SWITCH_AMDIX
wdenkbb1b8262003-03-27 12:09:35 +0000166
Wolfgang Denk47f57792005-08-08 01:03:24 +0200167/*
168 * JFFS2 partitions
169 */
170/* No command line, one static partition, use all space on the device */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100171#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200172#define CONFIG_JFFS2_DEV "nor1"
173#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
174#define CONFIG_JFFS2_PART_OFFSET 0x00000000
175
176/* mtdparts command line support */
177/*
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100178#define CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200179#define MTDIDS_DEFAULT "nor0=INCA-IP Bank 0"
180#define MTDPARTS_DEFAULT "mtdparts=INCA-IP Bank 0:192k(uboot)," \
181 "64k(env)," \
182 "768k(linux)," \
183 "1m@3m(rootfs)," \
184 "768k(linux2)," \
185 "3m@5m(rootfs2)"
186*/
wdenkdf28aa02003-12-12 00:02:26 +0000187
wdenkbb1b8262003-03-27 12:09:35 +0000188/*-----------------------------------------------------------------------
189 * Cache Configuration
190 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_DCACHE_SIZE 4096
192#define CONFIG_SYS_ICACHE_SIZE 4096
193#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbb1b8262003-03-27 12:09:35 +0000194
195#endif /* __CONFIG_H */