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git01.mediatek.com / filogic / uboot / ecf32415ec242904555d820578fa03f3037f6d99 / . / drivers / video / sunxi / tve_common.c
blob: b3e9bd98ef1445a2d353ea1a1d91f38bf25bac3f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Jernej Skrabec8531d082017-05-10 18:46:28 +0200[diff] [blame]2/*
3 * TV encoder driver for Allwinner SoCs.
4 *
5 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
6 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
7 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
Jernej Skrabec8531d082017-05-10 18:46:28 +0200[diff] [blame]8 */
9
Jernej Skrabec8531d082017-05-10 18:46:28 +0200[diff] [blame]10#include <asm/arch/tve.h>
11#include <asm/io.h>
12
13void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode)
14{
15 switch (mode) {
16 case tve_mode_vga:
17 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
18 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
19 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
20 writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0);
21 writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0);
22 writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1);
23 break;
24 case tve_mode_composite_pal_nc:
25 writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq);
26 /* Fall through */
27 case tve_mode_composite_pal:
28 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
29 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
30 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
31 SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
32 writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0);
33 writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
34 writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
35 writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num);
36 writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num);
37 writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL,
38 &tve->blank_black_level);
39 writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
40 writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level);
41 writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
42 writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2);
43 writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
44 writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
45 writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
46 writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num);
47 writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
48 break;
49 case tve_mode_composite_pal_m:
50 writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq);
51 writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst);
52 /* Fall through */
53 case tve_mode_composite_ntsc:
54 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
55 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
56 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
57 SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
58 writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0);
59 writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
60 writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
61 writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num);
62 writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num);
63 writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC,
64 &tve->blank_black_level);
65 writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
66 writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level);
67 writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase);
68 writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
69 writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2);
70 writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level);
71 writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
72 writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
73 writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
74 writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num);
75 writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
76 break;
77 }
78}
79
80void tvencoder_enable(struct sunxi_tve_reg * const tve)
81{
82 setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
83}