blob: e3ecc8d373577f2365dd7412e2cea50be4a559b1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warren3017ab52016-09-13 10:45:58 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warren3017ab52016-09-13 10:45:58 -06004 */
5
Stephen Warren3017ab52016-09-13 10:45:58 -06006#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06007#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -07008#include <malloc.h>
Stephen Warren3017ab52016-09-13 10:45:58 -06009#include <reset-uclass.h>
10#include <asm/arch/clock.h>
11#include <asm/arch-tegra/clk_rst.h>
12
13static int tegra_car_reset_request(struct reset_ctl *reset_ctl)
14{
15 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
16 reset_ctl->dev, reset_ctl->id);
17
18 /* PERIPH_ID_COUNT varies per SoC */
19 if (reset_ctl->id >= PERIPH_ID_COUNT)
20 return -EINVAL;
21
22 return 0;
23}
24
Stephen Warren3017ab52016-09-13 10:45:58 -060025static int tegra_car_reset_assert(struct reset_ctl *reset_ctl)
26{
27 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
28 reset_ctl->dev, reset_ctl->id);
29
30 reset_set_enable(reset_ctl->id, 1);
31
32 return 0;
33}
34
35static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl)
36{
37 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
38 reset_ctl->dev, reset_ctl->id);
39
40 reset_set_enable(reset_ctl->id, 0);
41
42 return 0;
43}
44
45struct reset_ops tegra_car_reset_ops = {
46 .request = tegra_car_reset_request,
Stephen Warren3017ab52016-09-13 10:45:58 -060047 .rst_assert = tegra_car_reset_assert,
48 .rst_deassert = tegra_car_reset_deassert,
49};
50
Stephen Warren3017ab52016-09-13 10:45:58 -060051U_BOOT_DRIVER(tegra_car_reset) = {
52 .name = "tegra_car_reset",
53 .id = UCLASS_RESET,
Stephen Warren3017ab52016-09-13 10:45:58 -060054 .ops = &tegra_car_reset_ops,
55};