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git01.mediatek.com / filogic / uboot / ecefa5fd16783645876f7ca685813118f6e1baa6 / . / include / zynqmp_tap_delay.h
blob: 7b713438f75249cfc2402fed650fe655ce7cd6a4 [file] [log] [blame]
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx ZynqMP SoC Tap Delay Programming
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7
8#ifndef __ZYNQMP_TAP_DELAY_H__
9#define __ZYNQMP_TAP_DELAY_H__
10
11#ifdef CONFIG_ARCH_ZYNQMP
12void zynqmp_dll_reset(u8 deviceid);
Ashok Reddy Soma5fe3f412020-10-23 04:59:04 -0600[diff] [blame]13void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay);
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]14#else
15inline void zynqmp_dll_reset(u8 deviceid) {}
Ashok Reddy Soma5fe3f412020-10-23 04:59:04 -0600[diff] [blame]16inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay,
17 u32 otap_delay) {}
Siva Durga Prasad Paladugucad14a82018-04-19 12:37:09 +0530[diff] [blame]18#endif
19
20#endif