blob: 6d85b2d91a7a5a6fd24a003a5f0ba9c41d221b90 [file] [log] [blame]
Hal Fengbaf555d2024-12-08 17:19:35 +08001// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2023 StarFive Technology Co., Ltd.
4 */
5
Hal Fengbaf555d2024-12-08 17:19:35 +08006#include "jh7110-u-boot.dtsi"
7/ {
8 aliases {
9 spi0 = &qspi;
10 };
11
12 chosen {
13 bootph-pre-ram;
14 };
15
16 firmware {
17 spi0 = &qspi;
18 bootph-pre-ram;
19 };
20
Hal Fengbaf555d2024-12-08 17:19:35 +080021 memory@40000000 {
22 bootph-pre-ram;
23 };
24};
25
26&uart0 {
27 bootph-pre-ram;
28 reg-offset = <0>;
29 current-speed = <115200>;
30 clock-frequency = <24000000>;
31};
32
33&mmc0 {
34 bootph-pre-ram;
35};
36
37&mmc1 {
38 bootph-pre-ram;
39};
40
41&qspi {
42 bootph-pre-ram;
43
44 flash@0 {
45 bootph-pre-ram;
46 cdns,read-delay = <2>;
47 spi-max-frequency = <100000000>;
48 };
49};
50
51&syscrg {
52 assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
53 <&syscrg JH7110_SYSCLK_BUS_ROOT>,
54 <&syscrg JH7110_SYSCLK_PERH_ROOT>,
55 <&syscrg JH7110_SYSCLK_QSPI_REF>;
56 assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
57 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
58 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
59 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
60 assigned-clock-rates = <0>, <0>, <0>, <0>;
61};
62
63&sysgpio {
64 bootph-pre-ram;
65};
66
67&mmc0_pins {
68 bootph-pre-ram;
69 rst-pins {
70 bootph-pre-ram;
71 };
72};
73
74&mmc1_pins {
75 bootph-pre-ram;
76 clk-pins {
77 bootph-pre-ram;
78 };
79
80 mmc-pins {
81 bootph-pre-ram;
82 };
83};
84
85&i2c5_pins {
86 bootph-pre-ram;
87 i2c-pins {
88 bootph-pre-ram;
89 };
90};
91
92&i2c5 {
93 bootph-pre-ram;
94 eeprom@50 {
95 bootph-pre-ram;
96 compatible = "atmel,24c04";
97 reg = <0x50>;
98 pagesize = <16>;
99 };
100};