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Ley Foon Tanc46f6a62019-11-27 15:55:31 +08001/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
4 *
5 */
6
7#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
8#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
9
Siew Chin Lim142d9c02021-08-10 11:26:27 +080010#include <asm/arch/base_addr_soc64.h>
Siew Chin Lim954d5992021-03-24 13:11:34 +080011#include <asm/arch/handoff_soc64.h>
Simon Glassfb64e362020-05-10 11:40:09 -060012#include <linux/stringify.h>
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080013
14/*
15 * U-Boot general configurations
16 */
17#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
18#define CONFIG_LOADADDR 0x2000000
19#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
20#define CONFIG_REMAKE_ELF
21/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
22#define CPU_RELEASE_ADDR 0xFFD12210
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080023
24/*
25 * U-Boot console configurations
26 */
27#define CONFIG_SYS_MAXARGS 64
28#define CONFIG_SYS_CBSIZE 2048
29#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
30 sizeof(CONFIG_SYS_PROMPT) + 16)
31#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
32
33/* Extend size of kernel image for uncompression */
34#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
35
36/*
37 * U-Boot run time memory configurations
38 */
39#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
40#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
Chee Hong Ang25d45cb2020-12-24 18:21:09 +080041#ifdef CONFIG_SPL_BUILD
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080042#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
43 + CONFIG_SYS_INIT_RAM_SIZE \
Siew Chin Lim954d5992021-03-24 13:11:34 +080044 - SOC64_HANDOFF_SIZE)
Chee Hong Ang25d45cb2020-12-24 18:21:09 +080045#else
46#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \
47 + 0x100000)
48#endif
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080049#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
50#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
51
52/*
53 * U-Boot environment configurations
54 */
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080055
56/*
57 * QSPI support
58 */
59 #ifdef CONFIG_CADENCE_QSPI
60/* Enable it if you want to use dual-stacked mode */
61/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
62
63/* Flash device info */
64
65/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
66
67#ifndef CONFIG_SPL_BUILD
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080068#define CONFIG_MTD_PARTITIONS
69#define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
70#endif /* CONFIG_SPL_BUILD */
71
72#ifndef __ASSEMBLY__
73unsigned int cm_get_qspi_controller_clk_hz(void);
74#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
75#endif
76
77#endif /* CONFIG_CADENCE_QSPI */
78
79/*
Siew Chin Lim14b8a482021-03-01 20:04:14 +080080 * Environment variable
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080081 */
Chee Hong Angf28875c2020-12-24 18:20:57 +080082
83#ifdef CONFIG_FIT
84#define CONFIG_BOOTFILE "kernel.itb"
Chee Hong Angf28875c2020-12-24 18:20:57 +080085#else
86#define CONFIG_BOOTFILE "Image"
Chee Hong Angf28875c2020-12-24 18:20:57 +080087#endif
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080088
89#define CONFIG_EXTRA_ENV_SETTINGS \
90 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Chee Hong Angf28875c2020-12-24 18:20:57 +080091 "bootfile=" CONFIG_BOOTFILE "\0" \
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080092 "fdt_addr=8000000\0" \
Ley Foon Tan461d2982019-11-27 15:55:32 +080093 "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
Ley Foon Tanc46f6a62019-11-27 15:55:31 +080094 "mmcroot=/dev/mmcblk0p2\0" \
95 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
96 " root=${mmcroot} rw rootwait;" \
97 "booti ${loadaddr} - ${fdt_addr}\0" \
98 "mmcload=mmc rescan;" \
99 "load mmc 0:1 ${loadaddr} ${bootfile};" \
100 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
Chee Hong Angf28875c2020-12-24 18:20:57 +0800101 "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
102 " root=${mmcroot} rw rootwait;" \
103 "bootm ${loadaddr}\0" \
104 "mmcfitload=mmc rescan;" \
105 "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800106 "linux_qspi_enable=if sf probe; then " \
107 "echo Enabling QSPI at Linux DTB...;" \
108 "fdt addr ${fdt_addr}; fdt resize;" \
109 "fdt set /soc/spi@ff8d2000 status okay;" \
110 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
111 " ${qspi_clock}; fi; \0" \
112 "scriptaddr=0x02100000\0" \
113 "scriptfile=u-boot.scr\0" \
114 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
115 "then source ${scriptaddr}; fi\0" \
116 "socfpga_legacy_reset_compat=1\0"
117
118/*
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800119 * External memory configurations
120 */
121#define PHYS_SDRAM_1 0x0
122#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
123#define CONFIG_SYS_SDRAM_BASE 0
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800124
125/*
126 * Serial / UART configurations
127 */
128#define CONFIG_SYS_NS16550_CLK 100000000
129#define CONFIG_SYS_NS16550_MEM32
130
131/*
132 * Timer & watchdog configurations
133 */
134#define COUNTER_FREQUENCY 400000000
135
136/*
137 * SDMMC configurations
138 */
139#ifdef CONFIG_CMD_MMC
140#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
141#endif
142/*
143 * Flash configurations
144 */
145#define CONFIG_SYS_MAX_FLASH_BANKS 1
146
147/* Ethernet on SoC (EMAC) */
148#if defined(CONFIG_CMD_NET)
149#define CONFIG_DW_ALTDESCRIPTOR
150#endif /* CONFIG_CMD_NET */
151
152/*
153 * L4 Watchdog
154 */
Marek Vasut8655f672019-06-27 01:19:23 +0200155#ifndef CONFIG_SPL_BUILD
Marek Vasut40919d92019-06-27 00:26:34 +0200156#undef CONFIG_HW_WATCHDOG
157#undef CONFIG_DESIGNWARE_WATCHDOG
158#endif
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800159#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
Ley Foon Tan461d2982019-11-27 15:55:32 +0800160#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800161#ifndef __ASSEMBLY__
162unsigned int cm_get_l4_sys_free_clk_hz(void);
163#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
164#endif
Ley Foon Tan461d2982019-11-27 15:55:32 +0800165#else
166#define CONFIG_DW_WDT_CLOCK_KHZ 100000
167#endif
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800168
169/*
170 * SPL memory layout
171 *
172 * On chip RAM
173 * 0xFFE0_0000 ...... Start of OCRAM
174 * SPL code, rwdata
175 * empty space
176 * 0xFFEx_xxxx ...... Top of stack (grows down)
177 * 0xFFEy_yyyy ...... Global Data
178 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
179 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
180 * 0xFFE3_FFFF ...... End of OCRAM
181 *
182 * SDRAM
183 * 0x0000_0000 ...... Start of SDRAM_1
184 * unused / empty space for image loading
185 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
186 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
187 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
188 *
189 */
Dalon Westergreen3a8621c2021-03-01 20:04:16 +0800190#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex"
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800191#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
192#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
193#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
194#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
195 - CONFIG_SPL_BSS_MAX_SIZE)
196#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
197#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
198 - CONFIG_SYS_SPL_MALLOC_SIZE)
199
200/* SPL SDMMC boot support */
Chee Hong Angf28875c2020-12-24 18:20:57 +0800201#ifdef CONFIG_SPL_LOAD_FIT
202#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
203#else
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800204#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Chee Hong Angf28875c2020-12-24 18:20:57 +0800205#endif
Ley Foon Tanc46f6a62019-11-27 15:55:31 +0800206
207#endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */