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git01.mediatek.com / filogic / uboot / ec1340d34cc7dfc71c58216bd7b8ab3844bb91eb / . / board / pm856 / pm856.c
blob: da4fd883365cfe49313992d79a8157948cd68091 [file] [log] [blame]
Wolfgang Denk9733b3c2005-08-05 12:19:30 +0200[diff] [blame]1/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
31#include <asm/immap_85xx.h>
32#include <ioports.h>
33#include <spd.h>
34#include <miiphy.h>
35
36#if defined(CONFIG_DDR_ECC)
37extern void ddr_enable_ecc(unsigned int dram_size);
38#endif
39
40extern long int spd_sdram(void);
41
42void local_bus_init(void);
43long int fixed_sdram(void);
44
45/*
46 * I/O Port configuration table
47 *
48 * if conf is 1, then that port pin will be configured at boot time
49 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 */
51
52const iop_conf_t iop_conf_tab[4][32] = {
53
54 /* Port A configuration */
55 { /* conf ppar psor pdir podr pdat */
56 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
57 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
58 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
59 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
60 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
61 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
62 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
63 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
64 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
65 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
66 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
67 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
68 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
69 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
70 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
71 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
72 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
73 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
74 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
75 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
76 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
77 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
78 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
79 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
80 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
81 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
82 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
83 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
84 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
85 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
86 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
87 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
88 },
89
90 /* Port B configuration */
91 { /* conf ppar psor pdir podr pdat */
92 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
93 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
94 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
95 /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
96 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
97 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
98 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
99 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
100 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
101 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
102 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
103 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
104 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
105 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
106 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
107 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
108 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
109 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
110 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
111 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
112 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
124 },
125
126 /* Port C */
127 { /* conf ppar psor pdir podr pdat */
128 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
129 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
130 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
131 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
132 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
133 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
134 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
135 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
136 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
137 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
138 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
139 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
140 /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
141 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
142 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
143 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
144 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
145 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
146 /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
147 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
148 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
149 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
150 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
151 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
152 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
153 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
154 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
155 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
156 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
157 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
158 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
159 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
160 },
161
162 /* Port D */
163 { /* conf ppar psor pdir podr pdat */
164 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
165 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
166 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
167 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
168 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
169 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
170 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
171 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
172 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
173 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
174 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
175 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
176 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
177 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
178 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
179 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
180 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
191 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 }
197};
198
199
200int board_early_init_f (void)
201{
202 return 0;
203}
204
205void reset_phy (void)
206{
207}
208
209
210int checkboard (void)
211{
212 puts("Board: MicroSys PM856\n");
213
214#ifdef CONFIG_PCI
215 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
216 CONFIG_SYS_CLK_FREQ / 1000000);
217#else
218 printf(" PCI1: disabled\n");
219#endif
220
221 /*
222 * Initialize local bus.
223 */
224 local_bus_init();
225
226 return 0;
227}
228
229
230long int
231initdram(int board_type)
232{
233 long dram_size = 0;
234 extern long spd_sdram (void);
Wolfgang Denk9733b3c2005-08-05 12:19:30 +0200[diff] [blame]235
236 puts("Initializing\n");
237
238#if defined(CONFIG_DDR_DLL)
239 {
Kumar Galaec1340d2007-11-27 23:25:02 -0600[diff] [blame^]240 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Wolfgang Denk9733b3c2005-08-05 12:19:30 +0200[diff] [blame]241 int i,x;
242
243 x = 10;
244
245 /*
246 * Work around to stabilize DDR DLL
247 */
248 gur->ddrdllcr = 0x81000000;
249 asm("sync;isync;msync");
250 udelay (200);
251 while (gur->ddrdllcr != 0x81000100)
252 {
253 gur->devdisr = gur->devdisr | 0x00010000;
254 asm("sync;isync;msync");
255 for (i=0; i<x; i++)
256 ;
257 gur->devdisr = gur->devdisr & 0xfff7ffff;
258 asm("sync;isync;msync");
259 x++;
260 }
261 }
262#endif
263
264#if defined(CONFIG_SPD_EEPROM)
265 dram_size = spd_sdram ();
266#else
267 dram_size = fixed_sdram ();
268#endif
269
270#if defined(CONFIG_DDR_ECC)
271 /*
272 * Initialize and enable DDR ECC.
273 */
274 ddr_enable_ecc(dram_size);
275#endif
276
277 puts(" DDR: ");
278 return dram_size;
279}
280
281
282/*
283 * Initialize Local Bus
284 */
285
286void
287local_bus_init(void)
288{
289 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Kumar Galaec1340d2007-11-27 23:25:02 -0600[diff] [blame^]290 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
Wolfgang Denk9733b3c2005-08-05 12:19:30 +0200[diff] [blame]291 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
292
293 uint clkdiv;
294 uint lbc_hz;
295 sys_info_t sysinfo;
296
297 /*
298 * Errata LBC11.
299 * Fix Local Bus clock glitch when DLL is enabled.
300 *
301 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
302 * If localbus freq is > 133Mhz, DLL can be safely enabled.
303 * Between 66 and 133, the DLL is enabled with an override workaround.
304 */
305
306 get_sys_info(&sysinfo);
307 clkdiv = lbc->lcrr & 0x0f;
308 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
309
310 if (lbc_hz < 66) {
311 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
312
313 } else if (lbc_hz >= 133) {
314 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
315
316 } else {
317 /*
318 * On REV1 boards, need to change CLKDIV before enable DLL.
319 * Default CLKDIV is 8, change it to 4 temporarily.
320 */
321 uint pvr = get_pvr();
322 uint temp_lbcdll = 0;
323
324 if (pvr == PVR_85xx_REV1) {
325 /* FIXME: Justify the high bit here. */
326 lbc->lcrr = 0x10000004;
327 }
328
329 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
330 udelay(200);
331
332 /*
333 * Sample LBC DLL ctrl reg, upshift it to set the
334 * override bits.
335 */
336 temp_lbcdll = gur->lbcdllcr;
337 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
338 asm("sync;isync;msync");
339 }
340}
341
342#if defined(CFG_DRAM_TEST)
343int testdram (void)
344{
345 uint *pstart = (uint *) CFG_MEMTEST_START;
346 uint *pend = (uint *) CFG_MEMTEST_END;
347 uint *p;
348
349 printf("SDRAM test phase 1:\n");
350 for (p = pstart; p < pend; p++)
351 *p = 0xaaaaaaaa;
352
353 for (p = pstart; p < pend; p++) {
354 if (*p != 0xaaaaaaaa) {
355 printf ("SDRAM test fails at: %08x\n", (uint) p);
356 return 1;
357 }
358 }
359
360 printf("SDRAM test phase 2:\n");
361 for (p = pstart; p < pend; p++)
362 *p = 0x55555555;
363
364 for (p = pstart; p < pend; p++) {
365 if (*p != 0x55555555) {
366 printf ("SDRAM test fails at: %08x\n", (uint) p);
367 return 1;
368 }
369 }
370
371 printf("SDRAM test passed.\n");
372 return 0;
373}
374#endif
375
376
377#if !defined(CONFIG_SPD_EEPROM)
378/*************************************************************************
379 * fixed sdram init -- doesn't use serial presence detect.
380 ************************************************************************/
381long int fixed_sdram (void)
382{
383 #ifndef CFG_RAMBOOT
384 volatile immap_t *immap = (immap_t *)CFG_IMMR;
385 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
386
387 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
388 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
389 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
390 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
391 ddr->sdram_mode = CFG_DDR_MODE;
392 ddr->sdram_interval = CFG_DDR_INTERVAL;
393 #if defined (CONFIG_DDR_ECC)
394 ddr->err_disable = 0x0000000D;
395 ddr->err_sbe = 0x00ff0000;
396 #endif
397 asm("sync;isync;msync");
398 udelay(500);
399 #if defined (CONFIG_DDR_ECC)
400 /* Enable ECC checking */
401 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
402 #else
403 ddr->sdram_cfg = CFG_DDR_CONTROL;
404 #endif
405 asm("sync; isync; msync");
406 udelay(500);
407 #endif
408 return CFG_SDRAM_SIZE * 1024 * 1024;
409}
410#endif /* !defined(CONFIG_SPD_EEPROM) */
411
412
413#if defined(CONFIG_PCI)
414/*
415 * Initialize PCI Devices, report devices found.
416 */
417
418#ifndef CONFIG_PCI_PNP
419static struct pci_config_table pci_mpc85xxads_config_table[] = {
420 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
421 PCI_IDSEL_NUMBER, PCI_ANY_ID,
422 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
423 PCI_ENET0_MEMADDR,
424 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
425 } },
426 { }
427};
428#endif
429
430
431static struct pci_controller hose = {
432#ifndef CONFIG_PCI_PNP
433 config_table: pci_mpc85xxads_config_table,
434#endif
435};
436
437#endif /* CONFIG_PCI */
438
439
440void
441pci_init_board(void)
442{
443#ifdef CONFIG_PCI
Wolfgang Denk9733b3c2005-08-05 12:19:30 +0200[diff] [blame]444 pci_mpc85xx_init(&hose);
445#endif /* CONFIG_PCI */
446}