Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - Configuration file for BF533 EZKIT board |
| 3 | */ |
| 4 | |
| 5 | #ifndef __CONFIG_EZKIT533_H__ |
| 6 | #define __CONFIG_EZKIT533_H__ |
| 7 | |
Mike Frysinger | f0dd792 | 2008-02-18 05:26:48 -0500 | [diff] [blame] | 8 | #include <asm/blackfin-config-pre.h> |
| 9 | |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 10 | #define CONFIG_BAUDRATE 57600 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 11 | |
| 12 | #define CONFIG_BOOTDELAY 5 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 13 | #define CONFIG_SYS_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 14 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 15 | #define CONFIG_SYS_LONGHELP 1 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 16 | #define CONFIG_CMDLINE_EDITING 1 |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 17 | #define CONFIG_LOADADDR 0x01000000 /* default load address */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 18 | #define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux" |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 19 | /* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 20 | |
| 21 | #define CONFIG_DRIVER_SMC91111 1 |
| 22 | #define CONFIG_SMC91111_BASE 0x20310300 |
| 23 | |
| 24 | #if 0 |
| 25 | #define CONFIG_MII |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_DISCOVER_PHY |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 27 | #endif |
| 28 | |
| 29 | #define CONFIG_RTC_BFIN 1 |
| 30 | #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ |
| 31 | |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 32 | #define CONFIG_PANIC_HANG 1 |
| 33 | |
Mike Frysinger | f0dd792 | 2008-02-18 05:26:48 -0500 | [diff] [blame] | 34 | #define CONFIG_BFIN_CPU bf533-0.3 |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 35 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 36 | |
| 37 | /* This sets the default state of the cache on U-Boot's boot */ |
| 38 | #define CONFIG_ICACHE_ON |
| 39 | #define CONFIG_DCACHE_ON |
| 40 | |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 41 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 42 | #define CONFIG_CLKIN_HZ 27000000 |
| 43 | /* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ |
| 44 | /* 1=CLKIN/2 */ |
| 45 | #define CONFIG_CLKIN_HALF 0 |
| 46 | /* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ |
| 47 | /* 1=bypass PLL */ |
| 48 | #define CONFIG_PLL_BYPASS 0 |
| 49 | /* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ |
| 50 | /* Values can range from 1-64 */ |
| 51 | #define CONFIG_VCO_MULT 22 |
| 52 | /* CONFIG_CCLK_DIV controls what the core clock divider is */ |
| 53 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| 54 | #define CONFIG_CCLK_DIV 1 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 55 | /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 56 | /* Values can range from 1-15 */ |
| 57 | #define CONFIG_SCLK_DIV 5 |
| 58 | /* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ |
| 59 | /* Values can range from 2-65535 */ |
| 60 | /* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ |
| 61 | #define CONFIG_SPI_BAUD 2 |
| 62 | #define CONFIG_SPI_BAUD_INITBLOCK 4 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 63 | |
| 64 | #if ( CONFIG_CLKIN_HALF == 0 ) |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 65 | #define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 66 | #else |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 67 | #define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 68 | #endif |
| 69 | |
| 70 | #if (CONFIG_PLL_BYPASS == 0) |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 71 | #define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) |
| 72 | #define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 73 | #else |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 74 | #define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
| 75 | #define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 76 | #endif |
| 77 | |
Aubrey Li | 3c56995 | 2007-03-12 00:25:14 +0800 | [diff] [blame] | 78 | #define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 79 | #define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ |
| 80 | #define CONFIG_MEM_MT48LC16M16A2TG_75 1 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 81 | |
| 82 | #define CONFIG_LOADS_ECHO 1 |
| 83 | |
| 84 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 85 | /* |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 86 | * BOOTP options |
| 87 | */ |
| 88 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 89 | #define CONFIG_BOOTP_BOOTPATH |
| 90 | #define CONFIG_BOOTP_GATEWAY |
| 91 | #define CONFIG_BOOTP_HOSTNAME |
| 92 | |
| 93 | |
| 94 | /* |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 95 | * Command line configuration. |
| 96 | */ |
| 97 | #include <config_cmd_default.h> |
| 98 | |
| 99 | #define CONFIG_CMD_PING |
| 100 | #define CONFIG_CMD_ELF |
| 101 | #define CONFIG_CMD_I2C |
| 102 | #define CONFIG_CMD_JFFS2 |
| 103 | #define CONFIG_CMD_DATE |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 104 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 105 | |
| 106 | #define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 107 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_PROMPT "bfin> " /* Monitor Command Prompt */ |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 109 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 111 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 113 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 115 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 116 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 117 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 118 | #define CONFIG_SYS_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */ |
| 119 | #define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */ |
| 120 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 10 ms ticks */ |
| 121 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 122 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 123 | #define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) |
| 124 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 127 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) |
| 128 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 129 | #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) |
| 130 | #define CONFIG_SYS_GBL_DATA_SIZE 0x4000 |
| 131 | #define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) |
| 132 | #define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 135 | #define CONFIG_SYS_FLASH0_BASE 0x20000000 |
| 136 | #define CONFIG_SYS_FLASH1_BASE 0x20200000 |
| 137 | #define CONFIG_SYS_FLASH2_BASE 0x20280000 |
| 138 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
| 139 | #define CONFIG_SYS_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 141 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 142 | #define CONFIG_ENV_ADDR 0x20020000 |
| 143 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 144 | |
| 145 | /* JFFS Partition offset set */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
| 147 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 148 | /* 512k reserved for u-boot */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 150 | |
| 151 | |
| 152 | /* |
| 153 | * Stack sizes |
| 154 | */ |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 155 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 156 | |
| 157 | #define POLL_MODE 1 |
| 158 | #define FLASH_TOT_SECT 40 |
| 159 | #define FLASH_SIZE 0x220000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | #define CONFIG_SYS_FLASH_SIZE 0x220000 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 161 | |
| 162 | /* |
| 163 | * Initialize PSD4256 registers for using I2C |
| 164 | */ |
| 165 | #define CONFIG_MISC_INIT_R |
| 166 | |
| 167 | /* |
| 168 | * I2C settings |
| 169 | * By default PF1 is used as SDA and PF0 as SCL on the Stamp board |
| 170 | */ |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 171 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 172 | /* |
| 173 | * Software (bit-bang) I2C driver configuration |
| 174 | */ |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 175 | #define PF_SCL PF0 |
| 176 | #define PF_SDA PF1 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 177 | |
Aubrey Li | f83a65c | 2007-03-10 23:49:29 +0800 | [diff] [blame] | 178 | #define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") |
| 179 | #define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") |
| 180 | #define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") |
| 181 | #define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") |
| 182 | #define I2C_SDA(bit) if(bit) { \ |
| 183 | *pFIO_FLAG_S = PF_SDA; \ |
| 184 | asm("ssync;"); \ |
| 185 | } \ |
| 186 | else { \ |
| 187 | *pFIO_FLAG_C = PF_SDA; \ |
| 188 | asm("ssync;"); \ |
| 189 | } |
| 190 | #define I2C_SCL(bit) if(bit) { \ |
| 191 | *pFIO_FLAG_S = PF_SCL; \ |
| 192 | asm("ssync;"); \ |
| 193 | } \ |
| 194 | else { \ |
| 195 | *pFIO_FLAG_C = PF_SCL; \ |
| 196 | asm("ssync;"); \ |
| 197 | } |
| 198 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 199 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_I2C_SPEED 50000 |
| 201 | #define CONFIG_SYS_I2C_SLAVE 0xFE |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 202 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 204 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 205 | #define CONFIG_EBIU_SDRRC_VAL 0x398 |
| 206 | #define CONFIG_EBIU_SDGCTL_VAL 0x91118d |
| 207 | #define CONFIG_EBIU_SDBCTL_VAL 0x13 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 208 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 209 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
| 210 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
| 211 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 212 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 213 | #include <asm/blackfin-config-post.h> |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 214 | |
| 215 | #endif |