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wdenkde887eb2003-09-10 18:20:28 +00001/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6 *
wdenkbfad55d2005-03-14 23:56:42 +00007 * Note: Much of this code has been derived from Linux 2.4
8 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
9 * (C) Copyright 2000-2002 David Brownell
10 *
wdenkde887eb2003-09-10 18:20:28 +000011 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 *
wdenkde887eb2003-09-10 18:20:28 +000029 */
30/*
31 * IMPORTANT NOTES
32 * 1 - you MUST define LITTLEENDIAN in the configuration file for the
33 * board or this driver will NOT work!
34 * 2 - this driver is intended for use with USB Mass Storage Devices
35 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
36 */
37
38#include <common.h>
wdenk4ea537d2003-12-07 18:32:37 +000039/* #include <pci.h> no PCI on the S3C24X0 */
wdenkde887eb2003-09-10 18:20:28 +000040
41#ifdef CONFIG_USB_OHCI
42
wdenk4ea537d2003-12-07 18:32:37 +000043#if defined(CONFIG_S3C2400)
wdenkde887eb2003-09-10 18:20:28 +000044#include <s3c2400.h>
wdenk4ea537d2003-12-07 18:32:37 +000045#elif defined(CONFIG_S3C2410)
46#include <s3c2410.h>
47#endif
48
wdenkde887eb2003-09-10 18:20:28 +000049#include <malloc.h>
50#include <usb.h>
51#include "usb_ohci.h"
52
53#define OHCI_USE_NPS /* force NoPowerSwitching mode */
54#undef OHCI_VERBOSE_DEBUG /* not always helpful */
55
wdenkde887eb2003-09-10 18:20:28 +000056/* For initializing controller (mask in an HCFS mode too) */
57#define OHCI_CONTROL_INIT \
58 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
59
wdenkde887eb2003-09-10 18:20:28 +000060#define readl(a) (*((vu_long *)(a)))
61#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
62
63#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
64
65#undef DEBUG
66#ifdef DEBUG
67#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
68#else
69#define dbg(format, arg...) do {} while(0)
70#endif /* DEBUG */
71#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
72#undef SHOW_INFO
73#ifdef SHOW_INFO
74#define info(format, arg...) printf("INFO: " format "\n", ## arg)
75#else
76#define info(format, arg...) do {} while(0)
77#endif
78
79#define m16_swap(x) swap_16(x)
80#define m32_swap(x) swap_32(x)
81
82/* global ohci_t */
83static ohci_t gohci;
84/* this must be aligned to a 256 byte boundary */
85struct ohci_hcca ghcca[1];
86/* a pointer to the aligned storage */
87struct ohci_hcca *phcca;
88/* this allocates EDs for all possible endpoints */
89struct ohci_device ohci_dev;
90/* urb_priv */
91urb_priv_t urb_priv;
dzu8d7e4d12003-09-29 21:55:54 +000092/* RHSC flag */
93int got_rhsc;
94/* device which was disconnected */
95struct usb_device *devgone;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +020096/* flag guarding URB transation */
97int urb_finished = 0;
wdenkde887eb2003-09-10 18:20:28 +000098
99/*-------------------------------------------------------------------------*/
100
101/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
102 * The erratum (#4) description is incorrect. AMD's workaround waits
103 * till some bits (mostly reserved) are clear; ok for all revs.
104 */
105#define OHCI_QUIRK_AMD756 0xabcd
106#define read_roothub(hc, register, mask) ({ \
107 u32 temp = readl (&hc->regs->roothub.register); \
108 if (hc->flags & OHCI_QUIRK_AMD756) \
109 while (temp & mask) \
110 temp = readl (&hc->regs->roothub.register); \
111 temp; })
112
113static u32 roothub_a (struct ohci *hc)
114 { return read_roothub (hc, a, 0xfc0fe000); }
115static inline u32 roothub_b (struct ohci *hc)
116 { return readl (&hc->regs->roothub.b); }
117static inline u32 roothub_status (struct ohci *hc)
118 { return readl (&hc->regs->roothub.status); }
119static u32 roothub_portstatus (struct ohci *hc, int i)
120 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
121
122
123/* forward declaration */
124static int hc_interrupt (void);
125static void
126td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
127 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
128
129/*-------------------------------------------------------------------------*
130 * URB support functions
131 *-------------------------------------------------------------------------*/
132
133/* free HCD-private data associated with this URB */
134
135static void urb_free_priv (urb_priv_t * urb)
136{
137 int i;
138 int last;
139 struct td * td;
140
141 last = urb->length - 1;
142 if (last >= 0) {
143 for (i = 0; i <= last; i++) {
144 td = urb->td[i];
145 if (td) {
146 td->usb_dev = NULL;
147 urb->td[i] = NULL;
148 }
149 }
150 }
151}
152
153/*-------------------------------------------------------------------------*/
154
155#ifdef DEBUG
156static int sohci_get_current_frame_number (struct usb_device * dev);
157
158/* debug| print the main components of an URB
159 * small: 0) header + data packets 1) just header */
160
161static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
162 int transfer_len, struct devrequest * setup, char * str, int small)
163{
164 urb_priv_t * purb = &urb_priv;
165
166 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
167 str,
wdenk9c53f402003-10-15 23:53:47 +0000168 sohci_get_current_frame_number (dev),
169 usb_pipedevice (pipe),
170 usb_pipeendpoint (pipe),
171 usb_pipeout (pipe)? 'O': 'I',
172 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
173 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
174 purb->actual_length,
175 transfer_len, dev->status);
wdenkde887eb2003-09-10 18:20:28 +0000176#ifdef OHCI_VERBOSE_DEBUG
177 if (!small) {
178 int i, len;
179
180 if (usb_pipecontrol (pipe)) {
181 printf (__FILE__ ": cmd(8):");
182 for (i = 0; i < 8 ; i++)
183 printf (" %02x", ((__u8 *) setup) [i]);
184 printf ("\n");
185 }
186 if (transfer_len > 0 && buffer) {
187 printf (__FILE__ ": data(%d/%d):",
188 purb->actual_length,
189 transfer_len);
190 len = usb_pipeout (pipe)?
191 transfer_len: purb->actual_length;
192 for (i = 0; i < 16 && i < len; i++)
193 printf (" %02x", ((__u8 *) buffer) [i]);
194 printf ("%s\n", i < len? "...": "");
195 }
196 }
197#endif
198}
199
200/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
201void ep_print_int_eds (ohci_t *ohci, char * str) {
202 int i, j;
203 __u32 * ed_p;
204 for (i= 0; i < 32; i++) {
205 j = 5;
206 ed_p = &(ohci->hcca->int_table [i]);
207 if (*ed_p == 0)
208 continue;
209 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
210 while (*ed_p != 0 && j--) {
211 ed_t *ed = (ed_t *)m32_swap(ed_p);
212 printf (" ed: %4x;", ed->hwINFO);
213 ed_p = &ed->hwNextED;
214 }
215 printf ("\n");
216 }
217}
218
219static void ohci_dump_intr_mask (char *label, __u32 mask)
220{
221 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
222 label,
223 mask,
224 (mask & OHCI_INTR_MIE) ? " MIE" : "",
225 (mask & OHCI_INTR_OC) ? " OC" : "",
226 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
227 (mask & OHCI_INTR_FNO) ? " FNO" : "",
228 (mask & OHCI_INTR_UE) ? " UE" : "",
229 (mask & OHCI_INTR_RD) ? " RD" : "",
230 (mask & OHCI_INTR_SF) ? " SF" : "",
231 (mask & OHCI_INTR_WDH) ? " WDH" : "",
232 (mask & OHCI_INTR_SO) ? " SO" : ""
233 );
234}
235
236static void maybe_print_eds (char *label, __u32 value)
237{
238 ed_t *edp = (ed_t *)value;
239
240 if (value) {
241 dbg ("%s %08x", label, value);
242 dbg ("%08x", edp->hwINFO);
243 dbg ("%08x", edp->hwTailP);
244 dbg ("%08x", edp->hwHeadP);
245 dbg ("%08x", edp->hwNextED);
246 }
247}
248
249static char * hcfs2string (int state)
250{
251 switch (state) {
252 case OHCI_USB_RESET: return "reset";
253 case OHCI_USB_RESUME: return "resume";
254 case OHCI_USB_OPER: return "operational";
255 case OHCI_USB_SUSPEND: return "suspend";
256 }
257 return "?";
258}
259
260/* dump control and status registers */
261static void ohci_dump_status (ohci_t *controller)
262{
263 struct ohci_regs *regs = controller->regs;
264 __u32 temp;
265
266 temp = readl (&regs->revision) & 0xff;
267 if (temp != 0x10)
268 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
269
270 temp = readl (&regs->control);
271 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
272 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
273 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
274 (temp & OHCI_CTRL_IR) ? " IR" : "",
275 hcfs2string (temp & OHCI_CTRL_HCFS),
276 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
277 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
278 (temp & OHCI_CTRL_IE) ? " IE" : "",
279 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
280 temp & OHCI_CTRL_CBSR
281 );
282
283 temp = readl (&regs->cmdstatus);
284 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
285 (temp & OHCI_SOC) >> 16,
286 (temp & OHCI_OCR) ? " OCR" : "",
287 (temp & OHCI_BLF) ? " BLF" : "",
288 (temp & OHCI_CLF) ? " CLF" : "",
289 (temp & OHCI_HCR) ? " HCR" : ""
290 );
291
292 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
293 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
294
295 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
296
297 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
298 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
299
300 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
301 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
302
303 maybe_print_eds ("donehead", readl (&regs->donehead));
304}
305
306static void ohci_dump_roothub (ohci_t *controller, int verbose)
307{
308 __u32 temp, ndp, i;
309
310 temp = roothub_a (controller);
311 ndp = (temp & RH_A_NDP);
312
313 if (verbose) {
314 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
315 ((temp & RH_A_POTPGT) >> 24) & 0xff,
316 (temp & RH_A_NOCP) ? " NOCP" : "",
317 (temp & RH_A_OCPM) ? " OCPM" : "",
318 (temp & RH_A_DT) ? " DT" : "",
319 (temp & RH_A_NPS) ? " NPS" : "",
320 (temp & RH_A_PSM) ? " PSM" : "",
321 ndp
322 );
323 temp = roothub_b (controller);
324 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
325 temp,
326 (temp & RH_B_PPCM) >> 16,
327 (temp & RH_B_DR)
328 );
329 temp = roothub_status (controller);
330 dbg ("roothub.status: %08x%s%s%s%s%s%s",
331 temp,
332 (temp & RH_HS_CRWE) ? " CRWE" : "",
333 (temp & RH_HS_OCIC) ? " OCIC" : "",
334 (temp & RH_HS_LPSC) ? " LPSC" : "",
335 (temp & RH_HS_DRWE) ? " DRWE" : "",
336 (temp & RH_HS_OCI) ? " OCI" : "",
337 (temp & RH_HS_LPS) ? " LPS" : ""
338 );
339 }
340
341 for (i = 0; i < ndp; i++) {
342 temp = roothub_portstatus (controller, i);
343 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
344 i,
345 temp,
346 (temp & RH_PS_PRSC) ? " PRSC" : "",
347 (temp & RH_PS_OCIC) ? " OCIC" : "",
348 (temp & RH_PS_PSSC) ? " PSSC" : "",
349 (temp & RH_PS_PESC) ? " PESC" : "",
350 (temp & RH_PS_CSC) ? " CSC" : "",
351
352 (temp & RH_PS_LSDA) ? " LSDA" : "",
353 (temp & RH_PS_PPS) ? " PPS" : "",
354 (temp & RH_PS_PRS) ? " PRS" : "",
355 (temp & RH_PS_POCI) ? " POCI" : "",
356 (temp & RH_PS_PSS) ? " PSS" : "",
357
358 (temp & RH_PS_PES) ? " PES" : "",
359 (temp & RH_PS_CCS) ? " CCS" : ""
360 );
361 }
362}
363
364static void ohci_dump (ohci_t *controller, int verbose)
365{
366 dbg ("OHCI controller usb-%s state", controller->slot_name);
367
368 /* dumps some of the state we know about */
369 ohci_dump_status (controller);
370 if (verbose)
371 ep_print_int_eds (controller, "hcca");
372 dbg ("hcca frame #%04x", controller->hcca->frame_no);
373 ohci_dump_roothub (controller, 1);
374}
375
376
377#endif /* DEBUG */
378
379/*-------------------------------------------------------------------------*
380 * Interface functions (URB)
381 *-------------------------------------------------------------------------*/
382
383/* get a transfer request */
384
385int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
386 int transfer_len, struct devrequest *setup, int interval)
387{
388 ohci_t *ohci;
389 ed_t * ed;
390 urb_priv_t *purb_priv;
391 int i, size = 0;
392
393 ohci = &gohci;
394
395 /* when controller's hung, permit only roothub cleanup attempts
396 * such as powering down ports */
397 if (ohci->disabled) {
398 err("sohci_submit_job: EPIPE");
399 return -1;
400 }
401
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200402 /* if we have an unfinished URB from previous transaction let's
403 * fail and scream as quickly as possible so as not to corrupt
404 * further communication */
405 if (!urb_finished) {
406 err("sohci_submit_job: URB NOT FINISHED");
407 return -1;
408 }
409 /* we're about to begin a new transaction here so mark the URB unfinished */
410 urb_finished = 0;
411
wdenkde887eb2003-09-10 18:20:28 +0000412 /* every endpoint has a ed, locate and fill it */
413 if (!(ed = ep_add_ed (dev, pipe))) {
414 err("sohci_submit_job: ENOMEM");
415 return -1;
416 }
417
418 /* for the private part of the URB we need the number of TDs (size) */
419 switch (usb_pipetype (pipe)) {
420 case PIPE_BULK: /* one TD for every 4096 Byte */
421 size = (transfer_len - 1) / 4096 + 1;
422 break;
423 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
424 size = (transfer_len == 0)? 2:
425 (transfer_len - 1) / 4096 + 3;
426 break;
427 }
428
429 if (size >= (N_URB_TD - 1)) {
430 err("need %d TDs, only have %d", size, N_URB_TD);
431 return -1;
432 }
433 purb_priv = &urb_priv;
434 purb_priv->pipe = pipe;
435
436 /* fill the private part of the URB */
437 purb_priv->length = size;
438 purb_priv->ed = ed;
439 purb_priv->actual_length = 0;
440
441 /* allocate the TDs */
442 /* note that td[0] was allocated in ep_add_ed */
443 for (i = 0; i < size; i++) {
444 purb_priv->td[i] = td_alloc (dev);
445 if (!purb_priv->td[i]) {
446 purb_priv->length = i;
447 urb_free_priv (purb_priv);
448 err("sohci_submit_job: ENOMEM");
449 return -1;
450 }
451 }
452
453 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
454 urb_free_priv (purb_priv);
455 err("sohci_submit_job: EINVAL");
456 return -1;
457 }
458
459 /* link the ed into a chain if is not already */
460 if (ed->state != ED_OPER)
461 ep_link (ohci, ed);
462
463 /* fill the TDs and link it to the ed */
464 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
465
466 return 0;
467}
468
469/*-------------------------------------------------------------------------*/
470
471#ifdef DEBUG
472/* tell us the current USB frame number */
473
474static int sohci_get_current_frame_number (struct usb_device *usb_dev)
475{
476 ohci_t *ohci = &gohci;
477
478 return m16_swap (ohci->hcca->frame_no);
479}
480#endif
481
482/*-------------------------------------------------------------------------*
483 * ED handling functions
484 *-------------------------------------------------------------------------*/
485
486/* link an ed into one of the HC chains */
487
488static int ep_link (ohci_t *ohci, ed_t *edi)
489{
490 volatile ed_t *ed = edi;
491
492 ed->state = ED_OPER;
493
494 switch (ed->type) {
495 case PIPE_CONTROL:
496 ed->hwNextED = 0;
497 if (ohci->ed_controltail == NULL) {
498 writel (ed, &ohci->regs->ed_controlhead);
499 } else {
500 ohci->ed_controltail->hwNextED = m32_swap (ed);
501 }
502 ed->ed_prev = ohci->ed_controltail;
503 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
504 !ohci->ed_rm_list[1] && !ohci->sleeping) {
505 ohci->hc_control |= OHCI_CTRL_CLE;
506 writel (ohci->hc_control, &ohci->regs->control);
507 }
508 ohci->ed_controltail = edi;
509 break;
510
511 case PIPE_BULK:
512 ed->hwNextED = 0;
513 if (ohci->ed_bulktail == NULL) {
514 writel (ed, &ohci->regs->ed_bulkhead);
515 } else {
516 ohci->ed_bulktail->hwNextED = m32_swap (ed);
517 }
518 ed->ed_prev = ohci->ed_bulktail;
519 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
520 !ohci->ed_rm_list[1] && !ohci->sleeping) {
521 ohci->hc_control |= OHCI_CTRL_BLE;
522 writel (ohci->hc_control, &ohci->regs->control);
523 }
524 ohci->ed_bulktail = edi;
525 break;
526 }
527 return 0;
528}
529
530/*-------------------------------------------------------------------------*/
531
532/* unlink an ed from one of the HC chains.
533 * just the link to the ed is unlinked.
534 * the link from the ed still points to another operational ed or 0
535 * so the HC can eventually finish the processing of the unlinked ed */
536
537static int ep_unlink (ohci_t *ohci, ed_t *ed)
538{
539 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
540
541 switch (ed->type) {
542 case PIPE_CONTROL:
543 if (ed->ed_prev == NULL) {
544 if (!ed->hwNextED) {
545 ohci->hc_control &= ~OHCI_CTRL_CLE;
546 writel (ohci->hc_control, &ohci->regs->control);
547 }
548 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
549 } else {
550 ed->ed_prev->hwNextED = ed->hwNextED;
551 }
552 if (ohci->ed_controltail == ed) {
553 ohci->ed_controltail = ed->ed_prev;
554 } else {
555 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
556 }
557 break;
558
559 case PIPE_BULK:
560 if (ed->ed_prev == NULL) {
561 if (!ed->hwNextED) {
562 ohci->hc_control &= ~OHCI_CTRL_BLE;
563 writel (ohci->hc_control, &ohci->regs->control);
564 }
565 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
566 } else {
567 ed->ed_prev->hwNextED = ed->hwNextED;
568 }
569 if (ohci->ed_bulktail == ed) {
570 ohci->ed_bulktail = ed->ed_prev;
571 } else {
572 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
573 }
574 break;
575 }
576 ed->state = ED_UNLINK;
577 return 0;
578}
579
580
581/*-------------------------------------------------------------------------*/
582
583/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
584 * but the USB stack is a little bit stateless so we do it at every transaction
585 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
586 * in all other cases the state is left unchanged
587 * the ed info fields are setted anyway even though most of them should not change */
588
589static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
590{
591 td_t *td;
592 ed_t *ed_ret;
593 volatile ed_t *ed;
594
595 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
596 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
597
598 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
599 err("ep_add_ed: pending delete");
600 /* pending delete request */
601 return NULL;
602 }
603
604 if (ed->state == ED_NEW) {
605 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
wdenk9c53f402003-10-15 23:53:47 +0000606 /* dummy td; end of td list for ed */
wdenkde887eb2003-09-10 18:20:28 +0000607 td = td_alloc (usb_dev);
608 ed->hwTailP = m32_swap (td);
609 ed->hwHeadP = ed->hwTailP;
610 ed->state = ED_UNLINK;
611 ed->type = usb_pipetype (pipe);
612 ohci_dev.ed_cnt++;
613 }
614
615 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
616 | usb_pipeendpoint (pipe) << 7
617 | (usb_pipeisoc (pipe)? 0x8000: 0)
618 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
619 | usb_pipeslow (pipe) << 13
620 | usb_maxpacket (usb_dev, pipe) << 16);
621
622 return ed_ret;
623}
624
625/*-------------------------------------------------------------------------*
626 * TD handling functions
627 *-------------------------------------------------------------------------*/
628
629/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
630
631static void td_fill (ohci_t *ohci, unsigned int info,
632 void *data, int len,
633 struct usb_device *dev, int index, urb_priv_t *urb_priv)
634{
635 volatile td_t *td, *td_pt;
636#ifdef OHCI_FILL_TRACE
637 int i;
638#endif
639
640 if (index > urb_priv->length) {
641 err("index > length");
642 return;
643 }
644 /* use this td as the next dummy */
645 td_pt = urb_priv->td [index];
646 td_pt->hwNextTD = 0;
647
648 /* fill the old dummy TD */
649 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
650
651 td->ed = urb_priv->ed;
652 td->next_dl_td = NULL;
653 td->index = index;
654 td->data = (__u32)data;
655#ifdef OHCI_FILL_TRACE
656 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
657 for (i = 0; i < len; i++)
658 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
659 printf("\n");
660 }
661#endif
662 if (!len)
663 data = 0;
664
665 td->hwINFO = m32_swap (info);
666 td->hwCBP = m32_swap (data);
667 if (data)
668 td->hwBE = m32_swap (data + len - 1);
669 else
670 td->hwBE = 0;
671 td->hwNextTD = m32_swap (td_pt);
wdenkde887eb2003-09-10 18:20:28 +0000672
673 /* append to queue */
674 td->ed->hwTailP = td->hwNextTD;
675}
676
677/*-------------------------------------------------------------------------*/
678
679/* prepare all TDs of a transfer */
680
681static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
682 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
683{
684 ohci_t *ohci = &gohci;
685 int data_len = transfer_len;
686 void *data;
687 int cnt = 0;
688 __u32 info = 0;
wdenk9c53f402003-10-15 23:53:47 +0000689 unsigned int toggle = 0;
wdenkde887eb2003-09-10 18:20:28 +0000690
691 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
wdenk9c53f402003-10-15 23:53:47 +0000692 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
693 toggle = TD_T_TOGGLE;
wdenkde887eb2003-09-10 18:20:28 +0000694 } else {
wdenk9c53f402003-10-15 23:53:47 +0000695 toggle = TD_T_DATA0;
wdenkde887eb2003-09-10 18:20:28 +0000696 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
697 }
698 urb->td_cnt = 0;
699 if (data_len)
700 data = buffer;
701 else
702 data = 0;
703
704 switch (usb_pipetype (pipe)) {
705 case PIPE_BULK:
706 info = usb_pipeout (pipe)?
707 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
708 while(data_len > 4096) {
709 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
710 data += 4096; data_len -= 4096; cnt++;
711 }
712 info = usb_pipeout (pipe)?
713 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
714 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
715 cnt++;
716
717 if (!ohci->sleeping)
718 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
719 break;
720
721 case PIPE_CONTROL:
722 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
723 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
724 if (data_len > 0) {
725 info = usb_pipeout (pipe)?
726 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
727 /* NOTE: mishandles transfers >8K, some >4K */
728 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
729 }
730 info = usb_pipeout (pipe)?
731 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
732 td_fill (ohci, info, data, 0, dev, cnt++, urb);
733 if (!ohci->sleeping)
734 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
735 break;
736 }
737 if (urb->length != cnt)
738 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
739}
740
741/*-------------------------------------------------------------------------*
742 * Done List handling functions
743 *-------------------------------------------------------------------------*/
744
745
746/* calculate the transfer length and update the urb */
747
748static void dl_transfer_length(td_t * td)
749{
750 __u32 tdINFO, tdBE, tdCBP;
wdenk9c53f402003-10-15 23:53:47 +0000751 urb_priv_t *lurb_priv = &urb_priv;
wdenkde887eb2003-09-10 18:20:28 +0000752
753 tdINFO = m32_swap (td->hwINFO);
wdenk9c53f402003-10-15 23:53:47 +0000754 tdBE = m32_swap (td->hwBE);
755 tdCBP = m32_swap (td->hwCBP);
wdenkde887eb2003-09-10 18:20:28 +0000756
757
758 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
759 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
760 if (tdBE != 0) {
761 if (td->hwCBP == 0)
762 lurb_priv->actual_length += tdBE - td->data + 1;
763 else
764 lurb_priv->actual_length += tdCBP - td->data;
765 }
766 }
767}
768
769/*-------------------------------------------------------------------------*/
770
771/* replies to the request have to be on a FIFO basis so
772 * we reverse the reversed done-list */
773
774static td_t * dl_reverse_done_list (ohci_t *ohci)
775{
776 __u32 td_list_hc;
777 td_t *td_rev = NULL;
778 td_t *td_list = NULL;
wdenk9c53f402003-10-15 23:53:47 +0000779 urb_priv_t *lurb_priv = NULL;
wdenkde887eb2003-09-10 18:20:28 +0000780
781 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
782 ohci->hcca->done_head = 0;
783
784 while (td_list_hc) {
785 td_list = (td_t *)td_list_hc;
786
787 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
788 lurb_priv = &urb_priv;
789 dbg(" USB-error/status: %x : %p",
790 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
791 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
792 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
793 td_list->ed->hwHeadP =
794 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
795 (td_list->ed->hwHeadP & m32_swap (0x2));
796 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
797 } else
798 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
799 }
800 }
801
802 td_list->next_dl_td = td_rev;
803 td_rev = td_list;
804 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
805 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200806
wdenkde887eb2003-09-10 18:20:28 +0000807 return td_list;
808}
809
810/*-------------------------------------------------------------------------*/
811
812/* td done list */
813static int dl_done_list (ohci_t *ohci, td_t *td_list)
814{
wdenk9c53f402003-10-15 23:53:47 +0000815 td_t *td_list_next = NULL;
wdenkde887eb2003-09-10 18:20:28 +0000816 ed_t *ed;
817 int cc = 0;
818 int stat = 0;
819 /* urb_t *urb; */
820 urb_priv_t *lurb_priv;
wdenk9c53f402003-10-15 23:53:47 +0000821 __u32 tdINFO, edHeadP, edTailP;
wdenkde887eb2003-09-10 18:20:28 +0000822
wdenk9c53f402003-10-15 23:53:47 +0000823 while (td_list) {
824 td_list_next = td_list->next_dl_td;
wdenkde887eb2003-09-10 18:20:28 +0000825
wdenk9c53f402003-10-15 23:53:47 +0000826 lurb_priv = &urb_priv;
827 tdINFO = m32_swap (td_list->hwINFO);
wdenkde887eb2003-09-10 18:20:28 +0000828
wdenk9c53f402003-10-15 23:53:47 +0000829 ed = td_list->ed;
wdenkde887eb2003-09-10 18:20:28 +0000830
wdenk9c53f402003-10-15 23:53:47 +0000831 dl_transfer_length(td_list);
wdenkde887eb2003-09-10 18:20:28 +0000832
wdenk9c53f402003-10-15 23:53:47 +0000833 /* error code of transfer */
834 cc = TD_CC_GET (tdINFO);
wdenkde887eb2003-09-10 18:20:28 +0000835 if (cc != 0) {
836 dbg("ConditionCode %#x", cc);
837 stat = cc_to_error[cc];
838 }
839
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +0200840 /* see if this done list makes for all TD's of current URB,
841 * and mark the URB finished if so */
842 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
843 if ((ed->state & (ED_OPER | ED_UNLINK)))
844 urb_finished = 1;
845 else
846 dbg("dl_done_list: strange.., ED state %x, ed->state\n");
847 } else
848 dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
849 lurb_priv->length);
850
wdenk9c53f402003-10-15 23:53:47 +0000851 if (ed->state != ED_NEW) {
852 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
853 edTailP = m32_swap (ed->hwTailP);
wdenkde887eb2003-09-10 18:20:28 +0000854
855 /* unlink eds if they are not busy */
wdenk9c53f402003-10-15 23:53:47 +0000856 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
857 ep_unlink (ohci, ed);
858 }
wdenkde887eb2003-09-10 18:20:28 +0000859
wdenk9c53f402003-10-15 23:53:47 +0000860 td_list = td_list_next;
861 }
wdenkde887eb2003-09-10 18:20:28 +0000862 return stat;
863}
864
865/*-------------------------------------------------------------------------*
866 * Virtual Root Hub
867 *-------------------------------------------------------------------------*/
868
869/* Device descriptor */
870static __u8 root_hub_dev_des[] =
871{
872 0x12, /* __u8 bLength; */
873 0x01, /* __u8 bDescriptorType; Device */
874 0x10, /* __u16 bcdUSB; v1.1 */
875 0x01,
876 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
877 0x00, /* __u8 bDeviceSubClass; */
878 0x00, /* __u8 bDeviceProtocol; */
879 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
880 0x00, /* __u16 idVendor; */
881 0x00,
882 0x00, /* __u16 idProduct; */
wdenk9c53f402003-10-15 23:53:47 +0000883 0x00,
wdenkde887eb2003-09-10 18:20:28 +0000884 0x00, /* __u16 bcdDevice; */
wdenk9c53f402003-10-15 23:53:47 +0000885 0x00,
wdenkde887eb2003-09-10 18:20:28 +0000886 0x00, /* __u8 iManufacturer; */
887 0x01, /* __u8 iProduct; */
888 0x00, /* __u8 iSerialNumber; */
889 0x01 /* __u8 bNumConfigurations; */
890};
891
892
893/* Configuration descriptor */
894static __u8 root_hub_config_des[] =
895{
896 0x09, /* __u8 bLength; */
897 0x02, /* __u8 bDescriptorType; Configuration */
898 0x19, /* __u16 wTotalLength; */
899 0x00,
900 0x01, /* __u8 bNumInterfaces; */
901 0x01, /* __u8 bConfigurationValue; */
902 0x00, /* __u8 iConfiguration; */
903 0x40, /* __u8 bmAttributes;
wdenk9c53f402003-10-15 23:53:47 +0000904 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
wdenkde887eb2003-09-10 18:20:28 +0000905 0x00, /* __u8 MaxPower; */
906
907 /* interface */
908 0x09, /* __u8 if_bLength; */
909 0x04, /* __u8 if_bDescriptorType; Interface */
910 0x00, /* __u8 if_bInterfaceNumber; */
911 0x00, /* __u8 if_bAlternateSetting; */
912 0x01, /* __u8 if_bNumEndpoints; */
913 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
914 0x00, /* __u8 if_bInterfaceSubClass; */
915 0x00, /* __u8 if_bInterfaceProtocol; */
916 0x00, /* __u8 if_iInterface; */
917
918 /* endpoint */
919 0x07, /* __u8 ep_bLength; */
920 0x05, /* __u8 ep_bDescriptorType; Endpoint */
921 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
wdenk9c53f402003-10-15 23:53:47 +0000922 0x03, /* __u8 ep_bmAttributes; Interrupt */
923 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
924 0x00,
wdenkde887eb2003-09-10 18:20:28 +0000925 0xff /* __u8 ep_bInterval; 255 ms */
926};
927
928static unsigned char root_hub_str_index0[] =
929{
930 0x04, /* __u8 bLength; */
931 0x03, /* __u8 bDescriptorType; String-descriptor */
932 0x09, /* __u8 lang ID */
933 0x04, /* __u8 lang ID */
934};
935
936static unsigned char root_hub_str_index1[] =
937{
938 28, /* __u8 bLength; */
939 0x03, /* __u8 bDescriptorType; String-descriptor */
940 'O', /* __u8 Unicode */
941 0, /* __u8 Unicode */
942 'H', /* __u8 Unicode */
943 0, /* __u8 Unicode */
944 'C', /* __u8 Unicode */
945 0, /* __u8 Unicode */
946 'I', /* __u8 Unicode */
947 0, /* __u8 Unicode */
948 ' ', /* __u8 Unicode */
949 0, /* __u8 Unicode */
950 'R', /* __u8 Unicode */
951 0, /* __u8 Unicode */
952 'o', /* __u8 Unicode */
953 0, /* __u8 Unicode */
954 'o', /* __u8 Unicode */
955 0, /* __u8 Unicode */
956 't', /* __u8 Unicode */
957 0, /* __u8 Unicode */
958 ' ', /* __u8 Unicode */
959 0, /* __u8 Unicode */
960 'H', /* __u8 Unicode */
961 0, /* __u8 Unicode */
962 'u', /* __u8 Unicode */
963 0, /* __u8 Unicode */
964 'b', /* __u8 Unicode */
965 0, /* __u8 Unicode */
966};
967
968/* Hub class-specific descriptor is constructed dynamically */
969
970
971/*-------------------------------------------------------------------------*/
972
973#define OK(x) len = (x); break
974#ifdef DEBUG
975#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
976#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
977#else
978#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
979#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
980#endif
981#define RD_RH_STAT roothub_status(&gohci)
982#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
983
984/* request to virtual root hub */
985
dzu8d7e4d12003-09-29 21:55:54 +0000986int rh_check_port_status(ohci_t *controller)
987{
988 __u32 temp, ndp, i;
989 int res;
990
991 res = -1;
992 temp = roothub_a (controller);
993 ndp = (temp & RH_A_NDP);
994 for (i = 0; i < ndp; i++) {
995 temp = roothub_portstatus (controller, i);
996 /* check for a device disconnect */
997 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
998 (RH_PS_PESC | RH_PS_CSC)) &&
999 ((temp & RH_PS_CCS) == 0)) {
1000 res = i;
1001 break;
1002 }
1003 }
1004 return res;
1005}
1006
1007static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1008 void *buffer, int transfer_len, struct devrequest *cmd)
wdenkde887eb2003-09-10 18:20:28 +00001009{
1010 void * data = buffer;
1011 int leni = transfer_len;
1012 int len = 0;
1013 int stat = 0;
1014 __u32 datab[4];
1015 __u8 *data_buf = (__u8 *)datab;
wdenk9c53f402003-10-15 23:53:47 +00001016 __u16 bmRType_bReq;
wdenkde887eb2003-09-10 18:20:28 +00001017 __u16 wValue;
1018 __u16 wIndex;
1019 __u16 wLength;
1020
1021#ifdef DEBUG
1022urb_priv.actual_length = 0;
1023pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1024#else
1025 wait_ms(1);
1026#endif
1027 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1028 info("Root-Hub submit IRQ: NOT implemented");
1029 return 0;
1030 }
1031
1032 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1033 wValue = m16_swap (cmd->value);
1034 wIndex = m16_swap (cmd->index);
1035 wLength = m16_swap (cmd->length);
1036
1037 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1038 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1039
1040 switch (bmRType_bReq) {
1041 /* Request Destination:
1042 without flags: Device,
1043 RH_INTERFACE: interface,
1044 RH_ENDPOINT: endpoint,
1045 RH_CLASS means HUB here,
1046 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1047 */
1048
1049 case RH_GET_STATUS:
1050 *(__u16 *) data_buf = m16_swap (1); OK (2);
1051 case RH_GET_STATUS | RH_INTERFACE:
1052 *(__u16 *) data_buf = m16_swap (0); OK (2);
1053 case RH_GET_STATUS | RH_ENDPOINT:
1054 *(__u16 *) data_buf = m16_swap (0); OK (2);
1055 case RH_GET_STATUS | RH_CLASS:
1056 *(__u32 *) data_buf = m32_swap (
1057 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1058 OK (4);
1059 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1060 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1061
1062 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1063 switch (wValue) {
1064 case (RH_ENDPOINT_STALL): OK (0);
1065 }
1066 break;
1067
1068 case RH_CLEAR_FEATURE | RH_CLASS:
1069 switch (wValue) {
1070 case RH_C_HUB_LOCAL_POWER:
1071 OK(0);
1072 case (RH_C_HUB_OVER_CURRENT):
1073 WR_RH_STAT(RH_HS_OCIC); OK (0);
1074 }
1075 break;
1076
1077 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1078 switch (wValue) {
1079 case (RH_PORT_ENABLE):
1080 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1081 case (RH_PORT_SUSPEND):
1082 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1083 case (RH_PORT_POWER):
1084 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1085 case (RH_C_PORT_CONNECTION):
1086 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1087 case (RH_C_PORT_ENABLE):
1088 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1089 case (RH_C_PORT_SUSPEND):
1090 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1091 case (RH_C_PORT_OVER_CURRENT):
1092 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1093 case (RH_C_PORT_RESET):
1094 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1095 }
1096 break;
1097
1098 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1099 switch (wValue) {
1100 case (RH_PORT_SUSPEND):
1101 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1102 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1103 if (RD_RH_PORTSTAT & RH_PS_CCS)
1104 WR_RH_PORTSTAT (RH_PS_PRS);
1105 OK (0);
1106 case (RH_PORT_POWER):
1107 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1108 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1109 if (RD_RH_PORTSTAT & RH_PS_CCS)
1110 WR_RH_PORTSTAT (RH_PS_PES );
1111 OK (0);
1112 }
1113 break;
1114
1115 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1116
1117 case RH_GET_DESCRIPTOR:
1118 switch ((wValue & 0xff00) >> 8) {
1119 case (0x01): /* device descriptor */
1120 len = min_t(unsigned int,
1121 leni,
1122 min_t(unsigned int,
1123 sizeof (root_hub_dev_des),
1124 wLength));
1125 data_buf = root_hub_dev_des; OK(len);
1126 case (0x02): /* configuration descriptor */
1127 len = min_t(unsigned int,
1128 leni,
1129 min_t(unsigned int,
1130 sizeof (root_hub_config_des),
1131 wLength));
1132 data_buf = root_hub_config_des; OK(len);
1133 case (0x03): /* string descriptors */
1134 if(wValue==0x0300) {
1135 len = min_t(unsigned int,
1136 leni,
1137 min_t(unsigned int,
1138 sizeof (root_hub_str_index0),
1139 wLength));
1140 data_buf = root_hub_str_index0;
1141 OK(len);
1142 }
1143 if(wValue==0x0301) {
1144 len = min_t(unsigned int,
1145 leni,
1146 min_t(unsigned int,
1147 sizeof (root_hub_str_index1),
1148 wLength));
1149 data_buf = root_hub_str_index1;
1150 OK(len);
1151 }
1152 default:
1153 stat = USB_ST_STALLED;
1154 }
1155 break;
1156
1157 case RH_GET_DESCRIPTOR | RH_CLASS:
1158 {
1159 __u32 temp = roothub_a (&gohci);
1160
1161 data_buf [0] = 9; /* min length; */
1162 data_buf [1] = 0x29;
1163 data_buf [2] = temp & RH_A_NDP;
1164 data_buf [3] = 0;
1165 if (temp & RH_A_PSM) /* per-port power switching? */
1166 data_buf [3] |= 0x1;
1167 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1168 data_buf [3] |= 0x10;
1169 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1170 data_buf [3] |= 0x8;
1171
1172 /* corresponds to data_buf[4-7] */
1173 datab [1] = 0;
1174 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1175 temp = roothub_b (&gohci);
1176 data_buf [7] = temp & RH_B_DR;
1177 if (data_buf [2] < 7) {
1178 data_buf [8] = 0xff;
1179 } else {
1180 data_buf [0] += 2;
1181 data_buf [8] = (temp & RH_B_DR) >> 8;
1182 data_buf [10] = data_buf [9] = 0xff;
1183 }
1184
1185 len = min_t(unsigned int, leni,
1186 min_t(unsigned int, data_buf [0], wLength));
1187 OK (len);
1188 }
1189
1190 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1191
1192 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1193
1194 default:
1195 dbg ("unsupported root hub command");
1196 stat = USB_ST_STALLED;
1197 }
1198
1199#ifdef DEBUG
1200 ohci_dump_roothub (&gohci, 1);
1201#else
1202 wait_ms(1);
1203#endif
1204
1205 len = min_t(int, len, leni);
1206 if (data != data_buf)
1207 memcpy (data, data_buf, len);
wdenk9c53f402003-10-15 23:53:47 +00001208 dev->act_len = len;
wdenkde887eb2003-09-10 18:20:28 +00001209 dev->status = stat;
1210
1211#ifdef DEBUG
1212 if (transfer_len)
1213 urb_priv.actual_length = transfer_len;
1214 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1215#else
1216 wait_ms(1);
1217#endif
1218
1219 return stat;
1220}
1221
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001222
wdenkde887eb2003-09-10 18:20:28 +00001223/*-------------------------------------------------------------------------*/
1224
1225/* common code for handling submit messages - used for all but root hub */
1226/* accesses. */
1227int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1228 int transfer_len, struct devrequest *setup, int interval)
1229{
1230 int stat = 0;
1231 int maxsize = usb_maxpacket(dev, pipe);
1232 int timeout;
1233
dzu8d7e4d12003-09-29 21:55:54 +00001234 /* device pulled? Shortcut the action. */
1235 if (devgone == dev) {
1236 dev->status = USB_ST_CRC_ERR;
1237 return 0;
1238 }
1239
wdenkde887eb2003-09-10 18:20:28 +00001240#ifdef DEBUG
1241 urb_priv.actual_length = 0;
1242 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1243#else
1244 wait_ms(1);
1245#endif
1246 if (!maxsize) {
1247 err("submit_common_message: pipesize for pipe %lx is zero",
1248 pipe);
1249 return -1;
1250 }
1251
1252 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1253 err("sohci_submit_job failed");
1254 return -1;
1255 }
1256
1257 wait_ms(10);
1258 /* ohci_dump_status(&gohci); */
wdenk9c53f402003-10-15 23:53:47 +00001259
wdenk934c4f82003-09-11 19:48:06 +00001260 /* allow more time for a BULK device to react - some are slow */
wdenkb6b2f0e2003-09-17 22:48:07 +00001261#define BULK_TO 5000 /* timeout in milliseconds */
wdenk934c4f82003-09-11 19:48:06 +00001262 if (usb_pipetype (pipe) == PIPE_BULK)
1263 timeout = BULK_TO;
1264 else
1265 timeout = 100;
1266
wdenkde887eb2003-09-10 18:20:28 +00001267 /* wait for it to complete */
wdenkde887eb2003-09-10 18:20:28 +00001268 for (;;) {
1269 /* check whether the controller is done */
1270 stat = hc_interrupt();
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001271
wdenkde887eb2003-09-10 18:20:28 +00001272 if (stat < 0) {
dzu8d7e4d12003-09-29 21:55:54 +00001273 stat = USB_ST_CRC_ERR;
wdenkde887eb2003-09-10 18:20:28 +00001274 break;
1275 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001276
1277 /* NOTE: since we are not interrupt driven in U-Boot and always
1278 * handle only one URB at a time, we cannot assume the
1279 * transaction finished on the first successful return from
1280 * hc_interrupt().. unless the flag for current URB is set,
1281 * meaning that all TD's to/from device got actually
1282 * transferred and processed. If the current URB is not
1283 * finished we need to re-iterate this loop so as
1284 * hc_interrupt() gets called again as there needs to be some
1285 * more TD's to process still */
1286 if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
wdenkde887eb2003-09-10 18:20:28 +00001287 /* 0xff is returned for an SF-interrupt */
1288 break;
1289 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001290
wdenkde887eb2003-09-10 18:20:28 +00001291 if (--timeout) {
1292 wait_ms(1);
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001293 if (!urb_finished)
1294 dbg("\%");
Jon Loeligerebc72242005-08-01 13:20:47 -05001295
wdenkde887eb2003-09-10 18:20:28 +00001296 } else {
dzu8d7e4d12003-09-29 21:55:54 +00001297 err("CTL:TIMEOUT ");
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001298 dbg("submit_common_msg: TO status %x\n", stat);
dzu8d7e4d12003-09-29 21:55:54 +00001299 stat = USB_ST_CRC_ERR;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001300 urb_finished = 1;
wdenkde887eb2003-09-10 18:20:28 +00001301 break;
1302 }
1303 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001304
1305#if 0
dzu8d7e4d12003-09-29 21:55:54 +00001306 /* we got an Root Hub Status Change interrupt */
1307 if (got_rhsc) {
1308#ifdef DEBUG
1309 ohci_dump_roothub (&gohci, 1);
1310#endif
1311 got_rhsc = 0;
1312 /* abuse timeout */
1313 timeout = rh_check_port_status(&gohci);
1314 if (timeout >= 0) {
1315#if 0 /* this does nothing useful, but leave it here in case that changes */
1316 /* the called routine adds 1 to the passed value */
1317 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1318#endif
1319 /*
1320 * XXX
1321 * This is potentially dangerous because it assumes
1322 * that only one device is ever plugged in!
1323 */
1324 devgone = dev;
1325 }
1326 }
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001327#endif
dzu8d7e4d12003-09-29 21:55:54 +00001328
wdenkde887eb2003-09-10 18:20:28 +00001329 dev->status = stat;
wdenk9c53f402003-10-15 23:53:47 +00001330 dev->act_len = transfer_len;
wdenkde887eb2003-09-10 18:20:28 +00001331
1332#ifdef DEBUG
1333 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1334#else
1335 wait_ms(1);
1336#endif
1337
1338 /* free TDs in urb_priv */
1339 urb_free_priv (&urb_priv);
1340 return 0;
1341}
1342
1343/* submit routines called from usb.c */
1344int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1345 int transfer_len)
1346{
1347 info("submit_bulk_msg");
1348 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1349}
1350
1351int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1352 int transfer_len, struct devrequest *setup)
1353{
1354 int maxsize = usb_maxpacket(dev, pipe);
1355
1356 info("submit_control_msg");
1357#ifdef DEBUG
1358 urb_priv.actual_length = 0;
1359 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1360#else
1361 wait_ms(1);
1362#endif
1363 if (!maxsize) {
1364 err("submit_control_message: pipesize for pipe %lx is zero",
1365 pipe);
1366 return -1;
1367 }
dzu8d7e4d12003-09-29 21:55:54 +00001368 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1369 gohci.rh.dev = dev;
wdenkde887eb2003-09-10 18:20:28 +00001370 /* root hub - redirect */
1371 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1372 setup);
dzu8d7e4d12003-09-29 21:55:54 +00001373 }
wdenkde887eb2003-09-10 18:20:28 +00001374
1375 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1376}
1377
1378int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1379 int transfer_len, int interval)
1380{
1381 info("submit_int_msg");
1382 return -1;
1383}
1384
1385/*-------------------------------------------------------------------------*
1386 * HC functions
1387 *-------------------------------------------------------------------------*/
1388
1389/* reset the HC and BUS */
1390
1391static int hc_reset (ohci_t *ohci)
1392{
1393 int timeout = 30;
1394 int smm_timeout = 50; /* 0,5 sec */
1395
1396 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1397 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1398 info("USB HC TakeOver from SMM");
1399 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1400 wait_ms (10);
1401 if (--smm_timeout == 0) {
1402 err("USB HC TakeOver failed!");
1403 return -1;
1404 }
1405 }
1406 }
1407
1408 /* Disable HC interrupts */
1409 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1410
1411 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1412 ohci->slot_name,
1413 readl (&ohci->regs->control));
1414
wdenk9c53f402003-10-15 23:53:47 +00001415 /* Reset USB (needed by some controllers) */
wdenkde887eb2003-09-10 18:20:28 +00001416 writel (0, &ohci->regs->control);
1417
1418 /* HC Reset requires max 10 us delay */
1419 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1420 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1421 if (--timeout == 0) {
1422 err("USB HC reset timed out!");
1423 return -1;
1424 }
1425 udelay (1);
1426 }
1427 return 0;
1428}
1429
1430/*-------------------------------------------------------------------------*/
1431
1432/* Start an OHCI controller, set the BUS operational
1433 * enable interrupts
1434 * connect the virtual root hub */
1435
1436static int hc_start (ohci_t * ohci)
1437{
wdenk9c53f402003-10-15 23:53:47 +00001438 __u32 mask;
1439 unsigned int fminterval;
wdenkde887eb2003-09-10 18:20:28 +00001440
1441 ohci->disabled = 1;
1442
1443 /* Tell the controller where the control and bulk lists are
1444 * The lists are empty now. */
1445
1446 writel (0, &ohci->regs->ed_controlhead);
1447 writel (0, &ohci->regs->ed_bulkhead);
1448
1449 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1450
wdenk9c53f402003-10-15 23:53:47 +00001451 fminterval = 0x2edf;
wdenkde887eb2003-09-10 18:20:28 +00001452 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1453 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1454 writel (fminterval, &ohci->regs->fminterval);
1455 writel (0x628, &ohci->regs->lsthresh);
1456
wdenk9c53f402003-10-15 23:53:47 +00001457 /* start controller operations */
1458 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
wdenkde887eb2003-09-10 18:20:28 +00001459 ohci->disabled = 0;
wdenk9c53f402003-10-15 23:53:47 +00001460 writel (ohci->hc_control, &ohci->regs->control);
wdenkde887eb2003-09-10 18:20:28 +00001461
dzu8d7e4d12003-09-29 21:55:54 +00001462 /* disable all interrupts */
1463 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1464 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1465 OHCI_INTR_OC | OHCI_INTR_MIE);
1466 writel (mask, &ohci->regs->intrdisable);
1467 /* clear all interrupts */
1468 mask &= ~OHCI_INTR_MIE;
wdenkde887eb2003-09-10 18:20:28 +00001469 writel (mask, &ohci->regs->intrstatus);
dzu8d7e4d12003-09-29 21:55:54 +00001470 /* Choose the interrupts we care about now - but w/o MIE */
1471 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1472 writel (mask, &ohci->regs->intrenable);
wdenkde887eb2003-09-10 18:20:28 +00001473
1474#ifdef OHCI_USE_NPS
1475 /* required for AMD-756 and some Mac platforms */
1476 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1477 &ohci->regs->roothub.a);
1478 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1479#endif /* OHCI_USE_NPS */
1480
1481#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1482 /* POTPGT delay is bits 24-31, in 2 ms units. */
1483 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1484
1485 /* connect the virtual root hub */
1486 ohci->rh.devnum = 0;
1487
1488 return 0;
1489}
1490
1491/*-------------------------------------------------------------------------*/
1492
1493/* an interrupt happens */
1494
1495static int
1496hc_interrupt (void)
1497{
1498 ohci_t *ohci = &gohci;
1499 struct ohci_regs *regs = ohci->regs;
wdenk9c53f402003-10-15 23:53:47 +00001500 int ints;
wdenkde887eb2003-09-10 18:20:28 +00001501 int stat = -1;
1502
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001503 if ((ohci->hcca->done_head != 0) &&
1504 !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1505
wdenkde887eb2003-09-10 18:20:28 +00001506 ints = OHCI_INTR_WDH;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001507
1508 } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1509 ohci->disabled++;
1510 err ("%s device removed!", ohci->slot_name);
1511 return -1;
Jon Loeligerebc72242005-08-01 13:20:47 -05001512
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001513 } else if ((ints &= readl (&regs->intrenable)) == 0) {
1514 dbg("hc_interrupt: returning..\n");
1515 return 0xff;
wdenkde887eb2003-09-10 18:20:28 +00001516 }
1517
1518 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1519
dzu8d7e4d12003-09-29 21:55:54 +00001520 if (ints & OHCI_INTR_RHSC) {
1521 got_rhsc = 1;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001522 stat = 0xff;
dzu8d7e4d12003-09-29 21:55:54 +00001523 }
1524
wdenkde887eb2003-09-10 18:20:28 +00001525 if (ints & OHCI_INTR_UE) {
1526 ohci->disabled++;
1527 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1528 ohci->slot_name);
1529 /* e.g. due to PCI Master/Target Abort */
1530
1531#ifdef DEBUG
1532 ohci_dump (ohci, 1);
1533#else
1534 wait_ms(1);
1535#endif
1536 /* FIXME: be optimistic, hope that bug won't repeat often. */
1537 /* Make some non-interrupt context restart the controller. */
1538 /* Count and limit the retries though; either hardware or */
1539 /* software errors can go forever... */
1540 hc_reset (ohci);
1541 return -1;
1542 }
1543
1544 if (ints & OHCI_INTR_WDH) {
1545 wait_ms(1);
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001546
wdenkde887eb2003-09-10 18:20:28 +00001547 writel (OHCI_INTR_WDH, &regs->intrdisable);
1548 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1549 writel (OHCI_INTR_WDH, &regs->intrenable);
1550 }
1551
1552 if (ints & OHCI_INTR_SO) {
1553 dbg("USB Schedule overrun\n");
1554 writel (OHCI_INTR_SO, &regs->intrenable);
1555 stat = -1;
1556 }
1557
1558 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1559 if (ints & OHCI_INTR_SF) {
1560 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1561 wait_ms(1);
1562 writel (OHCI_INTR_SF, &regs->intrdisable);
1563 if (ohci->ed_rm_list[frame] != NULL)
1564 writel (OHCI_INTR_SF, &regs->intrenable);
1565 stat = 0xff;
1566 }
1567
1568 writel (ints, &regs->intrstatus);
1569 return stat;
1570}
1571
1572/*-------------------------------------------------------------------------*/
1573
1574/*-------------------------------------------------------------------------*/
1575
1576/* De-allocate all resources.. */
1577
1578static void hc_release_ohci (ohci_t *ohci)
1579{
1580 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1581
1582 if (!ohci->disabled)
1583 hc_reset (ohci);
1584}
1585
1586/*-------------------------------------------------------------------------*/
1587
1588/*
1589 * low level initalisation routine, called from usb.c
1590 */
1591static char ohci_inited = 0;
1592
1593int usb_lowlevel_init(void)
1594{
1595 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1596 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1597
wdenk9c53f402003-10-15 23:53:47 +00001598 /*
1599 * Set the 48 MHz UPLL clocking. Values are taken from
1600 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1601 */
1602 clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
1603 gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
wdenkde887eb2003-09-10 18:20:28 +00001604
wdenk9c53f402003-10-15 23:53:47 +00001605 /*
1606 * Enable USB host clock.
1607 */
1608 clk_power->CLKCON |= (1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001609
1610 memset (&gohci, 0, sizeof (ohci_t));
1611 memset (&urb_priv, 0, sizeof (urb_priv_t));
1612
1613 /* align the storage */
1614 if ((__u32)&ghcca[0] & 0xff) {
1615 err("HCCA not aligned!!");
1616 return -1;
1617 }
1618 phcca = &ghcca[0];
1619 info("aligned ghcca %p", phcca);
1620 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1621 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1622 err("EDs not aligned!!");
1623 return -1;
1624 }
1625 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1626 if ((__u32)gtd & 0x7) {
1627 err("TDs not aligned!!");
1628 return -1;
1629 }
1630 ptd = gtd;
1631 gohci.hcca = phcca;
wdenk9c53f402003-10-15 23:53:47 +00001632 memset (phcca, 0, sizeof (struct ohci_hcca));
wdenkde887eb2003-09-10 18:20:28 +00001633
1634 gohci.disabled = 1;
1635 gohci.sleeping = 0;
1636 gohci.irq = -1;
1637 gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1638
1639 gohci.flags = 0;
1640 gohci.slot_name = "s3c2400";
1641
1642 if (hc_reset (&gohci) < 0) {
1643 hc_release_ohci (&gohci);
wdenk9c53f402003-10-15 23:53:47 +00001644 /* Initialization failed */
1645 clk_power->CLKCON &= ~(1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001646 return -1;
1647 }
1648
1649 /* FIXME this is a second HC reset; why?? */
1650 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1651 wait_ms (10);
1652
1653 if (hc_start (&gohci) < 0) {
1654 err ("can't start usb-%s", gohci.slot_name);
1655 hc_release_ohci (&gohci);
wdenk9c53f402003-10-15 23:53:47 +00001656 /* Initialization failed */
1657 clk_power->CLKCON &= ~(1 << 4);
wdenkde887eb2003-09-10 18:20:28 +00001658 return -1;
1659 }
1660
1661#ifdef DEBUG
1662 ohci_dump (&gohci, 1);
1663#else
1664 wait_ms(1);
1665#endif
1666 ohci_inited = 1;
Wolfgang Denkc7a4f7d2005-07-21 11:57:57 +02001667 urb_finished = 1;
1668
wdenkde887eb2003-09-10 18:20:28 +00001669 return 0;
1670}
1671
1672int usb_lowlevel_stop(void)
1673{
1674 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1675
1676 /* this gets called really early - before the controller has */
1677 /* even been initialized! */
1678 if (!ohci_inited)
1679 return 0;
1680 /* TODO release any interrupts, etc. */
1681 /* call hc_release_ohci() here ? */
1682 hc_reset (&gohci);
1683 /* may not want to do this */
1684 clk_power->CLKCON &= ~(1 << 4);
1685 return 0;
1686}
1687
1688#endif /* CONFIG_USB_OHCI */